From 901cf5ffcbb93a2003f48ccd087fafb5c45a1bb0 Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Tue, 2 Oct 2018 16:30:06 -0400 Subject: [PATCH] gpu: nvgpu: fifo_gk20a: fix some declaration types This fixes some declarations in fifo_gk20a that resulted in MISRA 10.3 violations. MISRA 10.3 prohibits implicit assignment between types. JIRA NVGPU-647 Change-Id: I28df83a73c5530c37275cdd36c6c56d03a1ccadd Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/1917633 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 20 ++++++++++++++------ drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 6 +++--- 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index b6b3e14df..05346d240 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -45,6 +45,7 @@ #include #include #include +#include #include "gk20a.h" #include "mm_gk20a.h" @@ -695,7 +696,7 @@ static int init_runlist(struct gk20a *g, struct fifo_gk20a *f) u32 i; size_t runlist_size; u32 active_engine_id, pbdma_id, engine_id; - int flags = nvgpu_is_enabled(g, NVGPU_MM_USE_PHYSICAL_SG) ? + u32 flags = nvgpu_is_enabled(g, NVGPU_MM_USE_PHYSICAL_SG) ? NVGPU_DMA_FORCE_CONTIGUOUS : 0; int err = 0; @@ -1895,7 +1896,7 @@ static bool gk20a_fifo_handle_mmu_fault( return verbose; } -static void gk20a_fifo_get_faulty_id_type(struct gk20a *g, int engine_id, +static void gk20a_fifo_get_faulty_id_type(struct gk20a *g, u32 engine_id, u32 *id, u32 *type) { u32 status = gk20a_readl(g, fifo_engine_status_r(engine_id)); @@ -2018,7 +2019,7 @@ void gk20a_fifo_teardown_ch_tsg(struct gk20a *g, u32 __engine_ids, u32 mmu_fault_engines = 0; u32 ref_type; u32 ref_id; - u32 ref_id_is_tsg = false; + bool ref_id_is_tsg = false; bool id_is_known = (id_type != ID_TYPE_UNKNOWN) ? true : false; bool id_is_tsg = (id_type == ID_TYPE_TSG) ? true : false; u32 rlid; @@ -2244,10 +2245,10 @@ fail_enable_tsg: } u32 gk20a_fifo_get_failing_engine_data(struct gk20a *g, - int *__id, bool *__is_tsg) + u32 *__id, bool *__is_tsg) { u32 engine_id; - int id = -1; + u32 id = U32_MAX; bool is_tsg = false; u32 mailbox2; u32 active_engine_id = FIFO_INVAL_ENGINE_ID; @@ -2413,7 +2414,7 @@ bool gk20a_fifo_handle_sched_error(struct gk20a *g) { u32 sched_error; u32 engine_id; - int id = -1; + u32 id = U32_MAX; bool is_tsg = false; bool ret = false; @@ -2436,6 +2437,13 @@ bool gk20a_fifo_handle_sched_error(struct gk20a *g) u32 ms = 0; bool verbose = false; + if (id > f->num_channels) { + nvgpu_err(g, "fifo sched error : channel id invalid %u", + id); + ret = false; + goto err; + } + if (is_tsg) { ret = g->ops.fifo.check_tsg_ctxsw_timeout( &f->tsg[id], &verbose, &ms); diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index d532a840f..d1ac1c007 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h @@ -46,8 +46,8 @@ enum { #define FIFO_INVAL_TSG_ID ((u32)~0) #define FIFO_INVAL_RUNLIST_ID ((u32)~0) -#define ID_TYPE_CHANNEL 0 -#define ID_TYPE_TSG 1 +#define ID_TYPE_CHANNEL 0U +#define ID_TYPE_TSG 1U #define ID_TYPE_UNKNOWN ((u32)~0) #define RC_YES 1 @@ -285,7 +285,7 @@ u32 gk20a_fifo_engine_interrupt_mask(struct gk20a *g); u32 gk20a_fifo_act_eng_interrupt_mask(struct gk20a *g, u32 act_eng_id); u32 gk20a_fifo_get_pbdma_signature(struct gk20a *g); u32 gk20a_fifo_get_failing_engine_data(struct gk20a *g, - int *__id, bool *__is_tsg); + u32 *__id, bool *__is_tsg); void gk20a_fifo_set_ctx_mmu_error_tsg(struct gk20a *g, struct tsg_gk20a *tsg); void gk20a_fifo_abort_tsg(struct gk20a *g, u32 tsgid, bool preempt);