From 90a974d2711354186077427dd35a6655e67c848e Mon Sep 17 00:00:00 2001 From: Abdul Salam Date: Thu, 23 Jan 2020 13:06:33 +0530 Subject: [PATCH] gpu: nvgpu: Refactor Volt sub-unit As a part of refactoring, we need to move the volt functions from pmu_pstate.c to volt.c as it belongs there and also move the arbitor specific functions under CLK_ARB as they will be removed from safety build. This patch does the following *Move volt setup from pmu_pstate to volt *Move clk freq related functions into CLK_ARB *Replace pmu.h with nvgpu_mem.h in boardobj.h *Rename obj_volt to nvgpu_pmu_volt NVGPU-4491 NVGPU-4492 Change-Id: I9abc96f695fce41893311982a80dc3656aaa64d6 Signed-off-by: Abdul Salam Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2282361 Reviewed-by: Ramesh Mylavarapu Reviewed-by: Vaibhav Kachore Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- arch/nvgpu-common.yaml | 7 +- drivers/gpu/nvgpu/Makefile | 2 +- drivers/gpu/nvgpu/Makefile.sources | 4 +- drivers/gpu/nvgpu/common/pmu/pmu_pstate.c | 60 +--------------- .../common/pmu/volt/{volt_pmu.c => volt.c} | 72 ++++++++++++++++--- drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c | 9 +-- drivers/gpu/nvgpu/common/pmu/volt/volt_dev.h | 6 +- drivers/gpu/nvgpu/common/pmu/volt/volt_pmu.h | 28 -------- .../gpu/nvgpu/common/pmu/volt/volt_policy.c | 8 +-- .../gpu/nvgpu/common/pmu/volt/volt_policy.h | 5 +- drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c | 8 +-- drivers/gpu/nvgpu/common/pmu/volt/volt_rail.h | 30 +++++++- drivers/gpu/nvgpu/hal/clk/clk_tu104.c | 7 +- drivers/gpu/nvgpu/hal/init/hal_tu104.c | 4 +- drivers/gpu/nvgpu/include/nvgpu/boardobjgrp.h | 4 +- drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h | 4 +- drivers/gpu/nvgpu/include/nvgpu/pmu/volt.h | 42 ++--------- 17 files changed, 134 insertions(+), 166 deletions(-) rename drivers/gpu/nvgpu/common/pmu/volt/{volt_pmu.c => volt.c} (66%) delete mode 100644 drivers/gpu/nvgpu/common/pmu/volt/volt_pmu.h diff --git a/arch/nvgpu-common.yaml b/arch/nvgpu-common.yaml index 8b1ceb7d8..b55c11c68 100644 --- a/arch/nvgpu-common.yaml +++ b/arch/nvgpu-common.yaml @@ -1,4 +1,4 @@ -# Copyright (c) 2019, NVIDIA CORPORATION. All Rights Reserved. +# Copyright (c) 2019-2020, NVIDIA CORPORATION. All Rights Reserved. # # Common elements and units in nvgpu. # @@ -903,12 +903,11 @@ pmu: safe: yes gpu: dgpu owner: Mahantesh K - sources: [ common/pmu/volt/volt_dev.c, - common/pmu/volt/volt_pmu.c, + sources: [ common/pmu/volt/volt.c, + common/pmu/volt/volt_dev.c, common/pmu/volt/volt_policy.c, common/pmu/volt/volt_rail.c, common/pmu/volt/volt_dev.h, - common/pmu/volt/volt_pmu.h, common/pmu/volt/volt_policy.h, common/pmu/volt/volt_rail.h, include/nvgpu/pmu/volt.h ] diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index b0b9a6257..8fe6ab12c 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -156,10 +156,10 @@ nvgpu-y += \ common/pmu/pmgr/pmgrpmu.o \ common/pmu/pmgr/pwrmonitor.o \ common/pmu/pmgr/pwrpolicy.o \ + common/pmu/volt/volt.o \ common/pmu/volt/volt_rail.o \ common/pmu/volt/volt_dev.o \ common/pmu/volt/volt_policy.o \ - common/pmu/volt/volt_pmu.o \ common/pmu/therm/thrm.o \ common/pmu/therm/thrmdev.o \ common/pmu/therm/thrmchannel.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index f170c9261..bd7f986e6 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -1,6 +1,6 @@ # -*- mode: makefile -*- # -# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. +# Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -433,6 +433,7 @@ srcs += \ common/pmu/boardobj/boardobjgrp_e255.c \ common/pmu/boardobj/boardobjgrp_e32.c \ common/pmu/clk/clk.c \ + common/pmu/volt/volt.c \ common/pmu/clk/clk_domain.c \ common/pmu/clk/clk_fll.c \ common/pmu/clk/clk_prog.c \ @@ -478,7 +479,6 @@ srcs += \ common/pmu/therm/thrmdev.c \ common/pmu/therm/thrmpmu.c \ common/pmu/volt/volt_dev.c \ - common/pmu/volt/volt_pmu.c \ common/pmu/volt/volt_policy.c \ common/pmu/volt/volt_rail.c \ common/pmu/pmu_allocator.c \ diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c b/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c index 72ce0a024..691e8b349 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c @@ -1,7 +1,7 @@ /* * general p state infrastructure * - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -139,29 +139,6 @@ static int pmu_pstate_init(struct gk20a *g) return 0; } -static int pmu_pstate_volt_sw_setup(struct gk20a *g) -{ - int err; - nvgpu_log_fn(g, " "); - - err = nvgpu_volt_rail_sw_setup(g); - if (err != 0) { - return err; - } - - err = nvgpu_volt_dev_sw_setup(g); - if (err != 0) { - return err; - } - - err = nvgpu_volt_policy_sw_setup(g); - if (err != 0) { - return err; - } - - return 0; -} - static int pmu_pstate_clk_sw_setup(struct gk20a *g) { int err; @@ -253,7 +230,7 @@ int nvgpu_pmu_pstate_sw_setup(struct gk20a *g) return err; } - err = pmu_pstate_volt_sw_setup(g); + err = nvgpu_pmu_volt_sw_setup(g); if (err != 0) { nvgpu_err(g, "Volt sw setup failed"); return err; @@ -302,37 +279,6 @@ err_perf_pmu_init_pmupstate: return err; } -static int pmu_pstate_volt_pmu_setup(struct gk20a *g) -{ - int err; - nvgpu_log_fn(g, " "); - - err = nvgpu_volt_rail_pmu_setup(g); - if (err != 0) { - return err; - } - - err = nvgpu_volt_dev_pmu_setup(g); - if (err != 0) { - return err; - } - - err = nvgpu_volt_policy_pmu_setup(g); - if (err != 0) { - return err; - } - - err = nvgpu_volt_send_load_cmd_to_pmu(g); - if (err != 0) { - nvgpu_err(g, - "Failed to send VOLT LOAD CMD to PMU: status = 0x%08x.", - err); - return err; - } - - return 0; -} - static int pmu_pstate_clk_pmu_setup(struct gk20a *g) { int err; @@ -425,7 +371,7 @@ int nvgpu_pmu_pstate_pmu_setup(struct gk20a *g) } } - err = pmu_pstate_volt_pmu_setup(g); + err = nvgpu_pmu_volt_pmu_setup(g); if (err != 0) { nvgpu_err(g, "Failed to send VOLT pmu setup"); return err; diff --git a/drivers/gpu/nvgpu/common/pmu/volt/volt_pmu.c b/drivers/gpu/nvgpu/common/pmu/volt/volt.c similarity index 66% rename from drivers/gpu/nvgpu/common/pmu/volt/volt_pmu.c rename to drivers/gpu/nvgpu/common/pmu/volt/volt.c index 1c33d2480..d2a2dec1e 100644 --- a/drivers/gpu/nvgpu/common/pmu/volt/volt_pmu.c +++ b/drivers/gpu/nvgpu/common/pmu/volt/volt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,20 +20,16 @@ * DEALINGS IN THE SOFTWARE. */ -#include -#include -#include -#include -#include -#include -#include -#include #include +#include #include -#include "volt_pmu.h" +#include "volt_rail.h" +#include "volt_dev.h" +#include "volt_policy.h" -int nvgpu_volt_send_load_cmd_to_pmu(struct gk20a *g) + +static int volt_send_load_cmd_to_pmu(struct gk20a *g) { struct nvgpu_pmu *pmu = g->pmu; struct nv_pmu_rpc_struct_volt_load rpc; @@ -65,3 +61,57 @@ void nvgpu_pmu_volt_rpc_handler(struct gk20a *g, struct nv_pmu_rpc_header *rpc) break; } } + +int nvgpu_pmu_volt_sw_setup(struct gk20a *g) +{ + int err; + nvgpu_log_fn(g, " "); + + err = volt_rail_sw_setup(g); + if (err != 0) { + return err; + } + + err = volt_dev_sw_setup(g); + if (err != 0) { + return err; + } + + err = volt_policy_sw_setup(g); + if (err != 0) { + return err; + } + + return 0; +} + +int nvgpu_pmu_volt_pmu_setup(struct gk20a *g) +{ + int err; + nvgpu_log_fn(g, " "); + + err = volt_rail_pmu_setup(g); + if (err != 0) { + return err; + } + + err = volt_dev_pmu_setup(g); + if (err != 0) { + return err; + } + + err = volt_policy_pmu_setup(g); + if (err != 0) { + return err; + } + + err = volt_send_load_cmd_to_pmu(g); + if (err != 0) { + nvgpu_err(g, + "Failed to send VOLT LOAD CMD to PMU: status = 0x%08x.", + err); + return err; + } + + return 0; +} diff --git a/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c b/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c index b46c57e15..7f6bbbca4 100644 --- a/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c +++ b/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,6 +34,7 @@ #include #include "volt_dev.h" +#include "volt_rail.h" static int volt_device_pmu_data_init_super(struct gk20a *g, struct boardobj *pboard_obj, struct nv_pmu_boardobj *ppmudata) @@ -463,7 +464,7 @@ static int volt_device_state_init(struct gk20a *g, goto done; } - status = nvgpu_volt_rail_volt_dev_register(g, pRail, + status = volt_rail_volt_dev_register(g, pRail, BOARDOBJ_GET_IDX(pvolt_dev), pvolt_dev->operation_type); if (status != 0) { nvgpu_err(g, @@ -480,7 +481,7 @@ done: return status; } -int nvgpu_volt_dev_pmu_setup(struct gk20a *g) +int volt_dev_pmu_setup(struct gk20a *g) { int status; struct boardobjgrp *pboardobjgrp = NULL; @@ -499,7 +500,7 @@ int nvgpu_volt_dev_pmu_setup(struct gk20a *g) return status; } -int nvgpu_volt_dev_sw_setup(struct gk20a *g) +int volt_dev_sw_setup(struct gk20a *g) { int status = 0; struct boardobjgrp *pboardobjgrp = NULL; diff --git a/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.h b/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.h index e6d6f7c97..3a84a9534 100644 --- a/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.h +++ b/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -70,4 +70,8 @@ struct voltage_device_pwm_entry { }; /* PWM end */ +int volt_dev_sw_setup(struct gk20a *g); +int volt_dev_pmu_setup(struct gk20a *g); +void nvgpu_pmu_volt_rpc_handler(struct gk20a *g, struct nv_pmu_rpc_header *rpc); + #endif /* NVGPU_VOLT_DEV_H */ diff --git a/drivers/gpu/nvgpu/common/pmu/volt/volt_pmu.h b/drivers/gpu/nvgpu/common/pmu/volt/volt_pmu.h deleted file mode 100644 index 4c5ed27bf..000000000 --- a/drivers/gpu/nvgpu/common/pmu/volt/volt_pmu.h +++ /dev/null @@ -1,28 +0,0 @@ -/* -* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. -* - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. -*/ - -#ifndef NVGPU_VOLT_PMU_H -#define NVGPU_VOLT_PMU_H - -u32 volt_pmu_send_load_cmd_to_pmu(struct gk20a *g); - -#endif /* NVGPU_VOLT_PMU_H */ diff --git a/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c b/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c index 78aff77a7..a5ca0d185 100644 --- a/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c +++ b/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -332,7 +332,7 @@ static int _volt_policy_grp_pmudatainit_super(struct gk20a *g, struct nv_pmu_volt_volt_policy_boardobjgrp_set_header *pset = (struct nv_pmu_volt_volt_policy_boardobjgrp_set_header *) pboardobjgrppmu; - struct obj_volt *volt = (struct obj_volt *)pboardobjgrp; + struct nvgpu_pmu_volt *volt = (struct nvgpu_pmu_volt *)pboardobjgrp; int status = 0; status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); @@ -349,7 +349,7 @@ done: return status; } -int nvgpu_volt_policy_pmu_setup(struct gk20a *g) +int volt_policy_pmu_setup(struct gk20a *g) { int status; struct boardobjgrp *pboardobjgrp = NULL; @@ -369,7 +369,7 @@ int nvgpu_volt_policy_pmu_setup(struct gk20a *g) return status; } -int nvgpu_volt_policy_sw_setup(struct gk20a *g) +int volt_policy_sw_setup(struct gk20a *g) { int status = 0; struct boardobjgrp *pboardobjgrp = NULL; diff --git a/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.h b/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.h index 07445b8d3..e3dfa5969 100644 --- a/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.h +++ b/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -47,4 +47,7 @@ struct voltage_policy_single_rail_multi_step { u32 ramp_down_step_size_uv; }; +int volt_policy_sw_setup(struct gk20a *g); +int volt_policy_pmu_setup(struct gk20a *g); + #endif /* NVGPU_VOLT_POLICY_H */ diff --git a/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c b/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c index 808181274..83ffb18cf 100644 --- a/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c +++ b/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -375,7 +375,7 @@ static int nvgpu_volt_rail_boardobj_grp_get_status(struct gk20a *g) return 0; } -int nvgpu_volt_rail_sw_setup(struct gk20a *g) +int volt_rail_sw_setup(struct gk20a *g) { int status = 0; struct boardobjgrp *pboardobjgrp = NULL; @@ -448,7 +448,7 @@ done: return status; } -int nvgpu_volt_rail_pmu_setup(struct gk20a *g) +int volt_rail_pmu_setup(struct gk20a *g) { int status; struct boardobjgrp *pboardobjgrp = NULL; @@ -490,7 +490,7 @@ u8 nvgpu_volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain) } } -int nvgpu_volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail +int volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail *pvolt_rail, u8 volt_dev_idx, u8 operation_type) { int status = 0; diff --git a/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.h b/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.h index f204d71e7..91ec40ce7 100644 --- a/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.h +++ b/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,5 +29,33 @@ #define CTRL_PMGR_PWR_EQUATION_INDEX_INVALID 0xFFU +struct voltage_rail { + struct boardobj super; + u32 boot_voltage_uv; + u8 rel_limit_vfe_equ_idx; + u8 alt_rel_limit_vfe_equ_idx; + u8 ov_limit_vfe_equ_idx; + u8 pwr_equ_idx; + u8 volt_scale_exp_pwr_equ_idx; + u8 volt_dev_idx_default; + u8 volt_dev_idx_ipc_vmin; + u8 boot_volt_vfe_equ_idx; + u8 vmin_limit_vfe_equ_idx; + u8 volt_margin_limit_vfe_equ_idx; + u32 volt_margin_limit_vfe_equ_mon_handle; + u32 rel_limit_vfe_equ_mon_handle; + u32 alt_rel_limit_vfe_equ_mon_handle; + u32 ov_limit_vfe_equ_mon_handle; + struct boardobjgrpmask_e32 volt_dev_mask; + s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES]; + u32 vmin_limitu_v; + u32 max_limitu_v; + u32 current_volt_uv; +}; + +int volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail + *pvolt_rail, u8 volt_dev_idx, u8 operation_type); +int volt_rail_sw_setup(struct gk20a *g); +int volt_rail_pmu_setup(struct gk20a *g); #endif /* NVGPU_VOLT_RAIL_H */ diff --git a/drivers/gpu/nvgpu/hal/clk/clk_tu104.c b/drivers/gpu/nvgpu/hal/clk/clk_tu104.c index 47cef968a..9a8b74649 100644 --- a/drivers/gpu/nvgpu/hal/clk/clk_tu104.c +++ b/drivers/gpu/nvgpu/hal/clk/clk_tu104.c @@ -1,7 +1,7 @@ /* * TU104 Clocks * - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -257,6 +257,7 @@ int nvgpu_clk_mon_check_status(struct gk20a *g, return 0; } +#ifdef CONFIG_NVGPU_CLK_ARB u32 tu104_crystal_clk_hz(struct gk20a *g) { return (XTAL4X_KHZ * 1000); @@ -513,7 +514,6 @@ u32 tu104_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) { return -EBUSY; } -#ifdef CONFIG_NVGPU_CLK_ARB int tu104_clk_domain_get_f_points( struct gk20a *g, u32 clkapidomain, @@ -543,13 +543,12 @@ int tu104_clk_domain_get_f_points( } return status; } -#endif void tu104_suspend_clk_support(struct gk20a *g) { nvgpu_mutex_destroy(&g->clk.clk_mutex); } -#ifdef CONFIG_NVGPU_CLK_ARB + unsigned long tu104_clk_maxrate(struct gk20a *g, u32 api_domain) { u16 min_mhz = 0, max_mhz = 0; diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index ea9d1072b..1db2ead2d 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -1246,13 +1246,12 @@ static const struct gpu_ops tu104_ops = { gm20b_clear_pmu_bar0_host_err_status, }, .clk = { +#ifdef CONFIG_NVGPU_CLK_ARB .init_clk_support = tu104_init_clk_support, .get_crystal_clk_hz = tu104_crystal_clk_hz, .get_rate_cntr = tu104_get_rate_cntr, .measure_freq = tu104_clk_measure_freq, .suspend_clk_support = tu104_suspend_clk_support, - .perf_pmu_vfe_load = nvgpu_perf_pmu_vfe_load_ps35, -#ifdef CONFIG_NVGPU_CLK_ARB .clk_domain_get_f_points = tu104_clk_domain_get_f_points, .get_maxrate = tu104_clk_maxrate, .get_change_seq_time = tu104_get_change_seq_time, @@ -1262,6 +1261,7 @@ static const struct gpu_ops tu104_ops = { nvgpu_clk_mon_check_master_fault_status, .clk_mon_check_status = nvgpu_clk_mon_check_status, .clk_mon_init_domains = nvgpu_clk_mon_init_domains, + .perf_pmu_vfe_load = nvgpu_perf_pmu_vfe_load_ps35, }, #ifdef CONFIG_NVGPU_CLK_ARB .clk_arb = { diff --git a/drivers/gpu/nvgpu/include/nvgpu/boardobjgrp.h b/drivers/gpu/nvgpu/include/nvgpu/boardobjgrp.h index 12063f3ab..524a487f4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/boardobjgrp.h +++ b/drivers/gpu/nvgpu/include/nvgpu/boardobjgrp.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -31,7 +31,7 @@ struct nvgpu_list_node; #include #include #include -#include +#include #include /* diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h index 2b8901d3d..7831a33e0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -106,7 +106,7 @@ struct perf_pmupstate { struct vfe_vars vfe_varobjs; struct vfe_equs vfe_equobjs; struct pstates pstatesobjs; - struct obj_volt volt; + struct nvgpu_pmu_volt volt; struct obj_lwpr lpwr; struct nvgpu_vfe_invalidate vfe_init; struct change_seq_pmu changeseq_pmu; diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/volt.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/volt.h index 36b8b29e5..13070d528 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/volt.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/volt.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -61,53 +61,19 @@ struct voltage_policy_metadata { struct boardobjgrp_e32 volt_policies; }; -struct obj_volt { +struct nvgpu_pmu_volt { struct voltage_rail_metadata volt_rail_metadata; struct voltage_device_metadata volt_dev_metadata; struct voltage_policy_metadata volt_policy_metadata; }; -struct voltage_rail { - struct boardobj super; - u32 boot_voltage_uv; - u8 rel_limit_vfe_equ_idx; - u8 alt_rel_limit_vfe_equ_idx; - u8 ov_limit_vfe_equ_idx; - u8 pwr_equ_idx; - u8 volt_scale_exp_pwr_equ_idx; - u8 volt_dev_idx_default; - u8 volt_dev_idx_ipc_vmin; - u8 boot_volt_vfe_equ_idx; - u8 vmin_limit_vfe_equ_idx; - u8 volt_margin_limit_vfe_equ_idx; - u32 volt_margin_limit_vfe_equ_mon_handle; - u32 rel_limit_vfe_equ_mon_handle; - u32 alt_rel_limit_vfe_equ_mon_handle; - u32 ov_limit_vfe_equ_mon_handle; - struct boardobjgrpmask_e32 volt_dev_mask; - s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES]; - u32 vmin_limitu_v; - u32 max_limitu_v; - u32 current_volt_uv; -}; -int nvgpu_volt_send_load_cmd_to_pmu(struct gk20a *g); - -int nvgpu_volt_dev_sw_setup(struct gk20a *g); -int nvgpu_volt_dev_pmu_setup(struct gk20a *g); - -int nvgpu_volt_policy_sw_setup(struct gk20a *g); -int nvgpu_volt_policy_pmu_setup(struct gk20a *g); - -int nvgpu_volt_rail_sw_setup(struct gk20a *g); -int nvgpu_volt_rail_pmu_setup(struct gk20a *g); u8 nvgpu_volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain); int nvgpu_volt_get_vmin_vmax_ps35(struct gk20a *g, u32 *vmin_uv, u32 *vmax_uv); u8 nvgpu_volt_get_vmargin_ps35(struct gk20a *g); -int nvgpu_volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail - *pvolt_rail, u8 volt_dev_idx, u8 operation_type); u8 nvgpu_volt_rail_vbios_volt_domain_convert_to_internal (struct gk20a *g, u8 vbios_volt_domain); -void nvgpu_pmu_volt_rpc_handler(struct gk20a *g, struct nv_pmu_rpc_header *rpc); int nvgpu_volt_get_curr_volt_ps35(struct gk20a *g, u32 *vcurr_uv); +int nvgpu_pmu_volt_sw_setup(struct gk20a *g); +int nvgpu_pmu_volt_pmu_setup(struct gk20a *g); #endif /* NVGPU_PMU_VOLT_H */