From 911d25dda2b6aacf4a4547c54a9c7107252f93ef Mon Sep 17 00:00:00 2001 From: Debarshi Dutta Date: Wed, 19 Dec 2018 12:58:17 +0530 Subject: [PATCH] gpu: nvgpu: move sema specific cmdbuf methods to common/sync/ sema cmdbuf specific functions are only for the sync functionality of nvgpu and donot belong to fifo. construct files sema_cmdbuf_gv11b.h and sema_cmdbuf_gv11b.c under common/sync to contain the syncpt specific cmdbuf functions for arch gv11b. Jira NVGPU-1308 Change-Id: I440847e8b996e0956d81fe6cdde331937deda40e Signed-off-by: Debarshi Dutta Reviewed-on: https://git-master.nvidia.com/r/1975923 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/Makefile.sources | 1 + .../gpu/nvgpu/common/sync/sema_cmdbuf_gv11b.c | 79 +++++++++++++++++++ .../gpu/nvgpu/common/sync/sema_cmdbuf_gv11b.h | 38 +++++++++ drivers/gpu/nvgpu/gv100/hal_gv100.c | 7 +- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 49 ------------ drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 6 -- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 7 +- drivers/gpu/nvgpu/tu104/hal_tu104.c | 7 +- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 7 +- 10 files changed, 135 insertions(+), 67 deletions(-) create mode 100644 drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gv11b.c create mode 100644 drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gv11b.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 289fdc15f..3a9bf7042 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -61,6 +61,7 @@ nvgpu-y += common/bus/bus_gk20a.o \ common/sync/channel_sync.o \ common/sync/channel_sync_semaphore.o \ common/sync/sema_cmdbuf_gk20a.o \ + common/sync/sema_cmdbuf_gv11b.o \ common/boardobj/boardobj.o \ common/boardobj/boardobjgrp.o \ common/boardobj/boardobjgrpmask.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 1362ce0d0..1ac972c01 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -163,6 +163,7 @@ srcs += common/sim.c \ common/sync/syncpt_cmdbuf_gk20a.c \ common/sync/syncpt_cmdbuf_gv11b.c \ common/sync/sema_cmdbuf_gk20a.c \ + common/sync/sema_cmdbuf_gv11b.c \ common/clock_gating/gm20b_gating_reglist.c \ common/clock_gating/gp10b_gating_reglist.c \ common/clock_gating/gv11b_gating_reglist.c \ diff --git a/drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gv11b.c b/drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gv11b.c new file mode 100644 index 000000000..a9868e289 --- /dev/null +++ b/drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gv11b.c @@ -0,0 +1,79 @@ +/* + * GV11B sema cmdbuf + * + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. +* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include + +#include "sema_cmdbuf_gv11b.h" + +u32 gv11b_get_sema_wait_cmd_size(void) +{ + return 10U; +} + +u32 gv11b_get_sema_incr_cmd_size(void) +{ + return 12U; +} + +void gv11b_add_sema_cmd(struct gk20a *g, + struct nvgpu_semaphore *s, u64 sema_va, + struct priv_cmd_entry *cmd, + u32 off, bool acquire, bool wfi) +{ + nvgpu_log_fn(g, " "); + + /* sema_addr_lo */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010017); + nvgpu_mem_wr32(g, cmd->mem, off++, sema_va & 0xffffffffULL); + + /* sema_addr_hi */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010018); + nvgpu_mem_wr32(g, cmd->mem, off++, (sema_va >> 32ULL) & 0xffULL); + + /* payload_lo */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010019); + nvgpu_mem_wr32(g, cmd->mem, off++, nvgpu_semaphore_get_value(s)); + + /* payload_hi : ignored */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001a); + nvgpu_mem_wr32(g, cmd->mem, off++, 0); + + if (acquire) { + /* sema_execute : acq_strict_geq | switch_en | 32bit */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b); + nvgpu_mem_wr32(g, cmd->mem, off++, U32(0x2) | BIT32(12)); + } else { + /* sema_execute : release | wfi | 32bit */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b); + nvgpu_mem_wr32(g, cmd->mem, off++, + U32(0x1) | ((wfi ? U32(0x1) : U32(0x0)) << 20U)); + + /* non_stall_int : payload is ignored */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010008); + nvgpu_mem_wr32(g, cmd->mem, off++, 0); + } +} \ No newline at end of file diff --git a/drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gv11b.h b/drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gv11b.h new file mode 100644 index 000000000..86a04d4ce --- /dev/null +++ b/drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gv11b.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_SYNC_SEMA_CMDBUF_GV11B_H +#define NVGPU_SYNC_SEMA_CMDBUF_GV11B_H + +#include + +struct gk20a; +struct priv_cmd_entry; +struct nvgpu_semaphore; + +u32 gv11b_get_sema_wait_cmd_size(void); +u32 gv11b_get_sema_incr_cmd_size(void); +void gv11b_add_sema_cmd(struct gk20a *g, + struct nvgpu_semaphore *s, u64 sema_va, + struct priv_cmd_entry *cmd, + u32 off, bool acquire, bool wfi); + +#endif /* NVGPU_SYNC_SEMA_CMDBUF_GV11B_H */ \ No newline at end of file diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 9d00ad1bc..4240bcf14 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -72,6 +72,7 @@ #include "common/nvlink/nvlink_tu104.h" #include "common/pmu/perf/perf_gv100.h" #include "common/sync/syncpt_cmdbuf_gv11b.h" +#include "common/sync/sema_cmdbuf_gv11b.h" #include "common/regops/regops_gv100.h" #include "common/fifo/runlist_gk20a.h" #include "common/fifo/runlist_gv11b.h" @@ -776,9 +777,9 @@ static const struct gpu_ops gv100_ops = { gv11b_get_syncpt_incr_per_release, .get_sync_ro_map = gv11b_get_sync_ro_map, #endif - .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, - .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, - .add_sema_cmd = gv11b_fifo_add_sema_cmd, + .get_sema_wait_cmd_size = gv11b_get_sema_wait_cmd_size, + .get_sema_incr_cmd_size = gv11b_get_sema_incr_cmd_size, + .add_sema_cmd = gv11b_add_sema_cmd, }, .runlist = { .update_runlist = gk20a_fifo_update_runlist, diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 53ebdb73f..07e136010 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1881,55 +1881,6 @@ void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g, nvgpu_log_info(g, "eng method buffers de-allocated"); } -u32 gv11b_fifo_get_sema_wait_cmd_size(void) -{ - return 10; -} - -u32 gv11b_fifo_get_sema_incr_cmd_size(void) -{ - return 12; -} - -void gv11b_fifo_add_sema_cmd(struct gk20a *g, - struct nvgpu_semaphore *s, u64 sema_va, - struct priv_cmd_entry *cmd, - u32 off, bool acquire, bool wfi) -{ - nvgpu_log_fn(g, " "); - - /* sema_addr_lo */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010017); - nvgpu_mem_wr32(g, cmd->mem, off++, sema_va & 0xffffffffULL); - - /* sema_addr_hi */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010018); - nvgpu_mem_wr32(g, cmd->mem, off++, (sema_va >> 32ULL) & 0xffULL); - - /* payload_lo */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010019); - nvgpu_mem_wr32(g, cmd->mem, off++, nvgpu_semaphore_get_value(s)); - - /* payload_hi : ignored */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001a); - nvgpu_mem_wr32(g, cmd->mem, off++, 0); - - if (acquire) { - /* sema_execute : acq_strict_geq | switch_en | 32bit */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b); - nvgpu_mem_wr32(g, cmd->mem, off++, U32(0x2) | BIT32(12)); - } else { - /* sema_execute : release | wfi | 32bit */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b); - nvgpu_mem_wr32(g, cmd->mem, off++, - U32(0x1) | ((wfi ? U32(0x1) : U32(0x0)) << 20U)); - - /* non_stall_int : payload is ignored */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010008); - nvgpu_mem_wr32(g, cmd->mem, off++, 0); - } -} - int gv11b_init_fifo_setup_hw(struct gk20a *g) { struct fifo_gk20a *f = &g->fifo; diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index c5bf0aaa6..6e73e4dcb 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -100,12 +100,6 @@ void gv11b_fifo_init_eng_method_buffers(struct gk20a *g, struct tsg_gk20a *tsg); void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g, struct tsg_gk20a *tsg); -u32 gv11b_fifo_get_sema_wait_cmd_size(void); -u32 gv11b_fifo_get_sema_incr_cmd_size(void); -void gv11b_fifo_add_sema_cmd(struct gk20a *g, - struct nvgpu_semaphore *s, u64 sema_va, - struct priv_cmd_entry *cmd, - u32 off, bool acquire, bool wfi); int gv11b_init_fifo_setup_hw(struct gk20a *g); void gv11b_fifo_tsg_verify_status_faulted(struct channel_gk20a *ch); diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 2a79b6e9d..ce2d40f9f 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -63,6 +63,7 @@ #include "common/top/top_gm20b.h" #include "common/top/top_gp10b.h" #include "common/sync/syncpt_cmdbuf_gv11b.h" +#include "common/sync/sema_cmdbuf_gv11b.h" #include "common/regops/regops_gv11b.h" #include "common/fifo/runlist_gk20a.h" #include "common/fifo/runlist_gv11b.h" @@ -729,9 +730,9 @@ static const struct gpu_ops gv11b_ops = { gv11b_get_syncpt_incr_per_release, .get_sync_ro_map = gv11b_get_sync_ro_map, #endif - .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, - .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, - .add_sema_cmd = gv11b_fifo_add_sema_cmd, + .get_sema_wait_cmd_size = gv11b_get_sema_wait_cmd_size, + .get_sema_incr_cmd_size = gv11b_get_sema_incr_cmd_size, + .add_sema_cmd = gv11b_add_sema_cmd, }, .runlist = { .reschedule_runlist = gv11b_fifo_reschedule_runlist, diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 23369f86f..990d0a76a 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -77,6 +77,7 @@ #include "common/nvlink/nvlink_gv100.h" #include "common/nvlink/nvlink_tu104.h" #include "common/sync/syncpt_cmdbuf_gv11b.h" +#include "common/sync/sema_cmdbuf_gv11b.h" #include "common/regops/regops_tu104.h" #include "common/fifo/runlist_gk20a.h" #include "common/fifo/runlist_gv11b.h" @@ -806,9 +807,9 @@ static const struct gpu_ops tu104_ops = { gv11b_get_syncpt_incr_per_release, .get_sync_ro_map = gv11b_get_sync_ro_map, #endif - .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, - .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, - .add_sema_cmd = gv11b_fifo_add_sema_cmd, + .get_sema_wait_cmd_size = gv11b_get_sema_wait_cmd_size, + .get_sema_incr_cmd_size = gv11b_get_sema_incr_cmd_size, + .add_sema_cmd = gv11b_add_sema_cmd, }, .runlist = { .update_runlist = gk20a_fifo_update_runlist, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 3a44c8a52..40ac79f1e 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -41,6 +41,7 @@ #include "common/fuse/fuse_gm20b.h" #include "common/fuse/fuse_gp10b.h" #include "common/sync/syncpt_cmdbuf_gv11b.h" +#include "common/sync/sema_cmdbuf_gv11b.h" #include "common/regops/regops_gv11b.h" #include "common/fifo/runlist_gv11b.h" @@ -498,9 +499,9 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_syncpt_incr_cmd_size = gv11b_get_syncpt_incr_cmd_size, .get_sync_ro_map = vgpu_gv11b_fifo_get_sync_ro_map, #endif - .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, - .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, - .add_sema_cmd = gv11b_fifo_add_sema_cmd, + .get_sema_wait_cmd_size = gv11b_get_sema_wait_cmd_size, + .get_sema_incr_cmd_size = gv11b_get_sema_incr_cmd_size, + .add_sema_cmd = gv11b_add_sema_cmd, }, .runlist = { .reschedule_runlist = NULL,