From 913a2d519fd8d18fd981433e47100e8c95d289be Mon Sep 17 00:00:00 2001 From: Vedashree Vidwans Date: Tue, 10 Aug 2021 16:31:34 -0700 Subject: [PATCH] gpu: nvgpu: ga10b: correct cbc base/top reg value CBC base and top values need to be left shifted by cbc_alignment factor to store in the CBC_BASE and CBC_TOP registers respectively. Fix cbc calculations accordingly. Update cbc information debug prints to print with gpu_dbg_info flag. Bug 3353418 Change-Id: I858c46a9dab1e5f810cabb327ba1797f15a2960e Signed-off-by: Vedashree Vidwans Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2574119 Reviewed-by: svc_kernel_abi Reviewed-by: Seshendra Gadagottu Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: Seshendra Gadagottu Tested-by: Bitan Biswas Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/cbc/cbc_ga10b.c | 17 +++++++++-------- drivers/gpu/nvgpu/hal/fb/fb_ga10b.c | 18 ++++++++++-------- .../nvgpu/include/nvgpu/hw/ga10b/hw_fb_ga10b.h | 4 +++- 3 files changed, 22 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/cbc/cbc_ga10b.c b/drivers/gpu/nvgpu/hal/cbc/cbc_ga10b.c index f49a18874..cd82532f8 100644 --- a/drivers/gpu/nvgpu/hal/cbc/cbc_ga10b.c +++ b/drivers/gpu/nvgpu/hal/cbc/cbc_ga10b.c @@ -142,15 +142,16 @@ int ga10b_cbc_alloc_comptags(struct gk20a *g, struct nvgpu_cbc *cbc) cbc->gobs_per_comptagline_per_slice = gobs_per_comptagline_per_slice; cbc->compbit_backing_size = compbit_backing_size; - nvgpu_log(g, gpu_dbg_pte, "supported LTCs: 0x%x", + nvgpu_log(g, gpu_dbg_info | gpu_dbg_pte, "supported LTCs: 0x%x", nvgpu_ltc_get_ltc_count(g)); - nvgpu_log(g, gpu_dbg_pte, "ltc_count used for calculations: 0x%x", - ltc_count); - nvgpu_log(g, gpu_dbg_pte, "compbit backing store size : 0x%x", - compbit_backing_size); - nvgpu_log(g, gpu_dbg_pte, "max comptag lines: %d", - max_comptag_lines); - nvgpu_log(g, gpu_dbg_pte, "gobs_per_comptagline_per_slice: %d", + nvgpu_log(g, gpu_dbg_info | gpu_dbg_pte, + "ltc_count used for calculations: 0x%x", ltc_count); + nvgpu_log(g, gpu_dbg_info | gpu_dbg_pte, + "compbit backing store size : 0x%x", compbit_backing_size); + nvgpu_log(g, gpu_dbg_info | gpu_dbg_pte, + "max comptag lines: %d", max_comptag_lines); + nvgpu_log(g, gpu_dbg_info | gpu_dbg_pte, + "gobs_per_comptagline_per_slice: %d", cbc->gobs_per_comptagline_per_slice); return 0; diff --git a/drivers/gpu/nvgpu/hal/fb/fb_ga10b.c b/drivers/gpu/nvgpu/hal/fb/fb_ga10b.c index c7d24f780..de538de2b 100644 --- a/drivers/gpu/nvgpu/hal/fb/fb_ga10b.c +++ b/drivers/gpu/nvgpu/hal/fb/fb_ga10b.c @@ -38,22 +38,24 @@ #ifdef CONFIG_NVGPU_COMPRESSION void ga10b_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc) { - u64 base_divisor; u64 compbit_store_base; u64 compbit_store_pa; u64 combit_top_size; + u64 combit_top; u32 cbc_max_rval; + /* Unlike dgpu, partition swizzling is disabled for ga10b */ + u32 num_swizzled_ltcs = 1U; /* * Update CBC registers * Note: CBC Base value should be updated after CBC MAX */ - base_divisor = g->ops.cbc.get_base_divisor(g); combit_top_size = cbc->compbit_backing_size; - combit_top_size = round_up(combit_top_size, base_divisor); - nvgpu_assert(combit_top_size < U64(U32_MAX)); + combit_top = (combit_top_size / num_swizzled_ltcs) >> + fb_mmu_cbc_top_alignment_shift_v(); + nvgpu_assert(combit_top < U64(U32_MAX)); nvgpu_writel(g, fb_mmu_cbc_top_r(), - fb_mmu_cbc_top_address_f(U32(combit_top_size))); + fb_mmu_cbc_top_size_f(u64_lo32(combit_top))); cbc_max_rval = nvgpu_readl(g, fb_mmu_cbc_max_r()); cbc_max_rval = set_field(cbc_max_rval, @@ -62,11 +64,11 @@ void ga10b_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc) nvgpu_writel(g, fb_mmu_cbc_max_r(), cbc_max_rval); compbit_store_pa = nvgpu_mem_get_addr(g, &cbc->compbit_store.mem); - compbit_store_base = round_down(compbit_store_pa, base_divisor); - + compbit_store_base = (compbit_store_pa / num_swizzled_ltcs) >> + fb_mmu_cbc_base_alignment_shift_v(); nvgpu_assert(compbit_store_base < U64(U32_MAX)); nvgpu_writel(g, fb_mmu_cbc_base_r(), - fb_mmu_cbc_base_address_f(U32(compbit_store_base))); + fb_mmu_cbc_base_address_f(u64_lo32(compbit_store_base))); nvgpu_log(g, gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte, "compbit top size: 0x%x,%08x \n", diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fb_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fb_ga10b.h index 70c012e5b..7364bd629 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fb_ga10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fb_ga10b.h @@ -284,9 +284,11 @@ #define fb_mmu_cbc_max_safe_m() (U32(0x1U) << 31U) #define fb_mmu_cbc_max_safe_true_f() (0x80000000U) #define fb_mmu_cbc_base_r() (0x00100ec4U) +#define fb_mmu_cbc_base_alignment_shift_v() (0x0000000bU) #define fb_mmu_cbc_base_address_f(v) ((U32(v) & 0x3ffffffU) << 0U) #define fb_mmu_cbc_top_r() (0x00100ec8U) -#define fb_mmu_cbc_top_address_f(v) ((U32(v) & 0x7fffU) << 0U) +#define fb_mmu_cbc_top_alignment_shift_v() (0x0000000bU) +#define fb_mmu_cbc_top_size_f(v) ((U32(v) & 0x7fffU) << 0U) #define fb_mmu_vpr_mode_r() (0x001fa800U) #define fb_mmu_vpr_mode_fetch_v(r) (((r) >> 2U) & 0x1U) #define fb_mmu_vpr_mode_fetch_false_v() (0x00000000U)