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gpu: nvgpu: unit: fifo: channel unit test

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This unit test covers remainder of the nvgpu.common.fifo.channel module
lines and branches.

Jira NVGPU-3696

Change-Id: I590faac1e4340d8fa2e5a7e591249128ec2b8760
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2241973
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2019-11-18 17:39:02 -08:00
committed by Alex Waterman
parent 83d4e3c7a7
commit 917fb2e2df
4 changed files with 1375 additions and 176 deletions
Download Patch File Download Diff File Expand all files Collapse all files

240
drivers/gpu/nvgpu/libnvgpu-drv_safe.export
View File

@@ -245,6 +245,7 @@ nvgpu_alloc_common_init
nvgpu_alloc_destroy
nvgpu_alloc_end
nvgpu_alloc_fixed
nvgpu_alloc_gr_ctx_struct
nvgpu_alloc_initialized
nvgpu_alloc_inst_block
nvgpu_alloc_length
@@ -256,10 +257,14 @@ nvgpu_allocator_init
nvgpu_aperture_mask
nvgpu_bar1_readl
nvgpu_bar1_writel
nvgpu_big_alloc_impl
nvgpu_big_free
nvgpu_big_pages_possible
nvgpu_bitmap_clear
nvgpu_bitmap_set
nvgpu_bsearch
nvgpu_can_busy
nvgpu_ce_engine_interrupt_mask
nvgpu_ce_init_support
nvgpu_cg_blcg_fb_ltc_load_enable
nvgpu_cg_blcg_fifo_load_enable
@@ -275,129 +280,29 @@ nvgpu_cg_slcg_ce2_load_enable
nvgpu_cg_init_gr_load_gating_prod
nvgpu_cg_elcg_enable_no_wait
nvgpu_cg_elcg_disable_no_wait
nvgpu_cond_get_fault_injection
nvgpu_current_pid
nvgpu_current_tid
nvgpu_engine_cleanup_sw
nvgpu_engine_get_active_eng_info
nvgpu_engine_get_ids
nvgpu_engine_get_gr_id
nvgpu_engine_init_info
nvgpu_engine_setup_sw
nvgpu_gr_alloc
nvgpu_gr_free
nvgpu_gr_init
nvgpu_gr_init_support
nvgpu_gr_remove_support
nvgpu_gr_intr_init_support
nvgpu_gr_intr_remove_support
nvgpu_gr_intr_handle_fecs_error
nvgpu_gr_prepare_sw
nvgpu_gr_enable_hw
nvgpu_gr_suspend
nvgpu_gr_sw_ready
nvgpu_gr_falcon_get_fecs_ucode_segments
nvgpu_gr_falcon_get_gpccs_ucode_segments
nvgpu_gr_falcon_get_surface_desc_cpu_va
nvgpu_gr_falcon_init_ctxsw
nvgpu_gr_falcon_init_ctx_state
nvgpu_gr_falcon_init_ctxsw_ucode
nvgpu_gr_falcon_init_support
nvgpu_gr_falcon_load_secure_ctxsw_ucode
nvgpu_gr_falcon_remove_support
nvgpu_gr_config_init
nvgpu_gr_config_deinit
nvgpu_gr_config_get_max_gpc_count
nvgpu_gr_config_get_max_tpc_count
nvgpu_gr_config_get_max_tpc_per_gpc_count
nvgpu_gr_config_get_gpc_count
nvgpu_gr_config_get_tpc_count
nvgpu_gr_config_get_ppc_count
nvgpu_gr_config_get_pe_count_per_gpc
nvgpu_gr_config_get_sm_count_per_tpc
nvgpu_gr_config_get_gpc_mask
nvgpu_gr_config_get_gpc_ppc_count
nvgpu_gr_config_get_gpc_skip_mask
nvgpu_gr_config_get_gpc_tpc_count
nvgpu_gr_config_get_pes_tpc_count
nvgpu_gr_config_get_pes_tpc_mask
nvgpu_gr_config_get_gpc_tpc_mask_base
nvgpu_gr_config_get_gpc_tpc_count_base
nvgpu_gr_config_set_no_of_sm
nvgpu_gr_config_get_no_of_sm
nvgpu_gr_config_get_sm_info
nvgpu_gr_config_set_sm_info_gpc_index
nvgpu_gr_config_get_sm_info_gpc_index
nvgpu_gr_config_set_sm_info_tpc_index
nvgpu_gr_config_get_sm_info_tpc_index
nvgpu_gr_config_set_sm_info_global_tpc_index
nvgpu_gr_config_get_sm_info_global_tpc_index
nvgpu_gr_config_set_sm_info_sm_index
nvgpu_gr_config_get_sm_info_sm_index
nvgpu_gr_config_set_gpc_tpc_mask
nvgpu_gr_config_get_gpc_tpc_mask
nvgpu_gr_engine_interrupt_mask
nvgpu_gr_obj_ctx_is_golden_image_ready
nvgpu_gr_ctx_get_tsgid
nvgpu_gr_get_config_ptr
nvgpu_gr_fs_state_init
nvgpu_gr_global_ctx_desc_alloc
nvgpu_gr_global_ctx_desc_free
nvgpu_gr_global_ctx_buffer_alloc
nvgpu_gr_global_ctx_buffer_free
nvgpu_gr_global_ctx_set_size
nvgpu_gr_global_ctx_buffer_map
nvgpu_gr_global_ctx_buffer_unmap
nvgpu_gr_global_ctx_buffer_get_mem
nvgpu_gr_global_ctx_buffer_ready
nvgpu_gr_global_ctx_init_local_golden_image
nvgpu_gr_global_ctx_load_local_golden_image
nvgpu_gr_global_ctx_compare_golden_images
nvgpu_gr_global_ctx_deinit_local_golden_image
nvgpu_gr_ctx_desc_alloc
nvgpu_gr_ctx_desc_free
nvgpu_alloc_gr_ctx_struct
nvgpu_free_gr_ctx_struct
nvgpu_gr_ctx_alloc
nvgpu_gr_ctx_free
nvgpu_gr_ctx_set_size
nvgpu_gr_ctx_alloc_patch_ctx
nvgpu_gr_ctx_free_patch_ctx
nvgpu_gr_ctx_map_global_ctx_buffers
nvgpu_gr_ctx_patch_write_begin
nvgpu_gr_ctx_patch_write
nvgpu_gr_ctx_patch_write_end
nvgpu_golden_ctx_verif_get_fault_injection
nvgpu_local_golden_image_get_fault_injection
nvgpu_gr_obj_ctx_init
nvgpu_gr_obj_ctx_alloc
nvgpu_gr_obj_ctx_deinit
nvgpu_gr_subctx_alloc
nvgpu_gr_subctx_free
nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode
nvgpu_hr_timestamp
nvgpu_init_ltc_support
nvgpu_ltc_ecc_free
nvgpu_ltc_get_cacheline_size
nvgpu_ltc_get_ltc_count
nvgpu_ltc_get_slices_per_ltc
nvgpu_ltc_remove_support
nvgpu_ltc_sync_enabled
nvgpu_can_busy
nvgpu_ce_engine_interrupt_mask
nvgpu_channel_abort
nvgpu_channel_alloc_inst
nvgpu_channel_cleanup_sw
nvgpu_channel_close
nvgpu_channel_debug_dump_all
nvgpu_channel_deterministic_idle
nvgpu_channel_deterministic_unidle
nvgpu_channel_disable_tsg
nvgpu_channel_enable_tsg
nvgpu_channel_free_inst
nvgpu_channel_from_id__func
nvgpu_channel_kill
nvgpu_channel_mark_error
nvgpu_channel_open_new
nvgpu_channel_put__func
nvgpu_channel_setup_bind
nvgpu_channel_refch_from_inst_ptr
nvgpu_channel_resume_all_serviceable_ch
nvgpu_channel_semaphore_wakeup
nvgpu_channel_set_unserviceable
nvgpu_channel_setup_sw
nvgpu_channel_suspend_all_serviceable_ch
nvgpu_channel_sw_quiesce
nvgpu_channel_sync_create
nvgpu_channel_sync_destroy
nvgpu_channel_sync_set_safe_state
@@ -409,6 +314,7 @@ nvgpu_cond_broadcast
nvgpu_cond_broadcast_interruptible
nvgpu_cond_broadcast_locked
nvgpu_cond_destroy
nvgpu_cond_get_fault_injection
nvgpu_cond_init
nvgpu_cond_lock
nvgpu_cond_signal
@@ -416,6 +322,8 @@ nvgpu_cond_signal_interruptible
nvgpu_cond_signal_locked
nvgpu_cond_timedwait
nvgpu_cond_unlock
nvgpu_current_pid
nvgpu_current_tid
nvgpu_current_time_ms
nvgpu_current_time_ns
nvgpu_current_time_us
@@ -432,12 +340,17 @@ nvgpu_ecc_counter_init_per_lts
nvgpu_ecc_init_support
nvgpu_engine_act_interrupt_mask
nvgpu_engine_check_valid_id
nvgpu_engine_cleanup_sw
nvgpu_engine_enum_from_type
nvgpu_engine_get_active_eng_info
nvgpu_engine_get_all_ce_reset_mask
nvgpu_engine_get_fast_ce_runlist_id
nvgpu_engine_get_gr_id
nvgpu_engine_get_gr_runlist_id
nvgpu_engine_get_ids
nvgpu_engine_init_info
nvgpu_engine_is_valid_runlist_id
nvgpu_get
nvgpu_engine_setup_sw
nvgpu_falcon_hs_ucode_load_bootstrap
nvgpu_falcon_copy_to_dmem
nvgpu_falcon_copy_to_imem
@@ -460,6 +373,8 @@ nvgpu_finalize_poweron
nvgpu_free
nvgpu_free_enabled_flags
nvgpu_free_fixed
nvgpu_free_gr_ctx_struct
nvgpu_get
nvgpu_get_pte
nvgpu_gmmu_init_page_table
nvgpu_gmmu_map
@@ -467,18 +382,106 @@ nvgpu_gmmu_map_locked
nvgpu_gmmu_map_fixed
nvgpu_gmmu_unmap
nvgpu_gmmu_unmap_locked
nvgpu_golden_ctx_verif_get_fault_injection
nvgpu_gr_alloc
nvgpu_gr_config_init
nvgpu_gr_config_deinit
nvgpu_gr_config_get_max_gpc_count
nvgpu_gr_config_get_max_tpc_count
nvgpu_gr_config_get_max_tpc_per_gpc_count
nvgpu_gr_config_get_gpc_count
nvgpu_gr_config_get_tpc_count
nvgpu_gr_config_get_ppc_count
nvgpu_gr_config_get_pe_count_per_gpc
nvgpu_gr_config_get_sm_count_per_tpc
nvgpu_gr_config_get_gpc_mask
nvgpu_gr_config_get_gpc_ppc_count
nvgpu_gr_config_get_gpc_skip_mask
nvgpu_gr_config_get_gpc_tpc_count
nvgpu_gr_config_get_pes_tpc_count
nvgpu_gr_config_get_pes_tpc_mask
nvgpu_gr_config_get_gpc_tpc_mask
nvgpu_gr_config_get_gpc_tpc_mask_base
nvgpu_gr_config_get_gpc_tpc_count_base
nvgpu_gr_config_get_sm_info
nvgpu_gr_config_get_sm_info_global_tpc_index
nvgpu_gr_config_get_sm_info_gpc_index
nvgpu_gr_config_get_sm_info_sm_index
nvgpu_gr_config_get_sm_info_tpc_index
nvgpu_gr_config_get_no_of_sm
nvgpu_gr_config_set_gpc_tpc_mask
nvgpu_gr_config_set_no_of_sm
nvgpu_gr_config_set_sm_info_global_tpc_index
nvgpu_gr_config_set_sm_info_gpc_index
nvgpu_gr_config_set_sm_info_sm_index
nvgpu_gr_config_set_sm_info_tpc_index
nvgpu_gr_ctx_alloc
nvgpu_gr_ctx_alloc_patch_ctx
nvgpu_gr_ctx_desc_alloc
nvgpu_gr_ctx_desc_free
nvgpu_gr_ctx_free
nvgpu_gr_ctx_free_patch_ctx
nvgpu_gr_ctx_get_tsgid
nvgpu_gr_ctx_map_global_ctx_buffers
nvgpu_gr_ctx_patch_write
nvgpu_gr_ctx_patch_write_begin
nvgpu_gr_ctx_patch_write_end
nvgpu_gr_ctx_set_size
nvgpu_gr_enable_hw
nvgpu_gr_engine_interrupt_mask
nvgpu_gr_falcon_get_fecs_ucode_segments
nvgpu_gr_falcon_get_gpccs_ucode_segments
nvgpu_gr_falcon_get_surface_desc_cpu_va
nvgpu_gr_falcon_init_ctxsw
nvgpu_gr_falcon_init_ctx_state
nvgpu_gr_falcon_init_ctxsw_ucode
nvgpu_gr_falcon_init_support
nvgpu_gr_falcon_load_secure_ctxsw_ucode
nvgpu_gr_falcon_remove_support
nvgpu_gr_free
nvgpu_gr_fs_state_init
nvgpu_gr_get_config_ptr
nvgpu_gr_global_ctx_buffer_alloc
nvgpu_gr_global_ctx_buffer_free
nvgpu_gr_global_ctx_buffer_get_mem
nvgpu_gr_global_ctx_buffer_map
nvgpu_gr_global_ctx_buffer_ready
nvgpu_gr_global_ctx_buffer_unmap
nvgpu_gr_global_ctx_compare_golden_images
nvgpu_gr_global_ctx_deinit_local_golden_image
nvgpu_gr_global_ctx_desc_alloc
nvgpu_gr_global_ctx_desc_free
nvgpu_gr_global_ctx_init_local_golden_image
nvgpu_gr_global_ctx_load_local_golden_image
nvgpu_gr_global_ctx_set_size
nvgpu_gr_init
nvgpu_gr_init_support
nvgpu_gr_intr_init_support
nvgpu_gr_intr_remove_support
nvgpu_gr_intr_handle_fecs_error
nvgpu_gr_obj_ctx_alloc
nvgpu_gr_obj_ctx_deinit
nvgpu_gr_obj_ctx_init
nvgpu_gr_obj_ctx_is_golden_image_ready
nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode
nvgpu_gr_prepare_sw
nvgpu_gr_remove_support
nvgpu_gr_subctx_alloc
nvgpu_gr_subctx_free
nvgpu_gr_suspend
nvgpu_gr_sw_ready
nvgpu_hr_timestamp
nvgpu_init_enabled_flags
nvgpu_init_hal
nvgpu_init_ltc_support
nvgpu_init_mm_support
nvgpu_init_therm_support
nvgpu_inst_block_addr
nvgpu_free_inst_block
nvgpu_inst_block_ptr
nvgpu_is_enabled
nvgpu_big_alloc_impl
nvgpu_big_free
nvgpu_kfree_impl
nvgpu_kcalloc_impl
nvgpu_kfree_impl
nvgpu_kmalloc_impl
nvgpu_kmem_cache_alloc
nvgpu_kmem_cache_create
@@ -486,7 +489,13 @@ nvgpu_kmem_cache_destroy
nvgpu_kmem_cache_free
nvgpu_kmem_get_fault_injection
nvgpu_kzalloc_impl
nvgpu_vmalloc_impl
nvgpu_ltc_ecc_free
nvgpu_ltc_get_cacheline_size
nvgpu_ltc_get_ltc_count
nvgpu_ltc_get_slices_per_ltc
nvgpu_ltc_remove_support
nvgpu_ltc_sync_enabled
nvgpu_local_golden_image_get_fault_injection
nvgpu_log_msg_impl
nvgpu_mc_intr_mask
nvgpu_mc_intr_nonstall_pause
@@ -688,6 +697,7 @@ nvgpu_vm_mapping_batch_start
nvgpu_vm_put
nvgpu_vm_put_buffers
nvgpu_vm_unmap
nvgpu_vmalloc_impl
nvgpu_vzalloc_impl
nvgpu_wait_for_deferred_interrupts
nvgpu_writel

66
userspace/required_tests.json
View File

@@ -2021,18 +2021,48 @@
"unit": "nvgpu_allocator",
"test_level": 0
},
{
"test": "test_channel_abort_cleanup",
"case": "abort_cleanup",
"unit": "nvgpu_channel",
"test_level": 0
},
{
"test": "test_channel_alloc_inst",
"case": "alloc_inst",
"unit": "nvgpu_channel",
"test_level": 0
},
{
"test": "test_channel_abort",
"case": "ch_abort",
"unit": "nvgpu_channel",
"test_level": 0
},
{
"test": "test_channel_from_invalid_id",
"case": "channel_from_invalid_id",
"unit": "nvgpu_channel",
"test_level": 0
},
{
"test": "test_channel_put_warn",
"case": "channel_put_warn",
"unit": "nvgpu_channel",
"test_level": 0
},
{
"test": "test_channel_close",
"case": "close",
"unit": "nvgpu_channel",
"test_level": 0
},
{
"test": "test_channel_debug_dump",
"case": "debug_dump",
"unit": "nvgpu_channel",
"test_level": 0
},
{
"test": "test_channel_enable_disable_tsg",
"case": "enable_disable_tsg",
@@ -2045,24 +2075,48 @@
"unit": "nvgpu_channel",
"test_level": 0
},
{
"test": "test_channel_deterministic_idle_unidle",
"case": "idle_unidle",
"unit": "nvgpu_channel",
"test_level": 0
},
{
"test": "test_fifo_init_support",
"case": "init_support",
"unit": "nvgpu_channel",
"test_level": 0
},
{
"test": "test_channel_mark_error",
"case": "mark_error",
"unit": "nvgpu_channel",
"test_level": 0
},
{
"test": "test_channel_open",
"case": "open",
"unit": "nvgpu_channel",
"test_level": 0
},
{
"test": "test_ch_referenceable_cleanup",
"case": "referenceable_cleanup",
"unit": "nvgpu_channel",
"test_level": 0
},
{
"test": "test_fifo_remove_support",
"case": "remove_support",
"unit": "nvgpu_channel",
"test_level": 0
},
{
"test": "test_channel_semaphore_wakeup",
"case": "semaphore_wakeup",
"unit": "nvgpu_channel",
"test_level": 0
},
{
"test": "test_channel_setup_bind",
"case": "setup_bind",
@@ -2075,6 +2129,18 @@
"unit": "nvgpu_channel",
"test_level": 0
},
{
"test": "test_channel_suspend_resume_serviceable_chs",
"case": "suspend_resume",
"unit": "nvgpu_channel",
"test_level": 0
},
{
"test": "test_channel_sw_quiesce",
"case": "sw_quiesce",
"unit": "nvgpu_channel",
"test_level": 0
},
{
"test": "test_gk20a_channel_disable",
"case": "disable",

981
userspace/units/fifo/channel/nvgpu-channel.c
View File

File diff suppressed because it is too large Load Diff

250
userspace/units/fifo/channel/nvgpu-channel.h
View File

@@ -42,6 +42,9 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: nvgpu_channel_setup_sw, nvgpu_channel_init_support,
* nvgpu_channel_destroy, nvgpu_channel_cleanup_sw
*
* Input: None
*
* Steps:
@@ -54,7 +57,7 @@ struct gk20a;
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/
int test_channel_setup_sw(struct unit_module *m,
struct gk20a *g, void *args);
struct gk20a *g, void *vargs);
/**
* Test specification for: test_channel_open
@@ -63,6 +66,8 @@ int test_channel_setup_sw(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: nvgpu_channel_open_new
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -92,7 +97,7 @@ int test_channel_setup_sw(struct unit_module *m,
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/
int test_channel_open(struct unit_module *m,
struct gk20a *g, void *args);
struct gk20a *g, void *vargs);
/**
* Test specification for: test_channel_close
@@ -101,6 +106,13 @@ int test_channel_open(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: nvgpu_channel_close, nvgpu_channel_kill, channel_free,
* channel_free_invoke_unbind, channel_free_wait_for_refs,
* channel_free_invoke_deferred_engine_reset,
* channel_free_invoke_sync_destroy,
* channel_free_put_deterministic_ref_from_init,
* channel_free_unlink_debug_session
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -122,8 +134,7 @@ int test_channel_open(struct unit_module *m,
*
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/
int test_channel_close(struct unit_module *m,
struct gk20a *g, void *args);
int test_channel_close(struct unit_module *m, struct gk20a *g, void *vargs);
/**
* Test specification for: test_channel_setup_bind
@@ -132,6 +143,8 @@ int test_channel_close(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: nvgpu_channel_setup_bind, nvgpu_channel_setup_usermode
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -160,7 +173,7 @@ int test_channel_close(struct unit_module *m,
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/
int test_channel_setup_bind(struct unit_module *m,
struct gk20a *g, void *args);
struct gk20a *g, void *vargs);
/**
* Test specification for: test_channel_alloc_inst
@@ -169,6 +182,8 @@ int test_channel_setup_bind(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: nvgpu_channel_alloc_inst, nvgpu_channel_free_inst
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -186,7 +201,7 @@ int test_channel_setup_bind(struct unit_module *m,
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/
int test_channel_alloc_inst(struct unit_module *m,
struct gk20a *g, void *args);
struct gk20a *g, void *vargs);
/**
* Test specification for: test_channel_from_inst
@@ -195,6 +210,8 @@ int test_channel_alloc_inst(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: nvgpu_channel_refch_from_inst_ptr
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -209,7 +226,7 @@ int test_channel_alloc_inst(struct unit_module *m,
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/
int test_channel_from_inst(struct unit_module *m,
struct gk20a *g, void *args);
struct gk20a *g, void *vargs);
/**
* Test specification for: test_channel_enable_disable_tsg
@@ -218,6 +235,8 @@ int test_channel_from_inst(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: nvgpu_channel_enable_tsg, nvgpu_channel_disable_tsg
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -232,7 +251,222 @@ int test_channel_from_inst(struct unit_module *m,
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/
int test_channel_enable_disable_tsg(struct unit_module *m,
struct gk20a *g, void *args);
struct gk20a *g, void *vargs);
/**
* Test specification for: test_channel_abort
*
* Description: Test channel TSG abort
*
* Test Type: Feature based
*
* Targets: nvgpu_channel_abort
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
* - Test that TSG abort is invoked for TSG bound channel.
*
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/
int test_channel_abort(struct unit_module *m, struct gk20a *g, void *vargs);
/**
* Test specification for: test_channel_mark_error
*
* Description: Mark channel as unserviceable
*
* Test Type: Feature based
*
* Targets: nvgpu_channel_mark_error, nvgpu_channel_set_unserviceable,
* nvgpu_channel_ctxsw_timeout_debug_dump_state,
* nvgpu_channel_set_has_timedout_and_wakeup_wqs
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
* - Test that the channel can be marked with error (unserviceable).
* - Test broadcast condition fail cases.
*
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/
int test_channel_mark_error(struct unit_module *m,
struct gk20a *g, void *vargs);
/**
* Test specification for: test_channel_sw_quiesce
*
* Description: Test emergency quiescing of channels
*
* Test Type: Feature based
*
* Targets: nvgpu_channel_sw_quiesce, nvgpu_channel_set_error_notifier
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
* - Check if channel can be placed in quiesce state.
*
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/
int test_channel_sw_quiesce(struct unit_module *m,
struct gk20a *g, void *vargs);
/**
* Test specification for: test_channel_deterministic_idle_unidle
*
* Description: Stop and allow deterministic channel activity
*
* Test Type: Feature based
*
* Targets: nvgpu_channel_deterministic_idle, nvgpu_channel_deterministic_unidle
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
* - Execute deterministic idle and unidle functions and check if gpu usage
* usage count is updated corresponding to input conditions.
*
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/
int test_channel_deterministic_idle_unidle(struct unit_module *m,
struct gk20a *g, void *vargs);
/**
* Test specification for: test_channel_suspend_resume_serviceable_chs
*
* Description: Test suspend resume of all servicable channels
*
* Test Type: Feature based
*
* Targets: nvgpu_channel_suspend_all_serviceable_ch,
* nvgpu_channel_resume_all_serviceable_ch,
* nvgpu_channel_check_unserviceable
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
* - Check if channels can be suspended and resumed.
*
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/
int test_channel_suspend_resume_serviceable_chs(struct unit_module *m,
struct gk20a *g, void *vargs);
/**
* Test specification for: test_channel_debug_dump
*
* Description: Dump channel debug information
*
* Test Type: Feature based
*
* Targets: nvgpu_channel_debug_dump_all
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
* - Dump all debug information for channels.
*
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/
int test_channel_debug_dump(struct unit_module *m,
struct gk20a *g, void *vargs);
/**
* Test specification for: test_channel_semaphore_wakeup
*
* Description: Wake up threads waiting for semaphore
*
* Test Type: Feature based
*
* Targets: nvgpu_channel_semaphore_wakeup
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
* - Execute semaphore_wakeup for deterministic/non-deterministic channels.
*
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/
int test_channel_semaphore_wakeup(struct unit_module *m,
struct gk20a *g, void *vargs);
/**
* Test specification for: test_channel_from_invalid_id
*
* Description: Test channel reference extracted using channel id
*
* Test Type: Feature based
*
* Targets: nvgpu_channel_from_id
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
* - Test corner case to retrieve channel with invalid channel id.
*
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/
int test_channel_from_invalid_id(struct unit_module *m, struct gk20a *g,
void *vargs);
/**
* Test specification for: test_channel_put_warn
*
* Description: Test channel dereference
*
* Test Type: Feature based
*
* Targets: nvgpu_channel_put__func
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
* - Test corner cases using referenceable channel and condition broadcast fail
* cases.
*
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/
int test_channel_put_warn(struct unit_module *m, struct gk20a *g, void *vargs);
/**
* Test specification for: test_ch_referenceable_cleanup
*
* Description: Test channel cleanup corner case
*
* Test Type: Feature based
*
* Targets: nvgpu_channel_cleanup_sw
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
* - Open a channel. Test how referenceable channel is cleaned-up/freed.
*
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/
int test_ch_referenceable_cleanup(struct unit_module *m,
struct gk20a *g, void *vargs);
/**
* Test specification for: test_channel_abort_cleanup
*
* Description: Test channel abort cleanup with user_sync available
*
* Test Type: Feature based
*
* Targets: nvgpu_channel_abort_clean_up
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
* - Bind channel to TSG and allocate channel user_sync. Test channel abort
* cleanup while unbinding from TSG.
*
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/
int test_channel_abort_cleanup(struct unit_module *m, struct gk20a *g,
void *vargs);
/**
* @}
*/