diff --git a/drivers/gpu/nvgpu/common/pmu/fw/fw.c b/drivers/gpu/nvgpu/common/pmu/fw/fw.c
index ce9682de7..a54e6a87b 100644
--- a/drivers/gpu/nvgpu/common/pmu/fw/fw.c
+++ b/drivers/gpu/nvgpu/common/pmu/fw/fw.c
@@ -33,9 +33,7 @@
 #include <nvgpu/pmu/fw.h>
 #include <nvgpu/pmu/pmu_pg.h>
 
-/* PMU NS UCODE IMG */
-#define NVGPU_PMU_NS_UCODE_IMAGE	"gpmu_ucode.bin"
-/* PMU SECURE UCODE IMG */
+/* PMU UCODE IMG */
 #define NVGPU_PMU_UCODE_IMAGE "gpmu_ucode_image.bin"
 #define NVGPU_PMU_UCODE_DESC "gpmu_ucode_desc.bin"
 #define NVGPU_PMU_UCODE_SIG "pmu_sig.bin"
@@ -211,40 +209,28 @@ static int pmu_fw_read_and_init_ops(struct gk20a *g, struct nvgpu_pmu *pmu,
 
 	nvgpu_log_fn(g, " ");
 
-	if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
-		/* non-secure PMU boot uocde */
-		rtos_fw->fw_image = nvgpu_request_firmware(g,
-				NVGPU_PMU_NS_UCODE_IMAGE, 0);
-		if (rtos_fw->fw_image == NULL) {
-			nvgpu_err(g,
-				"failed to load non-secure pmu ucode!!");
-			goto exit;
-		}
+	/* secure boot ucodes's */
+	nvgpu_pmu_dbg(g, "requesting PMU ucode image");
+	rtos_fw->fw_image =
+		nvgpu_request_firmware(g,
+			NVGPU_PMU_UCODE_IMAGE, 0);
+	if (rtos_fw->fw_image == NULL) {
+		nvgpu_err(g, "failed to load pmu ucode!!");
+		err = -ENOENT;
+		goto exit;
+	}
 
-		desc = (struct pmu_ucode_desc *)
-			(void *)rtos_fw->fw_image->data;
-	} else {
-		/* secure boot ucodes's */
-		nvgpu_pmu_dbg(g, "requesting PMU ucode image");
-		rtos_fw->fw_image =
-			nvgpu_request_firmware(g,
-				NVGPU_PMU_UCODE_IMAGE, 0);
-		if (rtos_fw->fw_image == NULL) {
-			nvgpu_err(g, "failed to load pmu ucode!!");
-			err = -ENOENT;
-			goto exit;
-		}
-
-		nvgpu_pmu_dbg(g, "requesting PMU ucode desc");
-		rtos_fw->fw_desc =
-			nvgpu_request_firmware(g,
-				NVGPU_PMU_UCODE_DESC, 0);
-		if (rtos_fw->fw_desc == NULL) {
-			nvgpu_err(g, "failed to load pmu ucode desc!!");
-			err = -ENOENT;
-			goto release_img_fw;
-		}
+	nvgpu_pmu_dbg(g, "requesting PMU ucode desc");
+	rtos_fw->fw_desc =
+		nvgpu_request_firmware(g,
+			NVGPU_PMU_UCODE_DESC, 0);
+	if (rtos_fw->fw_desc == NULL) {
+		nvgpu_err(g, "failed to load pmu ucode desc!!");
+		err = -ENOENT;
+		goto release_img_fw;
+	}
 
+	if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
 		nvgpu_pmu_dbg(g, "requesting PMU ucode sign");
 		rtos_fw->fw_sig =
 			nvgpu_request_firmware(g,
@@ -254,11 +240,11 @@ static int pmu_fw_read_and_init_ops(struct gk20a *g, struct nvgpu_pmu *pmu,
 			err = -ENOENT;
 			goto release_desc;
 		}
-
-		desc = (struct pmu_ucode_desc *)(void *)
-					rtos_fw->fw_desc->data;
 	}
 
+	desc = (struct pmu_ucode_desc *)(void *)
+				rtos_fw->fw_desc->data;
+
 	err = nvgpu_pmu_init_fw_ver_ops(g, pmu, desc->app_version);
 	if (err != 0) {
 		nvgpu_err(g, "failed to set function pointers");
diff --git a/drivers/gpu/nvgpu/common/pmu/fw/fw_ns_bootstrap.c b/drivers/gpu/nvgpu/common/pmu/fw/fw_ns_bootstrap.c
index ccbb77dd1..24f095394 100644
--- a/drivers/gpu/nvgpu/common/pmu/fw/fw_ns_bootstrap.c
+++ b/drivers/gpu/nvgpu/common/pmu/fw/fw_ns_bootstrap.c
@@ -39,8 +39,8 @@ static int pmu_prepare_ns_ucode_blob(struct gk20a *g)
 
 	nvgpu_log_fn(g, " ");
 
-	desc = (struct pmu_ucode_desc *)(void *)rtos_fw->fw_image->data;
-	ucode_image = (u32 *)(void *)((u8 *)desc + desc->descriptor_size);
+	desc = (struct pmu_ucode_desc *)(void *)rtos_fw->fw_desc->data;
+	ucode_image = (u32 *)(void *)rtos_fw->fw_image->data;
 
 	if (!nvgpu_mem_is_valid(&rtos_fw->ucode)) {
 		err = nvgpu_dma_alloc_map_sys(vm, PMU_RTOS_UCODE_SIZE_MAX,
diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c
index 8c1f4757d..8485ba24a 100644
--- a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c
@@ -625,7 +625,7 @@ int gk20a_pmu_ns_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu,
 
 	nvgpu_log_fn(g, " ");
 
-	fw = nvgpu_pmu_fw_image_desc(g, pmu);
+	fw = nvgpu_pmu_fw_desc_desc(g, pmu);
 	desc = (struct pmu_ucode_desc *)(void *)fw->data;
 
 	gk20a_writel(g, pwr_falcon_itfen_r(),
diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.c
index ad4702e21..f3f00a2f6 100644
--- a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -146,7 +146,7 @@ int gv11b_pmu_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu,
 
 	nvgpu_log_fn(g, " ");
 
-	fw = nvgpu_pmu_fw_image_desc(g, pmu);
+	fw = nvgpu_pmu_fw_desc_desc(g, pmu);
 	desc = (struct pmu_ucode_desc *)(void *)fw->data;
 
 	nvgpu_writel(g, pwr_falcon_itfen_r(),