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gpu: nvgpu: remove IO_COHERENT flag
This patch removes the IO_COHERENT flag as IO coherence is the default setting. Bug 3959027 Change-Id: I9800c2b8b161f7bdc2d6856639dd03488881882d Signed-off-by: Martin Radev <mradev@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2887630 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -352,9 +352,6 @@ u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm,
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if (flags & NVGPU_VM_MAP_CACHEABLE) {
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if (flags & NVGPU_VM_MAP_CACHEABLE) {
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p->flags = TEGRA_VGPU_MAP_CACHEABLE;
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p->flags = TEGRA_VGPU_MAP_CACHEABLE;
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}
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}
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if (flags & NVGPU_VM_MAP_IO_COHERENT) {
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p->flags |= TEGRA_VGPU_MAP_IO_COHERENT;
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}
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if (flags & NVGPU_VM_MAP_L3_ALLOC) {
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if (flags & NVGPU_VM_MAP_L3_ALLOC) {
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p->flags |= TEGRA_VGPU_MAP_L3_ALLOC;
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p->flags |= TEGRA_VGPU_MAP_L3_ALLOC;
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}
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}
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@@ -179,7 +179,6 @@ struct tegra_vgpu_as_map_params {
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};
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};
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#define TEGRA_VGPU_MAP_CACHEABLE (1 << 0)
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#define TEGRA_VGPU_MAP_CACHEABLE (1 << 0)
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#define TEGRA_VGPU_MAP_IO_COHERENT (1 << 1)
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#define TEGRA_VGPU_MAP_L3_ALLOC (1 << 2)
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#define TEGRA_VGPU_MAP_L3_ALLOC (1 << 2)
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#define TEGRA_VGPU_MAP_SYSTEM_COHERENT (1 << 3)
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#define TEGRA_VGPU_MAP_SYSTEM_COHERENT (1 << 3)
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@@ -347,7 +347,6 @@ struct vm_gk20a {
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*/
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*/
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#define NVGPU_VM_MAP_FIXED_OFFSET BIT32(0)
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#define NVGPU_VM_MAP_FIXED_OFFSET BIT32(0)
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#define NVGPU_VM_MAP_CACHEABLE BIT32(1)
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#define NVGPU_VM_MAP_CACHEABLE BIT32(1)
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#define NVGPU_VM_MAP_IO_COHERENT BIT32(2)
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#define NVGPU_VM_MAP_UNMAPPED_PTE BIT32(3)
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#define NVGPU_VM_MAP_UNMAPPED_PTE BIT32(3)
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#define NVGPU_VM_MAP_L3_ALLOC BIT32(5)
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#define NVGPU_VM_MAP_L3_ALLOC BIT32(5)
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#define NVGPU_VM_MAP_SYSTEM_COHERENT BIT32(6)
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#define NVGPU_VM_MAP_SYSTEM_COHERENT BIT32(6)
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@@ -58,10 +58,6 @@ static int nvgpu_vm_translate_linux_flags(struct gk20a *g, u32 flags, u32 *out_c
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core_flags |= NVGPU_VM_MAP_CACHEABLE;
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core_flags |= NVGPU_VM_MAP_CACHEABLE;
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consumed_flags |= NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE;
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consumed_flags |= NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE;
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}
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}
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if ((flags & NVGPU_AS_MAP_BUFFER_FLAGS_IO_COHERENT) != 0U) {
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core_flags |= NVGPU_VM_MAP_IO_COHERENT;
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consumed_flags |= NVGPU_AS_MAP_BUFFER_FLAGS_IO_COHERENT;
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}
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if ((flags & NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE) != 0U) {
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if ((flags & NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE) != 0U) {
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core_flags |= NVGPU_VM_MAP_UNMAPPED_PTE;
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core_flags |= NVGPU_VM_MAP_UNMAPPED_PTE;
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consumed_flags |= NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE;
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consumed_flags |= NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE;
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@@ -104,7 +104,6 @@ struct nvgpu_as_bind_channel_args {
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*/
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*/
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#define NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET (1 << 0)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET (1 << 0)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE (1 << 2)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE (1 << 2)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_IO_COHERENT (1 << 4)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE (1 << 5)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE (1 << 5)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS (1 << 6)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS (1 << 6)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC (1 << 7)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC (1 << 7)
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@@ -140,12 +139,6 @@ struct nvgpu_as_bind_channel_args {
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*
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*
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* Specify that a mapping shall be GPU cachable.
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* Specify that a mapping shall be GPU cachable.
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*
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*
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* %NVGPU_AS_MAP_BUFFER_FLAGS_IO_COHERENT
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*
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* Specify that a mapping shall be IO coherent.
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*
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* DEPRECATED: do not use! This will be removed in a future update.
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*
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* %NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE
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* %NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE
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*
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*
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* Specify that a mapping shall be marked as invalid but otherwise
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* Specify that a mapping shall be marked as invalid but otherwise
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* copy of this software and associated documentation files (the "Software"),
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@@ -124,7 +124,7 @@ static struct test_parameters test_iommu_sysmem_coh = {
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.aperture = APERTURE_SYSMEM,
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.aperture = APERTURE_SYSMEM,
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.is_iommuable = true,
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.is_iommuable = true,
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.rw_flag = gk20a_mem_flag_none,
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.rw_flag = gk20a_mem_flag_none,
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.flags = NVGPU_VM_MAP_CACHEABLE | NVGPU_VM_MAP_IO_COHERENT,
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.flags = NVGPU_VM_MAP_CACHEABLE,
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.priv = false,
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.priv = false,
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};
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};
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@@ -760,10 +760,6 @@ static u64 gmmu_map_advanced(struct unit_module *m, struct gk20a *g,
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mem->cpu_va = NULL;
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mem->cpu_va = NULL;
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}
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}
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if (nvgpu_is_enabled(g, NVGPU_USE_COHERENT_SYSMEM)) {
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params->flags |= NVGPU_VM_MAP_IO_COHERENT;
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}
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nvgpu_mutex_acquire(&vm->update_gmmu_lock);
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nvgpu_mutex_acquire(&vm->update_gmmu_lock);
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vaddr = g->ops.mm.gmmu.map(vm, (u64) mem->cpu_va,
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vaddr = g->ops.mm.gmmu.map(vm, (u64) mem->cpu_va,
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