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gpu: nvgpu: update static pg support for pre-si

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- On pre-silicon platform, static pg will be
  done by nvgpu driver. For this, retain structs
  and HALs of static pg.
- Add the static pg support under pre-silicon code.
- On silicon, the static pg will be done by BPMP.
- Rename variables used in static pg for better
  readability and consistency

Bug 200768322
JIRA NVGPU-6433

Change-Id: Ib31c0f83b751c2b1563a36bd51af78a0bd12a117
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2594801
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Divya
2021-09-18 15:40:43 +00:00
committed by mobile promotions
parent 72c3bce602
commit 9266da636b
14 changed files with 126 additions and 105 deletions
Download Patch File Download Diff File Expand all files Collapse all files

70
drivers/gpu/nvgpu/common/init/nvgpu_init.c
View File

@@ -439,47 +439,51 @@ static int nvgpu_init_power_gate(struct gk20a *g)
u32 fuse_status = 0x0; u32 fuse_status = 0x0;
/* /*
* Floorsweep the FBP as per the FBP_FS mask * Pre-Silicon - Static pg feature related settings
* and the fuse_status register. * are done in nvgpu driver.
* If FBP_FS mask is invalid, return error. * Silicon - Static pg feature related settings
* are done in BPMP.
*/ */
if (!(nvgpu_platform_is_silicon(g))) {
/*
* Set the fbp_pg mask. If fbp_pg mask is invalid
* halt the GPU poweron.
*/
g->can_fbp_pg = false;
g->can_fbp_fs = false; if (g->ops.fbp_pg.init_fbp_pg != NULL) {
err = g->ops.fbp_pg.init_fbp_pg(g, &g->can_fbp_pg);
if (g->ops.fbp_fs.init_fbp_floorsweep != NULL) {
err = g->ops.fbp_fs.init_fbp_floorsweep(g, &g->can_fbp_fs);
if (err != 0) { if (err != 0) {
return err; return err;
} }
} }
/* /*
* Floorsweep the GPC as per the GPC_FS mask * Set the gpc_pg mask. If gpc_pg mask is invalid
* and the fuse_status register. * halt the GPU poweron.
* If GPC_FS mask is invalid halt the GPU poweron.
*/ */
g->can_gpc_pg = false;
g->can_gpc_fs = false; if (g->ops.gpc_pg.init_gpc_pg != NULL) {
err = g->ops.gpc_pg.init_gpc_pg(g, &g->can_gpc_pg);
if (g->ops.gpc_pg.init_gpc_powergate != NULL) {
err = g->ops.gpc_pg.init_gpc_powergate(g, &g->can_gpc_fs);
if (err != 0) { if (err != 0) {
return err; return err;
} }
} }
}
/* /*
* Powergate the chip as per the TPC PG mask * static TPC PG for GV11b is done in NvGPU driver
* and the fuse_status register. * set the tpc_pg mask. If tpc_pg mask is invalid
* If TPC PG mask is invalid halt the GPU poweron. * halt the GPU poweron.
*/ */
g->can_tpc_powergate = false; g->can_tpc_pg = false;
if (g->ops.fuse.fuse_status_opt_tpc_gpc != NULL) { if (g->ops.fuse.fuse_status_opt_tpc_gpc != NULL) {
fuse_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0); fuse_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0);
} }
if (g->ops.tpc.init_tpc_powergate != NULL) { if (g->ops.tpc_pg.init_tpc_pg != NULL) {
err = g->ops.tpc.init_tpc_powergate(g, fuse_status); err = g->ops.tpc_pg.init_tpc_pg(g, fuse_status);
if (err != 0) { if (err != 0) {
return err; return err;
} }
@@ -490,19 +494,27 @@ static int nvgpu_init_power_gate(struct gk20a *g)
static int nvgpu_init_power_gate_gr(struct gk20a *g) static int nvgpu_init_power_gate_gr(struct gk20a *g)
{ {
/* Floorsweep FBP */ /*
if (g->can_fbp_fs && (g->ops.fbp_fs.fbp_static_fs != NULL)) { * Pre-Silicon - Static pg feature related settings
g->ops.fbp_fs.fbp_static_fs(g); * are done in nvgpu driver.
* Silicon - Static pg feature related settings
* are done in BPMP.
*/
if (!(nvgpu_platform_is_silicon(g))) {
/* powergate FBP as per fbp_pg mask */
if (g->can_fbp_pg && (g->ops.fbp_pg.fbp_pg != NULL)) {
g->ops.fbp_pg.fbp_pg(g);
} }
/* Floorsweep GPC */ /* powergate GPC as per gpc_pg mask*/
if (g->can_gpc_fs && (g->ops.gpc_pg.gpc_static_pg != NULL)) { if (g->can_gpc_pg && (g->ops.gpc_pg.gpc_pg != NULL)) {
g->ops.gpc_pg.gpc_static_pg(g); g->ops.gpc_pg.gpc_pg(g);
}
} }
/* Floorsweep TPC */ /* powergate TPC as per tpc_pg mask*/
if (g->can_tpc_powergate && (g->ops.tpc.tpc_gr_pg != NULL)) { if (g->can_tpc_pg && (g->ops.tpc_pg.tpc_pg != NULL)) {
g->ops.tpc.tpc_gr_pg(g); g->ops.tpc_pg.tpc_pg(g);
} }
return 0; return 0;
} }

19
drivers/gpu/nvgpu/hal/init/hal_ga10b.c
View File

@@ -246,7 +246,7 @@
#include "hal/fifo/channel_gv11b.h" #include "hal/fifo/channel_gv11b.h"
#include "hal/fifo/channel_ga10b.h" #include "hal/fifo/channel_ga10b.h"
#ifdef CONFIG_NVGPU_TPC_POWERGATE #ifdef CONFIG_NVGPU_STATIC_POWERGATE
#include "hal/tpc/tpc_gv11b.h" #include "hal/tpc/tpc_gv11b.h"
#endif #endif
@@ -1631,10 +1631,19 @@ static const struct gops_top ga10b_ops_top = {
.get_num_lce = gv11b_top_get_num_lce, .get_num_lce = gv11b_top_get_num_lce,
}; };
#ifdef CONFIG_NVGPU_TPC_POWERGATE #ifdef CONFIG_NVGPU_STATIC_POWERGATE
static const struct gops_tpc ga10b_ops_tpc = { static const struct gops_tpc_pg ga10b_ops_tpc_pg = {
.init_tpc_powergate = gv11b_tpc_powergate, /*
.tpc_gr_pg = gv11b_gr_pg_tpc, * HALs for static-pg will be updated
* for pre-silicon platform during HAL init.
* For silicon, static-pg feature related settings
* will be taken care of by BPMP.
* Silicon: assigining the HALs to NULL.
* Pre-Silicon: To-do JIRA-NVGPU-7112
* to add these HALs
*/
.init_tpc_pg = NULL,
.tpc_pg = NULL,
}; };
#endif #endif

20
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -1056,19 +1056,19 @@ static const struct gops_top gm20b_ops_top = {
}; };
#ifdef CONFIG_NVGPU_STATIC_POWERGATE #ifdef CONFIG_NVGPU_STATIC_POWERGATE
static const struct gops_tpc gm20b_ops_tpc = { static const struct gops_tpc_pg gm20b_ops_tpc_pg = {
.init_tpc_powergate = NULL, .init_tpc_pg = NULL,
.tpc_gr_pg = NULL, .tpc_pg = NULL,
}; };
static const struct gops_fbp_fs gm20b_ops_fbp_fs = { static const struct gops_fbp_pg gm20b_ops_fbp_pg = {
.init_fbp_floorsweep = NULL, .init_fbp_pg = NULL,
.fbp_static_fs = NULL, .fbp_pg = NULL,
}; };
static const struct gops_gpc_pg gm20b_ops_gpc_pg = { static const struct gops_gpc_pg gm20b_ops_gpc_pg = {
.init_gpc_powergate = NULL, .init_gpc_pg = NULL,
.gpc_static_pg = NULL, .gpc_pg = NULL,
}; };
#endif #endif
@@ -1183,8 +1183,8 @@ int gm20b_init_hal(struct gk20a *g)
gops->fuse = gm20b_ops_fuse; gops->fuse = gm20b_ops_fuse;
gops->top = gm20b_ops_top; gops->top = gm20b_ops_top;
#ifdef CONFIG_NVGPU_STATIC_POWERGATE #ifdef CONFIG_NVGPU_STATIC_POWERGATE
gops->tpc = gm20b_ops_tpc; gops->tpc_pg = gm20b_ops_tpc_pg;
gops->fbp_fs = gm20b_ops_fbp_fs; gops->fbp_pg = gm20b_ops_fbp_pg;
gops->gpc_pg = gm20b_ops_gpc_pg; gops->gpc_pg = gm20b_ops_gpc_pg;
#endif #endif
gops->grmgr = gm20b_ops_grmgr; gops->grmgr = gm20b_ops_grmgr;

20
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -1156,19 +1156,19 @@ static const struct gops_top gp10b_ops_top = {
}; };
#ifdef CONFIG_NVGPU_STATIC_POWERGATE #ifdef CONFIG_NVGPU_STATIC_POWERGATE
static const struct gops_tpc gp10b_ops_tpc = { static const struct gops_tpc_pg gp10b_ops_tpc_pg = {
.init_tpc_powergate = NULL, .init_tpc_pg = NULL,
.tpc_gr_pg = NULL, .tpc_pg = NULL,
}; };
static const struct gops_fbp_fs gp10b_ops_fbp_fs = { static const struct gops_fbp_pg gp10b_ops_fbp_pg = {
.init_fbp_floorsweep = NULL, .init_fbp_pg = NULL,
.fbp_static_fs = NULL, .fbp_pg = NULL,
}; };
static const struct gops_gpc_pg gp10b_ops_gpc_pg = { static const struct gops_gpc_pg gp10b_ops_gpc_pg = {
.init_gpc_powergate = NULL, .init_gpc_pg = NULL,
.gpc_static_pg = NULL, .gpc_pg = NULL,
}; };
#endif #endif
@@ -1273,8 +1273,8 @@ int gp10b_init_hal(struct gk20a *g)
gops->fuse = gp10b_ops_fuse; gops->fuse = gp10b_ops_fuse;
gops->top = gp10b_ops_top; gops->top = gp10b_ops_top;
#ifdef CONFIG_NVGPU_STATIC_POWERGATE #ifdef CONFIG_NVGPU_STATIC_POWERGATE
gops->tpc = gp10b_ops_tpc; gops->tpc_pg = gp10b_ops_tpc_pg;
gops->fbp_fs = gp10b_ops_fbp_fs; gops->fbp_pg = gp10b_ops_fbp_pg;
gops->gpc_pg = gp10b_ops_gpc_pg; gops->gpc_pg = gp10b_ops_gpc_pg;
#endif #endif
gops->grmgr = gp10b_ops_grmgr; gops->grmgr = gp10b_ops_grmgr;

20
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -1438,19 +1438,19 @@ static const struct gops_top gv11b_ops_top = {
}; };
#ifdef CONFIG_NVGPU_STATIC_POWERGATE #ifdef CONFIG_NVGPU_STATIC_POWERGATE
static const struct gops_tpc gv11b_ops_tpc = { static const struct gops_tpc_pg gv11b_ops_tpc_pg = {
.init_tpc_powergate = gv11b_tpc_powergate, .init_tpc_pg = gv11b_tpc_pg,
.tpc_gr_pg = gv11b_gr_pg_tpc, .tpc_pg = gv11b_gr_pg_tpc,
}; };
static const struct gops_fbp_fs gv11b_ops_fbp_fs = { static const struct gops_fbp_pg gv11b_ops_fbp_pg = {
.init_fbp_floorsweep = NULL, .init_fbp_pg = NULL,
.fbp_static_fs = NULL, .fbp_pg = NULL,
}; };
static const struct gops_gpc_pg gv11b_ops_gpc_pg = { static const struct gops_gpc_pg gv11b_ops_gpc_pg = {
.init_gpc_powergate = NULL, .init_gpc_pg = NULL,
.gpc_static_pg = NULL, .gpc_pg = NULL,
}; };
#endif #endif
@@ -1556,8 +1556,8 @@ int gv11b_init_hal(struct gk20a *g)
gops->fuse = gv11b_ops_fuse; gops->fuse = gv11b_ops_fuse;
gops->top = gv11b_ops_top; gops->top = gv11b_ops_top;
#ifdef CONFIG_NVGPU_STATIC_POWERGATE #ifdef CONFIG_NVGPU_STATIC_POWERGATE
gops->tpc = gv11b_ops_tpc; gops->tpc_pg = gv11b_ops_tpc_pg;
gops->fbp_fs = gv11b_ops_fbp_fs; gops->fbp_pg = gv11b_ops_fbp_pg;
gops->gpc_pg = gv11b_ops_gpc_pg; gops->gpc_pg = gv11b_ops_gpc_pg;
#endif #endif
gops->grmgr = gv11b_ops_grmgr; gops->grmgr = gv11b_ops_grmgr;

14
drivers/gpu/nvgpu/hal/tpc/tpc_gv11b.c
View File

@@ -1,7 +1,7 @@
/* /*
* GV11B TPC * GV11B TPC
* *
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -24,12 +24,12 @@
#include <nvgpu/gk20a.h> #include <nvgpu/gk20a.h>
#include "tpc_gv11b.h" #include "tpc_gv11b.h"
int gv11b_tpc_powergate(struct gk20a *g, u32 fuse_status) int gv11b_tpc_pg(struct gk20a *g, u32 fuse_status)
{ {
int err = 0; int err = 0;
if (fuse_status == 0x0) { if (fuse_status == 0x0) {
g->can_tpc_powergate = true; g->can_tpc_pg = true;
} else { } else {
/* if hardware has already floorswept any TPC /* if hardware has already floorswept any TPC
@@ -40,15 +40,15 @@ int gv11b_tpc_powergate(struct gk20a *g, u32 fuse_status)
* thus, set g->tpc_pg_mask to fuse_status value * thus, set g->tpc_pg_mask to fuse_status value
*/ */
if (g->tpc_pg_mask == 0x0) { if (g->tpc_pg_mask == 0x0) {
g->can_tpc_powergate = true; g->can_tpc_pg = true;
g->tpc_pg_mask = fuse_status; g->tpc_pg_mask = fuse_status;
} else if (fuse_status == g->tpc_pg_mask) { } else if (fuse_status == g->tpc_pg_mask) {
g->can_tpc_powergate = true; g->can_tpc_pg = true;
} else if ((fuse_status & g->tpc_pg_mask) == } else if ((fuse_status & g->tpc_pg_mask) ==
fuse_status) { fuse_status) {
g->can_tpc_powergate = true; g->can_tpc_pg = true;
} else { } else {
/* If userspace sends a TPC PG mask such that /* If userspace sends a TPC PG mask such that
@@ -60,7 +60,7 @@ int gv11b_tpc_powergate(struct gk20a *g, u32 fuse_status)
*/ */
nvgpu_err(g, "Invalid TPC_PG mask: 0x%x", nvgpu_err(g, "Invalid TPC_PG mask: 0x%x",
g->tpc_pg_mask); g->tpc_pg_mask);
g->can_tpc_powergate = false; g->can_tpc_pg = false;
g->tpc_pg_mask = 0x0; g->tpc_pg_mask = 0x0;
err = -EINVAL; err = -EINVAL;
} }

4
drivers/gpu/nvgpu/hal/tpc/tpc_gv11b.h
View File

@@ -1,7 +1,7 @@
/* /*
* GV11B TPC * GV11B TPC
* *
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -27,7 +27,7 @@
struct gk20a; struct gk20a;
int gv11b_tpc_powergate(struct gk20a *g, u32 fuse_status); int gv11b_tpc_pg(struct gk20a *g, u32 fuse_status);
void gv11b_gr_pg_tpc(struct gk20a *g); void gv11b_gr_pg_tpc(struct gk20a *g);
#endif /* NVGPU_TPC_GV11B_H */ #endif /* NVGPU_TPC_GV11B_H */

10
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -726,11 +726,11 @@ struct gk20a {
/** @cond DOXYGEN_SHOULD_SKIP_THIS */ /** @cond DOXYGEN_SHOULD_SKIP_THIS */
u32 tpc_pg_mask; u32 tpc_pg_mask;
bool can_tpc_powergate; u32 fbp_pg_mask;
u32 fbp_mask; u32 gpc_pg_mask;
bool can_fbp_fs; bool can_tpc_pg;
u32 gpc_mask; bool can_fbp_pg;
bool can_gpc_fs; bool can_gpc_pg;
u32 valid_tpc_mask[MAX_TPC_PG_CONFIGS]; u32 valid_tpc_mask[MAX_TPC_PG_CONFIGS];
u32 valid_gpc_fbp_fs_mask[MAX_GPC_FBP_FS_CONFIGS]; u32 valid_gpc_fbp_fs_mask[MAX_GPC_FBP_FS_CONFIGS];

16
drivers/gpu/nvgpu/include/nvgpu/gops/floorsweep.h
View File

@@ -23,19 +23,19 @@
#define NVGPU_GOPS_FLOORSWEEP_H #define NVGPU_GOPS_FLOORSWEEP_H
#ifdef CONFIG_NVGPU_STATIC_POWERGATE #ifdef CONFIG_NVGPU_STATIC_POWERGATE
struct gops_tpc { struct gops_tpc_pg {
int (*init_tpc_powergate)(struct gk20a *g, u32 fuse_status); int (*init_tpc_pg)(struct gk20a *g, u32 fuse_status);
void (*tpc_gr_pg)(struct gk20a *g); void (*tpc_pg)(struct gk20a *g);
}; };
struct gops_fbp_fs { struct gops_fbp_pg {
int (*init_fbp_floorsweep)(struct gk20a *g, bool *can_fbp_fs); int (*init_fbp_pg)(struct gk20a *g, bool *can_fbp_fs);
void (*fbp_static_fs)(struct gk20a *g); void (*fbp_pg)(struct gk20a *g);
}; };
struct gops_gpc_pg { struct gops_gpc_pg {
int (*init_gpc_powergate)(struct gk20a *g, bool *can_gpc_fs); int (*init_gpc_pg)(struct gk20a *g, bool *can_gpc_fs);
void (*gpc_static_pg)(struct gk20a *g); void (*gpc_pg)(struct gk20a *g);
}; };
#endif #endif

4
drivers/gpu/nvgpu/include/nvgpu/gpu_ops.h
View File

@@ -216,8 +216,8 @@ struct gpu_ops {
struct gops_gsp gsp; struct gops_gsp gsp;
/** @endcond */ /** @endcond */
#ifdef CONFIG_NVGPU_STATIC_POWERGATE #ifdef CONFIG_NVGPU_STATIC_POWERGATE
struct gops_tpc tpc; struct gops_tpc_pg tpc_pg;
struct gops_fbp_fs fbp_fs; struct gops_fbp_pg fbp_pg;
struct gops_gpc_pg gpc_pg; struct gops_gpc_pg gpc_pg;
#endif #endif
/** Wake up all threads waiting on semaphore wait. */ /** Wake up all threads waiting on semaphore wait. */

2
drivers/gpu/nvgpu/os/linux/driver_common.c
View File

@@ -184,7 +184,7 @@ static void nvgpu_init_pm_vars(struct gk20a *g)
nvgpu_set_enabled(g, NVGPU_CAN_RAILGATE, nvgpu_set_enabled(g, NVGPU_CAN_RAILGATE,
nvgpu_platform_is_simulation(g)? true : platform->can_railgate_init); nvgpu_platform_is_simulation(g)? true : platform->can_railgate_init);
g->can_tpc_powergate = platform->can_tpc_powergate; g->can_tpc_pg = platform->can_tpc_pg;
for (i = 0; i < MAX_TPC_PG_CONFIGS; i++) for (i = 0; i < MAX_TPC_PG_CONFIGS; i++)
g->valid_tpc_mask[i] = platform->valid_tpc_mask[i]; g->valid_tpc_mask[i] = platform->valid_tpc_mask[i];

2
drivers/gpu/nvgpu/os/linux/platform_ga10b_tegra.c
View File

@@ -322,7 +322,7 @@ struct gk20a_platform ga10b_tegra_platform = {
.can_railgate_init = false, .can_railgate_init = false,
/* add tpc powergate JIRA NVGPU-4683 */ /* add tpc powergate JIRA NVGPU-4683 */
.can_tpc_powergate = false, .can_tpc_pg = false,
.set_tpc_pg_mask = ga10b_tegra_set_tpc_pg_mask, .set_tpc_pg_mask = ga10b_tegra_set_tpc_pg_mask,

6
drivers/gpu/nvgpu/os/linux/platform_gk20a.h
View File

@@ -82,13 +82,13 @@ struct gk20a_platform {
bool can_pci_gc_off; bool can_pci_gc_off;
/* Should be populated at probe. */ /* Should be populated at probe. */
bool can_tpc_powergate; bool can_tpc_pg;
/* Should be populated at probe. */ /* Should be populated at probe. */
bool can_fbp_fs; bool can_fbp_pg;
/* Should be populated at probe. */ /* Should be populated at probe. */
bool can_gpc_fs; bool can_gpc_pg;
/* Should be populated at probe. */ /* Should be populated at probe. */
bool can_elpg_init; bool can_elpg_init;

2
drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
View File

@@ -247,7 +247,7 @@ struct gk20a_platform gv11b_tegra_platform = {
.railgate_delay_init = 500, .railgate_delay_init = 500,
.can_railgate_init = true, .can_railgate_init = true,
.can_tpc_powergate = true, .can_tpc_pg = true,
.valid_tpc_mask[0] = 0x0, .valid_tpc_mask[0] = 0x0,
.valid_tpc_mask[1] = 0x1, .valid_tpc_mask[1] = 0x1,
.valid_tpc_mask[2] = 0x2, .valid_tpc_mask[2] = 0x2,