diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index 32441c5bd..21e861feb 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -138,7 +138,7 @@ int gk20a_prepare_poweroff(struct gk20a *g)
 		ret |= g->ops.clk.suspend_clk_support(g);
 
 #ifdef CONFIG_ARCH_TEGRA_18x_SOC
-	if (g->ops.pmupstate)
+	if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE))
 		gk20a_deinit_pstate_support(g);
 #endif
 	g->power_on = false;
@@ -252,7 +252,7 @@ int gk20a_finalize_poweron(struct gk20a *g)
 	}
 
 #ifdef CONFIG_ARCH_TEGRA_18x_SOC
-	if (g->ops.pmupstate) {
+	if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) {
 		err = gk20a_init_pstate_support(g);
 		if (err) {
 			nvgpu_err(g, "failed to init pstates");
@@ -276,7 +276,7 @@ int gk20a_finalize_poweron(struct gk20a *g)
 	}
 
 #ifdef CONFIG_ARCH_TEGRA_18x_SOC
-	if (g->ops.pmupstate) {
+	if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) {
 		err = gk20a_init_pstate_pmu_support(g);
 		if (err) {
 			nvgpu_err(g, "failed to init pstates");
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index ff8eb988c..17a060998 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -994,7 +994,6 @@ struct gpu_ops {
 	} priv_ring;
 	bool privsecurity;
 	bool securegpccs;
-	bool pmupstate;
 };
 
 struct nvgpu_bios_ucode {
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index bdee11495..7415e6c10 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -352,7 +352,7 @@ int gm20b_init_hal(struct gk20a *g)
 	gops->get_litter_value = gm20b_ops.get_litter_value;
 
 	gops->securegpccs = false;
-	gops->pmupstate = false;
+	__nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
 #ifdef CONFIG_TEGRA_ACR
 	if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
 		gops->privsecurity = 1;
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index fa767c3b0..2a661734b 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -62,6 +62,7 @@
 #include <nvgpu/debug.h>
 #include <nvgpu/bug.h>
 #include <nvgpu/bus.h>
+#include <nvgpu/enabled.h>
 
 #include <nvgpu/hw/gp106/hw_proj_gp106.h>
 #include <nvgpu/hw/gp106/hw_fifo_gp106.h>
@@ -417,8 +418,7 @@ int gp106_init_hal(struct gk20a *g)
 
 	gops->privsecurity = 1;
 	gops->securegpccs = 1;
-	gops->pmupstate = true;
-
+	__nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true);
 
 	g->bootstrap_owner = LSF_FALCON_ID_SEC2;
 	gp106_init_gr(gops);
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index d603703b5..177a7c9f4 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -364,7 +364,8 @@ int gp10b_init_hal(struct gk20a *g)
 		gp10b_ops.chip_init_gpu_characteristics;
 	gops->get_litter_value = gp10b_ops.get_litter_value;
 
-	gops->pmupstate = false;
+	__nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
+
 #ifdef CONFIG_TEGRA_ACR
 	if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
 		gops->privsecurity = 0;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
index 3bfd48990..6fa7dcfa3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
@@ -42,6 +42,7 @@ struct gk20a;
  */
 /* perfmon enabled or disabled for PMU */
 #define NVGPU_PMU_PERFMON			48
+#define NVGPU_PMU_PSTATE			49
 
 /*
  * Must be greater than the largest bit offset in the above list.