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gpu: nvgpu: gsp units separation

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Separated gsp unit into three unit:
- GSP unit which holds the core functionality of GSP RISCV core,
  bootstrap, interrupt, etc.
- GSP Scheduler to hold the cmd/msg management, IPC, etc.
- GSP Test to hold stress test ucode specific support.

NVGPU-7492

Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I12340dc776d610502f28c8574843afc7481c0871
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2660619
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Ramesh Mylavarapu
2022-02-03 17:37:07 +05:30
committed by mobile promotions
parent 14ed75e857
commit 9302b2efee
29 changed files with 871 additions and 630 deletions
Download Patch File Download Diff File Expand all files Collapse all files

142
drivers/gpu/nvgpu/common/gsp/gsp_bootstrap.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -28,25 +28,8 @@
#include <nvgpu/firmware.h>
#include <nvgpu/io.h>
#include <nvgpu/gsp.h>
#include "gsp_priv.h"
#include "gsp_bootstrap.h"
#define GSP_WAIT_TIME_MS 10000U
#define GSP_DBG_RISCV_FW_MANIFEST "sample-gsp.manifest.encrypt.bin.out.bin"
#define GSP_DBG_RISCV_FW_CODE "sample-gsp.text.encrypt.bin"
#define GSP_DBG_RISCV_FW_DATA "sample-gsp.data.encrypt.bin"
#ifdef CONFIG_NVGPU_GSP_STRESS_TEST
#define GSPDBG_RISCV_STRESS_TEST_FW_MANIFEST "gsp-stress.manifest.encrypt.bin.out.bin"
#define GSPDBG_RISCV_STRESS_TEST_FW_CODE "gsp-stress.text.encrypt.bin"
#define GSPDBG_RISCV_STRESS_TEST_FW_DATA "gsp-stress.data.encrypt.bin"
#define GSPPROD_RISCV_STRESS_TEST_FW_MANIFEST "gsp-stress.manifest.encrypt.bin.out.bin.prod"
#define GSPPROD_RISCV_STRESS_TEST_FW_CODE "gsp-stress.text.encrypt.bin.prod"
#define GSPPROD_RISCV_STRESS_TEST_FW_DATA "gsp-stress.data.encrypt.bin.prod"
#define GSP_STRESS_TEST_MAILBOX_PASS 0xAAAAAAAA
#include <nvgpu/gsp/gsp_test.h>
#endif
static void gsp_release_firmware(struct gk20a *g, struct nvgpu_gsp *gsp)
@@ -64,86 +47,45 @@ static void gsp_release_firmware(struct gk20a *g, struct nvgpu_gsp *gsp)
}
}
static int gsp_read_firmware(struct gk20a *g, struct gsp_fw *gsp_ucode)
static int gsp_read_firmware(struct gk20a *g, struct nvgpu_gsp *gsp,
struct gsp_fw *gsp_ucode)
{
const char *gsp_code_name;
const char *gsp_data_name;
const char *gsp_manifest_name;
const char *code_name = gsp_ucode->code_name;
const char *data_name = gsp_ucode->data_name;
const char *manifest_name = gsp_ucode->manifest_name;
nvgpu_log_fn(g, " ");
#ifdef CONFIG_NVGPU_GSP_STRESS_TEST
if (g->gsp->gsp_test.load_stress_test) {
/*
* TODO Switch to GSP specific register
*/
if (g->ops.pmu.is_debug_mode_enabled(g)) {
gsp_code_name = GSPDBG_RISCV_STRESS_TEST_FW_CODE;
gsp_data_name = GSPDBG_RISCV_STRESS_TEST_FW_DATA;
gsp_manifest_name = GSPDBG_RISCV_STRESS_TEST_FW_MANIFEST;
} else {
gsp_code_name = GSPPROD_RISCV_STRESS_TEST_FW_CODE;
gsp_data_name = GSPPROD_RISCV_STRESS_TEST_FW_DATA;
gsp_manifest_name = GSPPROD_RISCV_STRESS_TEST_FW_MANIFEST;
}
} else
#endif
{
gsp_code_name = GSP_DBG_RISCV_FW_CODE;
gsp_data_name = GSP_DBG_RISCV_FW_DATA;
gsp_manifest_name = GSP_DBG_RISCV_FW_MANIFEST;
}
gsp_ucode->manifest = nvgpu_request_firmware(g,
gsp_manifest_name, NVGPU_REQUEST_FIRMWARE_NO_WARN);
manifest_name, NVGPU_REQUEST_FIRMWARE_NO_WARN);
if (gsp_ucode->manifest == NULL) {
nvgpu_err(g, "%s ucode get failed", gsp_manifest_name);
nvgpu_err(g, "%s ucode get failed", manifest_name);
goto fw_release;
}
gsp_ucode->code = nvgpu_request_firmware(g,
gsp_code_name, NVGPU_REQUEST_FIRMWARE_NO_WARN);
code_name, NVGPU_REQUEST_FIRMWARE_NO_WARN);
if (gsp_ucode->code == NULL) {
nvgpu_err(g, "%s ucode get failed", gsp_code_name);
nvgpu_err(g, "%s ucode get failed", code_name);
goto fw_release;
}
gsp_ucode->data = nvgpu_request_firmware(g,
gsp_data_name, NVGPU_REQUEST_FIRMWARE_NO_WARN);
data_name, NVGPU_REQUEST_FIRMWARE_NO_WARN);
if (gsp_ucode->data == NULL) {
nvgpu_err(g, "%s ucode get failed", gsp_data_name);
nvgpu_err(g, "%s ucode get failed", data_name);
goto fw_release;
}
return 0;
fw_release:
gsp_release_firmware(g, g->gsp);
gsp_release_firmware(g, gsp);
return -ENOENT;
}
#ifdef CONFIG_NVGPU_GSP_STRESS_TEST
static void gsp_write_test_sysmem_addr(struct nvgpu_gsp *gsp)
{
struct gk20a *g;
struct nvgpu_falcon *flcn;
u64 sysmem_addr;
g = gsp->g;
flcn = gsp->gsp_flcn;
sysmem_addr = nvgpu_mem_get_addr(g, &gsp->gsp_test.gsp_test_sysmem_block);
nvgpu_falcon_mailbox_write(flcn, FALCON_MAILBOX_0, u64_lo32(sysmem_addr));
nvgpu_falcon_mailbox_write(flcn, FALCON_MAILBOX_1, u64_hi32(sysmem_addr));
}
#endif
static int gsp_ucode_load_and_bootstrap(struct gk20a *g,
struct nvgpu_falcon *flcn,
struct gsp_fw *gsp_ucode)
struct nvgpu_falcon *flcn, struct gsp_fw *gsp_ucode)
{
u32 dmem_size = 0U;
u32 code_size = gsp_ucode->code->size;
@@ -197,8 +139,9 @@ static int gsp_ucode_load_and_bootstrap(struct gk20a *g,
* Update the address of the allocated sysmem block in the
* mailbox register for stress test.
*/
if (g->gsp->gsp_test.load_stress_test)
gsp_write_test_sysmem_addr(g->gsp);
if (nvgpu_gsp_get_stress_test_load(g)) {
nvgpu_gsp_write_test_sysmem_addr(g);
}
#endif
g->ops.falcon.bootstrap(flcn, 0x0);
@@ -240,31 +183,22 @@ exit:
return -1;
}
static int gsp_wait_for_mailbox_update(struct nvgpu_gsp *gsp,
u32 mailbox_index, signed int timeoutms)
int nvgpu_gsp_wait_for_mailbox_update(struct nvgpu_gsp *gsp,
u32 mailbox_index, u32 exp_value, signed int timeoutms)
{
u32 mail_box_data = 0;
u32 pass_val = 0;
struct nvgpu_falcon *flcn = gsp->gsp_flcn;
nvgpu_log_fn(flcn->g, " ");
#ifdef CONFIG_NVGPU_GSP_STRESS_TEST
if (gsp->gsp_test.load_stress_test) {
pass_val = GSP_STRESS_TEST_MAILBOX_PASS;
}
#endif
do {
mail_box_data = flcn->g->ops.falcon.mailbox_read(
flcn, mailbox_index);
if (mail_box_data != 0U) {
if ((pass_val == 0U) || (mail_box_data == pass_val)) {
nvgpu_info(flcn->g,
"gsp mailbox-0 updated successful with 0x%x",
mail_box_data);
break;
}
if (mail_box_data == exp_value) {
nvgpu_info(flcn->g,
"gsp mailbox-0 updated successful with 0x%x",
mail_box_data);
break;
}
if (timeoutms <= 0) {
@@ -280,7 +214,7 @@ static int gsp_wait_for_mailbox_update(struct nvgpu_gsp *gsp,
return 0;
}
int gsp_bootstrap_ns(struct gk20a *g, struct nvgpu_gsp *gsp)
int nvgpu_gsp_bootstrap_ns(struct gk20a *g, struct nvgpu_gsp *gsp)
{
int err = 0;
struct gsp_fw *gsp_ucode = &gsp->gsp_ucode;
@@ -288,46 +222,34 @@ int gsp_bootstrap_ns(struct gk20a *g, struct nvgpu_gsp *gsp)
nvgpu_log_fn(g, " ");
err = gsp_read_firmware(g, gsp_ucode);
err = gsp_read_firmware(g, gsp, gsp_ucode);
if (err != 0) {
nvgpu_err(g, "gsp firmware reading failed");
goto exit;
}
/* core reset */
err = nvgpu_falcon_reset(gsp->gsp_flcn);
err = nvgpu_falcon_reset(flcn);
if (err != 0) {
nvgpu_err(g, "gsp core reset failed err=%d", err);
goto exit;
}
/* Enable required interrupts support and isr */
nvgpu_gsp_isr_support(g, true);
nvgpu_gsp_isr_support(g, gsp, true);
/* setup falcon apertures */
if (flcn->flcn_engine_dep_ops.setup_bootstrap_config != NULL) {
flcn->flcn_engine_dep_ops.setup_bootstrap_config(flcn->g);
}
err = gsp_ucode_load_and_bootstrap(g, gsp->gsp_flcn, gsp_ucode);
err = gsp_ucode_load_and_bootstrap(g, flcn, gsp_ucode);
if (err != 0) {
nvgpu_err(g, "gsp load and bootstrap failed");
goto exit;
}
err = gsp_check_for_brom_completion(gsp->gsp_flcn, GSP_WAIT_TIME_MS);
err = gsp_check_for_brom_completion(flcn, GSP_WAIT_TIME_MS);
if (err != 0) {
nvgpu_err(g, "gsp BROM failed");
goto exit;
}
/* wait for mailbox-0 update with non-zero value */
err = gsp_wait_for_mailbox_update(gsp, 0x0, GSP_WAIT_TIME_MS);
if (err != 0) {
nvgpu_err(g, "gsp ucode failed to update mailbox-0");
}
exit:
gsp_release_firmware(g, g->gsp);
gsp_release_firmware(g, gsp);
return err;
}