From 930c218810db6c989e07aa961a8ce9bec8d83bdb Mon Sep 17 00:00:00 2001 From: mkumbar Date: Fri, 18 Feb 2022 18:17:36 +0530 Subject: [PATCH] gpu: nvgpu: ga10b: fix priv error for nvriscv bcr reg read Read nvriscv bcr regsiter only if priv lockdown is released. Reading bcr during priv lockdown triggers priv violation error. Bug 3541062 Change-Id: Ib63f1ad634a945e0f9c573b4703217dbf887a776 Signed-off-by: mkumbar Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2672196 Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/hal/falcon/falcon_ga10b_fusa.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/falcon/falcon_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/falcon/falcon_ga10b_fusa.c index 41f83872f..87c029780 100644 --- a/drivers/gpu/nvgpu/hal/falcon/falcon_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/falcon/falcon_ga10b_fusa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -79,10 +79,7 @@ void ga10b_falcon_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector) void ga10b_falcon_dump_brom_stats(struct nvgpu_falcon *flcn) { - u32 reg; - - reg = nvgpu_riscv_readl(flcn, priscv_priscv_bcr_ctrl_r()); - nvgpu_falcon_dbg(flcn->g, "Bootrom Configuration: 0x%08x", reg); + u32 reg = 0; reg = nvgpu_falcon_readl(flcn, falcon_falcon_hwcfg2_r()); nvgpu_falcon_dbg(flcn->g, "HWCFG2: 0x%08x", reg); @@ -92,6 +89,9 @@ void ga10b_falcon_dump_brom_stats(struct nvgpu_falcon *flcn) nvgpu_falcon_dbg(flcn->g, "PRIV LOCKDOWN enabled"); } else { nvgpu_falcon_dbg(flcn->g, "PRIV LOCKDOWN disabled"); + + reg = nvgpu_riscv_readl(flcn, priscv_priscv_bcr_ctrl_r()); + nvgpu_falcon_dbg(flcn->g, "Bootrom Configuration: 0x%08x", reg); } reg = nvgpu_riscv_readl(flcn, priscv_priscv_br_retcode_r());