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gpu: nvgpu: fix misra violations in SDL

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This patch addresses misra violations due to SDL error reporting
callbacks. In particular, it addresses the following misra violation:

- misra_c_2012_directive_4_7_violation: Calling function
  "nvgpu_report_*_err()" which returns error information without testing
  the error information.

JIRA NVGPU-4025

Change-Id: Ia10b6b3fd9c127a8c5189c3b6ba316f243cedf04
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196895
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Rajesh Devaraj
2019-09-13 14:19:42 +05:30
committed by Alex Waterman
parent 84bb355525
commit 935c5f6578
26 changed files with 152 additions and 230 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/nvgpu/common/fifo/preempt.c
View File

@@ -57,7 +57,6 @@ void nvgpu_preempt_poll_tsg_on_pbdma(struct gk20a *g,
unsigned long runlist_served_pbdmas;
unsigned long pbdma_id_bit;
u32 tsgid, pbdma_id;
int err;
if (g->ops.fifo.preempt_poll_pbdma == NULL) {
return;
@@ -78,15 +77,10 @@ void nvgpu_preempt_poll_tsg_on_pbdma(struct gk20a *g,
* GPU. Any sort of hang indicates the entire GPU’s
* memory system would be blocked.
*/
if (g->ops.fifo.preempt_poll_pbdma(g, tsgid,
pbdma_id) != 0) {
err = nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST,
if (g->ops.fifo.preempt_poll_pbdma(g, tsgid, pbdma_id) != 0) {
nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST,
pbdma_id,
GPU_HOST_PBDMA_PREEMPT_ERROR, 0);
if (err == 0) {
nvgpu_info(g, "failed to report PBDMA preempt failed error");
}
nvgpu_err(g, "PBDMA preempt failed");
}
}

6
drivers/gpu/nvgpu/common/gr/gr_intr.c
View File

@@ -52,7 +52,7 @@ static void gr_intr_report_ctxsw_error(struct gk20a *g, u32 err_type, u32 chid,
err_info.mailbox_value = mailbox_value;
err_info.chid = chid;
(void) nvgpu_report_ctxsw_err(g, NVGPU_ERR_MODULE_FECS,
nvgpu_report_ctxsw_err(g, NVGPU_ERR_MODULE_FECS,
err_type, (void *)&err_info);
}
@@ -226,7 +226,7 @@ static void gr_intr_report_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
err_info.tpc = tpc;
err_info.sm = sm;
info.sm_mcerr_info = &err_info;
(void) nvgpu_report_gr_err(g, NVGPU_ERR_MODULE_SM, inst,
nvgpu_report_gr_err(g, NVGPU_ERR_MODULE_SM, inst,
GPU_SM_MACHINE_CHECK_ERROR, &info, 0U);
}
@@ -337,7 +337,7 @@ void nvgpu_gr_intr_report_exception(struct gk20a *g, u32 inst,
err_info.tsgid = tsgid;
err_info.status = status;
info.exception_info = &err_info;
(void) nvgpu_report_gr_err(g, NVGPU_ERR_MODULE_PGRAPH,
nvgpu_report_gr_err(g, NVGPU_ERR_MODULE_PGRAPH,
inst, err_type, &info, sub_err_type);
}

2
drivers/gpu/nvgpu/common/pmu/pmu.c
View File

@@ -394,7 +394,7 @@ void nvgpu_pmu_remove_support(struct gk20a *g, struct nvgpu_pmu *pmu)
void nvgpu_pmu_report_bar0_pri_err_status(struct gk20a *g, u32 bar0_status,
u32 error_type)
{
(void) nvgpu_report_pmu_err(g, NVGPU_ERR_MODULE_PMU,
nvgpu_report_pmu_err(g, NVGPU_ERR_MODULE_PMU,
GPU_PMU_BAR0_ERROR_TIMEOUT, error_type, bar0_status);
}

2
drivers/gpu/nvgpu/hal/bus/bus_gk20a_fusa.c
View File

@@ -79,7 +79,7 @@ void gk20a_bus_isr(struct gk20a *g)
*/
err_type = GPU_HOST_PBUS_TIMEOUT_ERROR;
}
(void) nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST,
nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST,
0, err_type, val);
gk20a_writel(g, bus_intr_0_r(), val);
}

6
drivers/gpu/nvgpu/hal/ce/ce_gp10b_fusa.c
View File

@@ -39,14 +39,14 @@ void gp10b_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
/* clear blocking interrupts: they exibit broken behavior */
if ((ce_intr & ce_intr_status_blockpipe_pending_f()) != 0U) {
(void) nvgpu_report_ce_err(g, NVGPU_ERR_MODULE_CE, inst_id,
nvgpu_report_ce_err(g, NVGPU_ERR_MODULE_CE, inst_id,
GPU_CE_BLOCK_PIPE, ce_intr);
nvgpu_log(g, gpu_dbg_intr, "ce blocking pipe interrupt");
clear_intr |= ce_intr_status_blockpipe_pending_f();
}
if ((ce_intr & ce_intr_status_launcherr_pending_f()) != 0U) {
(void) nvgpu_report_ce_err(g, NVGPU_ERR_MODULE_CE, inst_id,
nvgpu_report_ce_err(g, NVGPU_ERR_MODULE_CE, inst_id,
GPU_CE_LAUNCH_ERROR, ce_intr);
nvgpu_log(g, gpu_dbg_intr, "ce launch error interrupt");
clear_intr |= ce_intr_status_launcherr_pending_f();
@@ -65,7 +65,7 @@ u32 gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
ce_intr, inst_id);
if ((ce_intr & ce_intr_status_nonblockpipe_pending_f()) != 0U) {
(void) nvgpu_report_ce_err(g, NVGPU_ERR_MODULE_CE, inst_id,
nvgpu_report_ce_err(g, NVGPU_ERR_MODULE_CE, inst_id,
GPU_CE_NONBLOCK_PIPE, ce_intr);
nvgpu_writel(g, ce_intr_status_r(inst_id),
ce_intr_status_nonblockpipe_pending_f());

4
drivers/gpu/nvgpu/hal/ce/ce_gv11b_fusa.c
View File

@@ -61,7 +61,7 @@ void gv11b_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
* reset to get back to a working state.
*/
if ((ce_intr & ce_intr_status_invalid_config_pending_f()) != 0U) {
(void) nvgpu_report_ce_err(g, NVGPU_ERR_MODULE_CE, inst_id,
nvgpu_report_ce_err(g, NVGPU_ERR_MODULE_CE, inst_id,
GPU_CE_INVALID_CONFIG, ce_intr);
nvgpu_log(g, gpu_dbg_intr,
"ce: inst %d: invalid config", inst_id);
@@ -75,7 +75,7 @@ void gv11b_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
* reset before operations can start again, if not the entire GPU.
*/
if ((ce_intr & ce_intr_status_mthd_buffer_fault_pending_f()) != 0U) {
(void) nvgpu_report_ce_err(g, NVGPU_ERR_MODULE_CE, inst_id,
nvgpu_report_ce_err(g, NVGPU_ERR_MODULE_CE, inst_id,
GPU_CE_METHOD_BUFFER_FAULT, ce_intr);
nvgpu_log(g, gpu_dbg_intr,
"ce: inst %d: mthd buffer fault", inst_id);

6
drivers/gpu/nvgpu/hal/fb/fb_mmu_fault_gv11b_fusa.c
View File

@@ -581,7 +581,7 @@ void gv11b_fb_handle_mmu_fault(struct gk20a *g, u32 niso_intr)
if ((niso_intr &
fb_niso_intr_mmu_other_fault_notify_m()) != 0U) {
(void) nvgpu_report_mmu_err(g, NVGPU_ERR_MODULE_HUBMMU,
nvgpu_report_mmu_err(g, NVGPU_ERR_MODULE_HUBMMU,
GPU_HUBMMU_PAGE_FAULT_ERROR,
NULL,
fault_status,
@@ -610,7 +610,7 @@ void gv11b_fb_handle_mmu_fault(struct gk20a *g, u32 niso_intr)
if ((niso_intr &
fb_niso_intr_mmu_nonreplayable_fault_overflow_m()) != 0U) {
(void) nvgpu_report_mmu_err(g, NVGPU_ERR_MODULE_HUBMMU,
nvgpu_report_mmu_err(g, NVGPU_ERR_MODULE_HUBMMU,
GPU_HUBMMU_PAGE_FAULT_ERROR,
NULL,
fault_status,
@@ -634,7 +634,7 @@ void gv11b_fb_handle_mmu_fault(struct gk20a *g, u32 niso_intr)
if ((niso_intr &
fb_niso_intr_mmu_replayable_fault_overflow_m()) != 0U) {
(void) nvgpu_report_mmu_err(g, NVGPU_ERR_MODULE_HUBMMU,
nvgpu_report_mmu_err(g, NVGPU_ERR_MODULE_HUBMMU,
GPU_HUBMMU_PAGE_FAULT_ERROR,
NULL,
fault_status,

2
drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b.h
View File

@@ -36,7 +36,7 @@ void gv11b_fb_intr_handle_ecc(struct gk20a *g);
#ifdef CONFIG_NVGPU_INJECT_HWERR
struct nvgpu_hw_err_inject_info_desc *
gv11b_fb_intr_get_hubmmu_err_desc(struct gk20a *g);
int gv11b_fb_intr_inject_hubmmu_ecc_error(struct gk20a *g,
void gv11b_fb_intr_inject_hubmmu_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info);
#endif

20
drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b_fusa.c
View File

@@ -32,7 +32,7 @@
#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
#ifdef CONFIG_NVGPU_INJECT_HWERR
int gv11b_fb_intr_inject_hubmmu_ecc_error(struct gk20a *g,
void gv11b_fb_intr_inject_hubmmu_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err,
u32 error_info)
{
@@ -40,8 +40,6 @@ int gv11b_fb_intr_inject_hubmmu_ecc_error(struct gk20a *g,
nvgpu_info(g, "Injecting HUBMMU fault %s", err->name);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
return 0;
}
static inline u32 l2tlb_ecc_control_r(void)
@@ -158,7 +156,7 @@ static void gv11b_fb_intr_handle_ecc_l2tlb(struct gk20a *g, u32 ecc_status)
if ((ecc_status &
fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m())
!= 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_HUBMMU,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_HUBMMU,
0, GPU_HUBMMU_L2TLB_SA_DATA_ECC_CORRECTED,
ecc_addr,
g->ecc.fb.mmu_l2tlb_ecc_corrected_err_count[0].counter);
@@ -167,7 +165,7 @@ static void gv11b_fb_intr_handle_ecc_l2tlb(struct gk20a *g, u32 ecc_status)
if ((ecc_status &
fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m())
!= 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_HUBMMU,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_HUBMMU,
0, GPU_HUBMMU_L2TLB_SA_DATA_ECC_UNCORRECTED,
ecc_addr,
g->ecc.fb.mmu_l2tlb_ecc_uncorrected_err_count[0].counter);
@@ -239,7 +237,7 @@ static void gv11b_fb_intr_handle_ecc_hubtlb(struct gk20a *g, u32 ecc_status)
if ((ecc_status &
fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_HUBMMU,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_HUBMMU,
0, GPU_HUBMMU_TLB_SA_DATA_ECC_CORRECTED,
ecc_addr,
g->ecc.fb.mmu_hubtlb_ecc_corrected_err_count[0].counter);
@@ -247,7 +245,7 @@ static void gv11b_fb_intr_handle_ecc_hubtlb(struct gk20a *g, u32 ecc_status)
}
if ((ecc_status &
fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_HUBMMU,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_HUBMMU,
0, GPU_HUBMMU_TLB_SA_DATA_ECC_UNCORRECTED,
ecc_addr,
g->ecc.fb.mmu_hubtlb_ecc_uncorrected_err_count[0].counter);
@@ -320,7 +318,7 @@ static void gv11b_fb_intr_handle_ecc_fillunit(struct gk20a *g, u32 ecc_status)
if ((ecc_status &
fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_HUBMMU,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_HUBMMU,
0, GPU_HUBMMU_PTE_DATA_ECC_CORRECTED,
ecc_addr,
g->ecc.fb.mmu_fillunit_ecc_corrected_err_count[0].counter);
@@ -329,7 +327,7 @@ static void gv11b_fb_intr_handle_ecc_fillunit(struct gk20a *g, u32 ecc_status)
if ((ecc_status &
fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m())
!= 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_HUBMMU,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_HUBMMU,
0, GPU_HUBMMU_PTE_DATA_ECC_UNCORRECTED,
ecc_addr,
g->ecc.fb.mmu_fillunit_ecc_uncorrected_err_count[0].counter);
@@ -337,7 +335,7 @@ static void gv11b_fb_intr_handle_ecc_fillunit(struct gk20a *g, u32 ecc_status)
}
if ((ecc_status &
fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_HUBMMU,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_HUBMMU,
0, GPU_HUBMMU_PDE0_DATA_ECC_CORRECTED,
ecc_addr,
g->ecc.fb.mmu_fillunit_ecc_corrected_err_count[0].counter);
@@ -346,7 +344,7 @@ static void gv11b_fb_intr_handle_ecc_fillunit(struct gk20a *g, u32 ecc_status)
if ((ecc_status &
fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m())
!= 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_HUBMMU,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_HUBMMU,
0, GPU_HUBMMU_PDE0_DATA_ECC_UNCORRECTED,
ecc_addr,
g->ecc.fb.mmu_fillunit_ecc_uncorrected_err_count[0].counter);

7
drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_gv11b_fusa.c
View File

@@ -188,7 +188,6 @@ bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g)
u32 info_status;
const char *info_status_str;
struct nvgpu_tsg *tsg = NULL;
int err;
/* get ctxsw timedout engines */
ctxsw_timeout_engines = nvgpu_readl(g, fifo_intr_ctxsw_timeout_r());
@@ -218,14 +217,10 @@ bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g)
continue;
}
err = nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST,
nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST,
0, GPU_HOST_PFIFO_CTXSW_TIMEOUT_ERROR,
tsgid);
if (err != 0) {
nvgpu_info(g, "failed to report ctxsw_timeout_errors");
}
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
recover = g->ops.tsg.check_ctxsw_timeout(tsg,
&debug_dump, &ms);

2
drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a.c
View File

@@ -141,7 +141,7 @@ static u32 gk20a_fifo_intr_handle_errors(struct gk20a *g, u32 fifo_intr)
}
if ((fifo_intr & fifo_intr_0_fb_flush_timeout_pending_f()) != 0U) {
(void) nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST,
nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST,
0, GPU_HOST_PFIFO_FB_FLUSH_TIMEOUT_ERROR, 0);
nvgpu_err(g, "fifo fb flush timeout error");
handled |= fifo_intr_0_fb_flush_timeout_pending_f();

6
drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a_fusa.c
View File

@@ -69,14 +69,10 @@ u32 gk20a_fifo_intr_1_isr(struct gk20a *g)
void gk20a_fifo_intr_handle_chsw_error(struct gk20a *g)
{
u32 intr;
int err;
intr = nvgpu_readl(g, fifo_intr_chsw_error_r());
err = nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST,
nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST,
0, GPU_HOST_PFIFO_CHSW_ERROR, intr);
if (err != 0) {
nvgpu_info(g, "failed to report chsw_error");
}
nvgpu_err(g, "chsw: %08x", intr);
g->ops.gr.falcon.dump_stats(g);
nvgpu_writel(g, fifo_intr_chsw_error_r(), intr);

29
drivers/gpu/nvgpu/hal/fifo/fifo_intr_gv11b_fusa.c
View File

@@ -118,7 +118,6 @@ void gv11b_fifo_intr_0_enable(struct gk20a *g, bool enable)
bool gv11b_fifo_handle_sched_error(struct gk20a *g)
{
u32 sched_error;
int err;
sched_error = nvgpu_readl(g, fifo_intr_sched_error_r());
@@ -129,13 +128,9 @@ bool gv11b_fifo_handle_sched_error(struct gk20a *g)
nvgpu_err(g, "fifo sched error code not supported");
}
err = nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST,
nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST,
0, GPU_HOST_PFIFO_SCHED_ERROR, sched_error);
if (err != 0) {
nvgpu_info(g, "failed to report fifo sched error");
}
if (sched_error == SCHED_ERROR_CODE_BAD_TSG) {
/* id is unknown, preempt all runlists and do recovery */
nvgpu_rc_sched_error_bad_tsg(g);
@@ -147,19 +142,13 @@ bool gv11b_fifo_handle_sched_error(struct gk20a *g)
static u32 gv11b_fifo_intr_handle_errors(struct gk20a *g, u32 fifo_intr)
{
u32 handled = 0U;
int err;
nvgpu_log_fn(g, "fifo_intr=0x%08x", fifo_intr);
if ((fifo_intr & fifo_intr_0_bind_error_pending_f()) != 0U) {
u32 bind_error = nvgpu_readl(g, fifo_intr_bind_error_r());
err = nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST, 0,
nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST, 0,
GPU_HOST_PFIFO_BIND_ERROR, bind_error);
if (err != 0) {
nvgpu_info(g, "failed to report fifo bind error");
}
nvgpu_err(g, "fifo bind error: 0x%08x", bind_error);
handled |= fifo_intr_0_bind_error_pending_f();
}
@@ -170,13 +159,8 @@ static u32 gv11b_fifo_intr_handle_errors(struct gk20a *g, u32 fifo_intr)
}
if ((fifo_intr & fifo_intr_0_memop_timeout_pending_f()) != 0U) {
err = nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST, 0,
nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST, 0,
GPU_HOST_PFIFO_MEMOP_TIMEOUT_ERROR, 0);
if (err != 0) {
nvgpu_info(g, "failed to report fifo memop error");
}
nvgpu_err(g, "fifo memop timeout error");
handled |= fifo_intr_0_memop_timeout_pending_f();
}
@@ -184,13 +168,8 @@ static u32 gv11b_fifo_intr_handle_errors(struct gk20a *g, u32 fifo_intr)
if ((fifo_intr & fifo_intr_0_lb_error_pending_f()) != 0U) {
u32 lb_error = nvgpu_readl(g, fifo_intr_lb_error_r());
err = nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST, 0,
nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST, 0,
GPU_HOST_PFIFO_LB_ERROR, lb_error);
if (err != 0) {
nvgpu_info(g, "failed to report fifo lb error");
}
nvgpu_err(g, "fifo lb error");
handled |= fifo_intr_0_lb_error_pending_f();
}

14
drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b_fusa.c
View File

@@ -36,7 +36,6 @@ static void report_pbdma_error(struct gk20a *g, u32 pbdma_id,
u32 pbdma_intr_0)
{
u32 err_type = GPU_HOST_INVALID_ERROR;
int err;
/*
* Multiple errors have been grouped as part of a single
@@ -87,12 +86,8 @@ static void report_pbdma_error(struct gk20a *g, u32 pbdma_id,
err_type = GPU_HOST_PBDMA_SIGNATURE_ERROR;
}
if (err_type != GPU_HOST_INVALID_ERROR) {
err = nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST,
nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST,
pbdma_id, err_type, pbdma_intr_0);
if (err != 0) {
nvgpu_info(g, "failed to report GPU host invalid error");
}
}
return;
}
@@ -178,7 +173,6 @@ bool gv11b_pbdma_handle_intr_1(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_1,
u32 *error_notifier)
{
bool recover = false;
int err;
u32 pbdma_intr_1_current = gk20a_readl(g, pbdma_intr_1_r(pbdma_id));
@@ -194,13 +188,9 @@ bool gv11b_pbdma_handle_intr_1(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_1,
recover = true;
err = nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST, pbdma_id,
nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST, pbdma_id,
GPU_HOST_PBDMA_HCE_ERROR, pbdma_intr_1);
if (err != 0) {
nvgpu_info(g, "failed to report PBDMA HCE error");
}
if ((pbdma_intr_1 & pbdma_intr_1_ctxnotvalid_pending_f()) != 0U) {
nvgpu_log(g, gpu_dbg_intr, "ctxnotvalid intr on pbdma id %d",
pbdma_id);

10
drivers/gpu/nvgpu/hal/gr/ecc/ecc_gv11b.h
View File

@@ -34,23 +34,23 @@ void gv11b_ecc_detect_enabled_units(struct gk20a *g);
int gv11b_ecc_init(struct gk20a *g);
#ifdef CONFIG_NVGPU_INJECT_HWERR
int gv11b_gr_intr_inject_fecs_ecc_error(struct gk20a *g,
void gv11b_gr_intr_inject_fecs_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info);
struct nvgpu_hw_err_inject_info_desc *
gv11b_gr_intr_get_fecs_err_desc(struct gk20a *g);
int gv11b_gr_intr_inject_gpccs_ecc_error(struct gk20a *g,
void gv11b_gr_intr_inject_gpccs_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info);
struct nvgpu_hw_err_inject_info_desc *
gv11b_gr_intr_get_gpccs_err_desc(struct gk20a *g);
int gv11b_gr_intr_inject_sm_ecc_error(struct gk20a *g,
void gv11b_gr_intr_inject_sm_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info);
struct nvgpu_hw_err_inject_info_desc *
gv11b_gr_intr_get_sm_err_desc(struct gk20a *g);
int gv11b_gr_intr_inject_mmu_ecc_error(struct gk20a *g,
void gv11b_gr_intr_inject_mmu_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info);
struct nvgpu_hw_err_inject_info_desc *
gv11b_gr_intr_get_mmu_err_desc(struct gk20a *g);
int gv11b_gr_intr_inject_gcc_ecc_error(struct gk20a *g,
void gv11b_gr_intr_inject_gcc_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info);
struct nvgpu_hw_err_inject_info_desc *
gv11b_gr_intr_get_gcc_err_desc(struct gk20a *g);

20
drivers/gpu/nvgpu/hal/gr/ecc/ecc_gv11b_fusa.c
View File

@@ -29,16 +29,14 @@
#include "ecc_gv11b.h"
#ifdef CONFIG_NVGPU_INJECT_HWERR
int gv11b_gr_intr_inject_fecs_ecc_error(struct gk20a *g,
void gv11b_gr_intr_inject_fecs_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
nvgpu_info(g, "Injecting FECS fault %s", err->name);
nvgpu_writel(g, err->get_reg_addr(), err->get_reg_val(1U));
return 0;
}
int gv11b_gr_intr_inject_gpccs_ecc_error(struct gk20a *g,
void gv11b_gr_intr_inject_gpccs_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
unsigned int gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
@@ -48,11 +46,9 @@ int gv11b_gr_intr_inject_gpccs_ecc_error(struct gk20a *g,
nvgpu_info(g, "Injecting GPCCS fault %s for gpc: %d", err->name, gpc);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
return 0;
}
int gv11b_gr_intr_inject_sm_ecc_error(struct gk20a *g,
void gv11b_gr_intr_inject_sm_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err,
u32 error_info)
{
@@ -69,11 +65,9 @@ int gv11b_gr_intr_inject_sm_ecc_error(struct gk20a *g,
nvgpu_info(g, "Injecting SM fault %s for gpc: %d, tpc: %d",
err->name, gpc, tpc);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
return 0;
}
int gv11b_gr_intr_inject_mmu_ecc_error(struct gk20a *g,
void gv11b_gr_intr_inject_mmu_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
unsigned int gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
@@ -83,11 +77,9 @@ int gv11b_gr_intr_inject_mmu_ecc_error(struct gk20a *g,
nvgpu_info(g, "Injecting MMU fault %s for gpc: %d", err->name, gpc);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
return 0;
}
int gv11b_gr_intr_inject_gcc_ecc_error(struct gk20a *g,
void gv11b_gr_intr_inject_gcc_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
unsigned int gpc_stride = nvgpu_get_litter_value(g,
@@ -98,8 +90,6 @@ int gv11b_gr_intr_inject_gcc_ecc_error(struct gk20a *g,
nvgpu_info(g, "Injecting GCC fault %s for gpc: %d", err->name, gpc);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
return 0;
}
static inline u32 fecs_falcon_ecc_control_r(void)

68
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c
View File

@@ -54,28 +54,28 @@ static void gv11b_gr_intr_handle_fecs_ecc_error(struct gk20a *g)
fecs_ecc_status.uncorrected_delta);
if (fecs_ecc_status.imem_corrected_err) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_FECS, 0,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_FECS, 0,
GPU_FECS_FALCON_IMEM_ECC_CORRECTED,
fecs_ecc_status.ecc_addr,
g->ecc.gr.fecs_ecc_corrected_err_count[0].counter);
nvgpu_log(g, gpu_dbg_intr, "imem ecc error corrected");
}
if (fecs_ecc_status.imem_uncorrected_err) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_FECS, 0,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_FECS, 0,
GPU_FECS_FALCON_IMEM_ECC_UNCORRECTED,
fecs_ecc_status.ecc_addr,
g->ecc.gr.fecs_ecc_uncorrected_err_count[0].counter);
nvgpu_log(g, gpu_dbg_intr, "imem ecc error uncorrected");
}
if (fecs_ecc_status.dmem_corrected_err) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_FECS, 0,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_FECS, 0,
GPU_FECS_FALCON_DMEM_ECC_CORRECTED,
fecs_ecc_status.ecc_addr,
g->ecc.gr.fecs_ecc_corrected_err_count[0].counter);
nvgpu_log(g, gpu_dbg_intr, "dmem ecc error corrected");
}
if (fecs_ecc_status.dmem_uncorrected_err) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_FECS, 0,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_FECS, 0,
GPU_FECS_FALCON_DMEM_ECC_UNCORRECTED,
fecs_ecc_status.ecc_addr,
g->ecc.gr.fecs_ecc_uncorrected_err_count[0].counter);
@@ -330,7 +330,7 @@ void gv11b_gr_intr_handle_gcc_exception(struct gk20a *g, u32 gpc,
*corrected_err = nvgpu_safe_add_u32(
*corrected_err,
gcc_l15_corrected_err_count_delta);
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_GCC, gpc,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_GCC, gpc,
GPU_GCC_L15_ECC_CORRECTED,
0, *corrected_err);
nvgpu_writel(g, nvgpu_safe_add_u32(
@@ -355,7 +355,7 @@ void gv11b_gr_intr_handle_gcc_exception(struct gk20a *g, u32 gpc,
}
*uncorrected_err = nvgpu_safe_add_u32(*uncorrected_err,
gcc_l15_uncorrected_err_count_delta);
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_GCC, gpc,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_GCC, gpc,
GPU_GCC_L15_ECC_UNCORRECTED,
0, *uncorrected_err);
nvgpu_writel(g, nvgpu_safe_add_u32(
@@ -375,7 +375,7 @@ static void gv11b_gr_intr_report_gpcmmu_ecc_err(struct gk20a *g,
if ((ecc_status &
gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_m()) !=
0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_MMU, gpc,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_MMU, gpc,
GPU_MMU_L1TLB_SA_DATA_ECC_CORRECTED,
0, correct_err);
nvgpu_log(g, gpu_dbg_intr, "corrected ecc sa data error");
@@ -383,7 +383,7 @@ static void gv11b_gr_intr_report_gpcmmu_ecc_err(struct gk20a *g,
if ((ecc_status &
gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_m()) !=
0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_MMU, gpc,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_MMU, gpc,
GPU_MMU_L1TLB_SA_DATA_ECC_UNCORRECTED,
0, uncorrect_err);
nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc sa data error");
@@ -391,7 +391,7 @@ static void gv11b_gr_intr_report_gpcmmu_ecc_err(struct gk20a *g,
if ((ecc_status &
gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_m()) !=
0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_MMU, gpc,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_MMU, gpc,
GPU_MMU_L1TLB_FA_DATA_ECC_CORRECTED,
0, correct_err);
nvgpu_log(g, gpu_dbg_intr, "corrected ecc fa data error");
@@ -399,7 +399,7 @@ static void gv11b_gr_intr_report_gpcmmu_ecc_err(struct gk20a *g,
if ((ecc_status &
gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_m()) !=
0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_MMU, gpc,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_MMU, gpc,
GPU_MMU_L1TLB_FA_DATA_ECC_UNCORRECTED,
0, uncorrect_err);
nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc fa data error");
@@ -499,28 +499,28 @@ static void gv11b_gr_intr_report_gpccs_ecc_err(struct gk20a *g,
{
if ((ecc_status &
gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_GPCCS,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_GPCCS,
gpc, GPU_GPCCS_FALCON_IMEM_ECC_CORRECTED,
ecc_addr, correct_err);
nvgpu_log(g, gpu_dbg_intr, "imem ecc error corrected");
}
if ((ecc_status &
gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_GPCCS,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_GPCCS,
gpc, GPU_GPCCS_FALCON_IMEM_ECC_UNCORRECTED,
ecc_addr, uncorrect_err);
nvgpu_log(g, gpu_dbg_intr, "imem ecc error uncorrected");
}
if ((ecc_status &
gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_GPCCS,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_GPCCS,
gpc, GPU_GPCCS_FALCON_DMEM_ECC_CORRECTED,
ecc_addr, correct_err);
nvgpu_log(g, gpu_dbg_intr, "dmem ecc error corrected");
}
if ((ecc_status &
gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_GPCCS,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_GPCCS,
gpc, GPU_GPCCS_FALCON_DMEM_ECC_UNCORRECTED,
ecc_addr, uncorrect_err);
nvgpu_log(g, gpu_dbg_intr, "dmem ecc error uncorrected");
@@ -911,21 +911,21 @@ static void gv11b_gr_intr_report_l1_tag_uncorrected_err(struct gk20a *g,
if ((l1_tag_ecc_status &
(gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_0_m() |
gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_1_m())) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_L1_TAG_ECC_UNCORRECTED, 0,
g->ecc.gr.sm_l1_tag_ecc_uncorrected_err_count[gpc][tpc].counter);
}
if ((l1_tag_ecc_status &
gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_miss_fifo_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_L1_TAG_MISS_FIFO_ECC_UNCORRECTED, 0,
g->ecc.gr.sm_l1_tag_ecc_uncorrected_err_count[gpc][tpc].counter);
}
if ((l1_tag_ecc_status &
gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_pixrpf_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_L1_TAG_S2R_PIXPRF_ECC_UNCORRECTED, 0,
g->ecc.gr.sm_l1_tag_ecc_uncorrected_err_count[gpc][tpc].counter);
@@ -946,21 +946,21 @@ static void gv11b_gr_intr_report_l1_tag_corrected_err(struct gk20a *g,
if ((l1_tag_ecc_status &
(gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_0_m() |
gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_1_m())) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_L1_TAG_ECC_CORRECTED, 0,
g->ecc.gr.sm_l1_tag_ecc_corrected_err_count[gpc][tpc].counter);
}
if ((l1_tag_ecc_status &
gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_miss_fifo_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_L1_TAG_MISS_FIFO_ECC_CORRECTED, 0,
g->ecc.gr.sm_l1_tag_ecc_corrected_err_count[gpc][tpc].counter);
}
if ((l1_tag_ecc_status &
gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_pixrpf_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_L1_TAG_S2R_PIXPRF_ECC_CORRECTED, 0,
g->ecc.gr.sm_l1_tag_ecc_corrected_err_count[gpc][tpc].counter);
@@ -1146,7 +1146,7 @@ static void gv11b_gr_intr_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc
nvgpu_safe_add_u32(
g->ecc.gr.sm_lrf_ecc_single_err_count[gpc][tpc].counter,
lrf_corrected_err_count_delta);
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_LRF_ECC_CORRECTED, 0,
g->ecc.gr.sm_lrf_ecc_single_err_count[gpc][tpc].counter);
@@ -1170,7 +1170,7 @@ static void gv11b_gr_intr_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc
nvgpu_safe_add_u32(
g->ecc.gr.sm_lrf_ecc_double_err_count[gpc][tpc].counter,
lrf_uncorrected_err_count_delta);
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_LRF_ECC_UNCORRECTED, 0,
g->ecc.gr.sm_lrf_ecc_double_err_count[gpc][tpc].counter);
@@ -1256,7 +1256,7 @@ static void gv11b_gr_intr_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc
nvgpu_safe_add_u32(
g->ecc.gr.sm_cbu_ecc_corrected_err_count[gpc][tpc].counter,
cbu_corrected_err_count_delta);
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_CBU_ECC_CORRECTED,
0, g->ecc.gr.sm_cbu_ecc_corrected_err_count[gpc][tpc].counter);
@@ -1279,7 +1279,7 @@ static void gv11b_gr_intr_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc
nvgpu_safe_add_u32(
g->ecc.gr.sm_cbu_ecc_uncorrected_err_count[gpc][tpc].counter,
cbu_uncorrected_err_count_delta);
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_CBU_ECC_UNCORRECTED,
0, g->ecc.gr.sm_cbu_ecc_uncorrected_err_count[gpc][tpc].counter);
@@ -1362,7 +1362,7 @@ static void gv11b_gr_intr_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32
nvgpu_safe_add_u32(
g->ecc.gr.sm_l1_data_ecc_corrected_err_count[gpc][tpc].counter,
l1_data_corrected_err_count_delta);
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_L1_DATA_ECC_CORRECTED,
0, g->ecc.gr.sm_l1_data_ecc_corrected_err_count[gpc][tpc].counter);
@@ -1385,7 +1385,7 @@ static void gv11b_gr_intr_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32
nvgpu_safe_add_u32(
g->ecc.gr.sm_l1_data_ecc_uncorrected_err_count[gpc][tpc].counter,
l1_data_uncorrected_err_count_delta);
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_L1_DATA_ECC_UNCORRECTED,
0, g->ecc.gr.sm_l1_data_ecc_uncorrected_err_count[gpc][tpc].counter);
@@ -1411,28 +1411,28 @@ static void gv11b_gr_intr_report_icache_uncorrected_err(struct gk20a *g,
}
if ((icache_ecc_status &
gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_data_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_ICACHE_L0_DATA_ECC_UNCORRECTED,
0, g->ecc.gr.sm_icache_ecc_uncorrected_err_count[gpc][tpc].counter);
}
if ((icache_ecc_status &
gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_predecode_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_ICACHE_L0_PREDECODE_ECC_UNCORRECTED,
0, g->ecc.gr.sm_icache_ecc_uncorrected_err_count[gpc][tpc].counter);
}
if ((icache_ecc_status &
gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_ICACHE_L1_DATA_ECC_UNCORRECTED,
0, g->ecc.gr.sm_icache_ecc_uncorrected_err_count[gpc][tpc].counter);
}
if ((icache_ecc_status &
gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_predecode_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_ICACHE_L1_PREDECODE_ECC_UNCORRECTED,
0, g->ecc.gr.sm_icache_ecc_uncorrected_err_count[gpc][tpc].counter);
@@ -1452,28 +1452,28 @@ static void gv11b_gr_intr_report_icache_corrected_err(struct gk20a *g,
}
if ((icache_ecc_status &
gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_data_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_ICACHE_L0_DATA_ECC_CORRECTED,
0, g->ecc.gr.sm_icache_ecc_corrected_err_count[gpc][tpc].counter);
}
if ((icache_ecc_status &
gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_predecode_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_ICACHE_L0_PREDECODE_ECC_CORRECTED,
0, g->ecc.gr.sm_icache_ecc_corrected_err_count[gpc][tpc].counter);
}
if ((icache_ecc_status &
gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_data_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_ICACHE_L1_DATA_ECC_CORRECTED,
0, g->ecc.gr.sm_icache_ecc_corrected_err_count[gpc][tpc].counter);
}
if ((icache_ecc_status &
gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_predecode_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_SM,
(gpc << 8) | tpc,
GPU_SM_ICACHE_L1_PREDECODE_ECC_CORRECTED,
0, g->ecc.gr.sm_icache_ecc_corrected_err_count[gpc][tpc].counter);

16
drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b_fusa.c
View File

@@ -103,7 +103,7 @@ static void gv11b_ltc_intr_handle_rstg_ecc_interrupts(struct gk20a *g,
if ((ecc_status &
ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m())
!= 0U) {
(void) nvgpu_report_ecc_err(g,
nvgpu_report_ecc_err(g,
NVGPU_ERR_MODULE_LTC,
(ltc << 8U) | slice,
GPU_LTC_CACHE_RSTG_ECC_CORRECTED, ecc_addr,
@@ -113,7 +113,7 @@ static void gv11b_ltc_intr_handle_rstg_ecc_interrupts(struct gk20a *g,
if ((ecc_status &
ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m())
!= 0U) {
(void) nvgpu_report_ecc_err(g,
nvgpu_report_ecc_err(g,
NVGPU_ERR_MODULE_LTC,
(ltc << 8U) | slice,
GPU_LTC_CACHE_RSTG_ECC_UNCORRECTED, ecc_addr,
@@ -129,7 +129,7 @@ static void gv11b_ltc_intr_handle_tstg_ecc_interrupts(struct gk20a *g,
if ((ecc_status &
ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m())
!= 0U) {
(void) nvgpu_report_ecc_err(g,
nvgpu_report_ecc_err(g,
NVGPU_ERR_MODULE_LTC,
(ltc << 8U) | slice,
GPU_LTC_CACHE_TSTG_ECC_CORRECTED, ecc_addr,
@@ -139,7 +139,7 @@ static void gv11b_ltc_intr_handle_tstg_ecc_interrupts(struct gk20a *g,
if ((ecc_status &
ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m())
!= 0U) {
(void) nvgpu_report_ecc_err(g,
nvgpu_report_ecc_err(g,
NVGPU_ERR_MODULE_LTC,
(ltc << 8U) | slice,
GPU_LTC_CACHE_TSTG_ECC_UNCORRECTED, ecc_addr,
@@ -159,13 +159,13 @@ static void gv11b_ltc_intr_handle_dstg_ecc_interrupts(struct gk20a *g,
if ((dstg_ecc_addr &
ltc_ltc0_lts0_dstg_ecc_address_info_ram_m())
== 0U) {
(void) nvgpu_report_ecc_err(g,
nvgpu_report_ecc_err(g,
NVGPU_ERR_MODULE_LTC,
(ltc << 8U) | slice,
GPU_LTC_CACHE_DSTG_ECC_CORRECTED, ecc_addr,
g->ecc.ltc.ecc_sec_count[ltc][slice].counter);
} else {
(void) nvgpu_report_ecc_err(g,
nvgpu_report_ecc_err(g,
NVGPU_ERR_MODULE_LTC,
(ltc << 8U) | slice,
GPU_LTC_CACHE_DSTG_BE_ECC_CORRECTED, ecc_addr,
@@ -178,13 +178,13 @@ static void gv11b_ltc_intr_handle_dstg_ecc_interrupts(struct gk20a *g,
!= 0U) {
if ((dstg_ecc_addr &
ltc_ltc0_lts0_dstg_ecc_address_info_ram_m()) == 0U) {
(void) nvgpu_report_ecc_err(g,
nvgpu_report_ecc_err(g,
NVGPU_ERR_MODULE_LTC,
(ltc << 8U) | slice,
GPU_LTC_CACHE_DSTG_ECC_UNCORRECTED, ecc_addr,
g->ecc.ltc.ecc_ded_count[ltc][slice].counter);
} else {
(void) nvgpu_report_ecc_err(g,
nvgpu_report_ecc_err(g,
NVGPU_ERR_MODULE_LTC,
(ltc << 8U) | slice,
GPU_LTC_CACHE_DSTG_BE_ECC_UNCORRECTED, ecc_addr,

2
drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.h
View File

@@ -38,7 +38,7 @@ void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g,
#endif /* CONFIG_NVGPU_GRAPHICS */
#ifdef CONFIG_NVGPU_INJECT_HWERR
struct nvgpu_hw_err_inject_info_desc * gv11b_ltc_get_err_desc(struct gk20a *g);
int gv11b_ltc_inject_ecc_error(struct gk20a *g,
void gv11b_ltc_inject_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info);
#endif

4
drivers/gpu/nvgpu/hal/ltc/ltc_gv11b_fusa.c
View File

@@ -34,7 +34,7 @@
#include <nvgpu/utils.h>
#ifdef CONFIG_NVGPU_INJECT_HWERR
int gv11b_ltc_inject_ecc_error(struct gk20a *g,
void gv11b_ltc_inject_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
@@ -48,8 +48,6 @@ int gv11b_ltc_inject_ecc_error(struct gk20a *g,
nvgpu_info(g, "Injecting LTC fault %s for ltc: %d, lts: %d",
err->name, ltc, lts);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
return 0;
}
static inline u32 ltc0_lts0_l1_cache_ecc_control_r(void)

2
drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_gv11b_fusa.c
View File

@@ -500,7 +500,7 @@ void gv11b_mm_mmu_fault_handle_nonreplay_replay_fault(struct gk20a *g,
sub_err_type = GPU_HUBMMU_NONREPLAYABLE_FAULT_NOTIFY;
}
(void) nvgpu_report_mmu_err(g, NVGPU_ERR_MODULE_HUBMMU,
nvgpu_report_mmu_err(g, NVGPU_ERR_MODULE_HUBMMU,
GPU_HUBMMU_PAGE_FAULT_ERROR,
mmufault,
fault_status,

2
drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.h
View File

@@ -61,7 +61,7 @@ bool gv11b_pmu_validate_mem_integrity(struct gk20a *g);
#ifdef CONFIG_NVGPU_INJECT_HWERR
struct nvgpu_hw_err_inject_info_desc * gv11b_pmu_intr_get_err_desc(struct gk20a *g);
int gv11b_pmu_inject_ecc_error(struct gk20a *g,
void gv11b_pmu_inject_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info);
#endif /* CONFIG_NVGPU_INJECT_HWERR */

12
drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c
View File

@@ -40,13 +40,11 @@
#define ALIGN_4KB 12
#ifdef CONFIG_NVGPU_INJECT_HWERR
int gv11b_pmu_inject_ecc_error(struct gk20a *g,
void gv11b_pmu_inject_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
nvgpu_info(g, "Injecting PMU fault %s", err->name);
nvgpu_writel(g, err->get_reg_addr(), err->get_reg_val(1U));
return 0;
}
static inline u32 pmu_falcon_ecc_control_r(void)
@@ -183,7 +181,7 @@ int gv11b_pmu_correct_ecc(struct gk20a *g, u32 ecc_status, u32 ecc_addr)
if ((ecc_status &
pwr_pmu_falcon_ecc_status_corrected_err_imem_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_PMU, 0,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_PMU, 0,
GPU_PMU_FALCON_IMEM_ECC_CORRECTED,
ecc_addr,
g->ecc.pmu.pmu_ecc_corrected_err_count[0].counter);
@@ -191,7 +189,7 @@ int gv11b_pmu_correct_ecc(struct gk20a *g, u32 ecc_status, u32 ecc_addr)
}
if ((ecc_status &
pwr_pmu_falcon_ecc_status_uncorrected_err_imem_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_PMU, 0,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_PMU, 0,
GPU_PMU_FALCON_IMEM_ECC_UNCORRECTED,
ecc_addr,
g->ecc.pmu.pmu_ecc_uncorrected_err_count[0].counter);
@@ -200,7 +198,7 @@ int gv11b_pmu_correct_ecc(struct gk20a *g, u32 ecc_status, u32 ecc_addr)
}
if ((ecc_status &
pwr_pmu_falcon_ecc_status_corrected_err_dmem_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_PMU, 0,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_PMU, 0,
GPU_PMU_FALCON_DMEM_ECC_CORRECTED,
ecc_addr,
g->ecc.pmu.pmu_ecc_corrected_err_count[0].counter);
@@ -208,7 +206,7 @@ int gv11b_pmu_correct_ecc(struct gk20a *g, u32 ecc_status, u32 ecc_addr)
}
if ((ecc_status &
pwr_pmu_falcon_ecc_status_uncorrected_err_dmem_m()) != 0U) {
(void) nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_PMU, 0,
nvgpu_report_ecc_err(g, NVGPU_ERR_MODULE_PMU, 0,
GPU_PMU_FALCON_DMEM_ECC_UNCORRECTED,
ecc_addr,
g->ecc.pmu.pmu_ecc_uncorrected_err_count[0].counter);

66
drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h
View File

@@ -302,7 +302,7 @@ struct gr_err_info {
struct nvgpu_hw_err_inject_info {
/** String representation of error. */
const char *name;
int (*inject_hw_fault)(struct gk20a *g,
void (*inject_hw_fault)(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 err_info);
u32 (*get_reg_addr)(void);
u32 (*get_reg_val)(u32 val);
@@ -334,12 +334,10 @@ struct nvgpu_hw_err_inject_info_desc {
* - Forms error packet and checks whether it exceeds the max size.
* - Sends error packet to report error to 3LSS.
*
* @return 0 in case of success, <0 in case of failure.
* @retval -EINVAL in case of (1) invalid HW unit ID, (2) invalid error ID,
* (3) clock get time API failed, (4) the size of error packet exceeds
* maximum allowed size.
* @return None
* @retval None
*/
int nvgpu_report_host_err(struct gk20a *g, u32 hw_unit,
void nvgpu_report_host_err(struct gk20a *g, u32 hw_unit,
u32 inst, u32 err_id, u32 intr_info);
/**
@@ -359,12 +357,10 @@ int nvgpu_report_host_err(struct gk20a *g, u32 hw_unit,
* - Forms error packet and checks whether it exceeds the max size.
* - Sends error packet to report error to 3LSS.
*
* @return 0 in case of success, <0 in case of failure.
* @retval -EINVAL in case of (1) invalid HW unit ID, (2) invalid error ID,
* (3) clock get time API failed, (4) the size of error packet exceeds
* maximum allowed size.
* @return None
* @retval None
*/
int nvgpu_report_ce_err(struct gk20a *g, u32 hw_unit,
void nvgpu_report_ce_err(struct gk20a *g, u32 hw_unit,
u32 inst, u32 err_id, u32 intr_info);
/**
@@ -386,12 +382,10 @@ int nvgpu_report_ce_err(struct gk20a *g, u32 hw_unit,
* - Forms error packet and checks whether it exceeds the max size.
* - Sends error packet to report error to 3LSS.
*
* @return 0 in case of success, <0 in case of failure.
* @retval -EINVAL in case of (1) invalid HW unit ID, (2) invalid error ID,
* (3) clock get time API failed, (4) the size of error packet exceeds
* maximum allowed size.
* @return None
* @retval None
*/
int nvgpu_report_ecc_err(struct gk20a *g, u32 hw_unit, u32 inst,
void nvgpu_report_ecc_err(struct gk20a *g, u32 hw_unit, u32 inst,
u32 err_id, u64 err_addr, u64 err_count);
/**
@@ -410,12 +404,10 @@ int nvgpu_report_ecc_err(struct gk20a *g, u32 hw_unit, u32 inst,
* - Forms error packet and checks whether it exceeds the max size.
* - Sends error packet to report error to 3LSS.
*
* @return 0 in case of success, <0 in case of failure.
* @retval -EINVAL in case of (1) invalid HW unit ID, (2) invalid error ID,
* (3) clock get time API failed, (4) the size of error packet exceeds
* maximum allowed size.
* @return None
* @retval None
*/
int nvgpu_report_ctxsw_err(struct gk20a *g, u32 hw_unit, u32 err_id,
void nvgpu_report_ctxsw_err(struct gk20a *g, u32 hw_unit, u32 err_id,
void *data);
/**
@@ -436,12 +428,10 @@ int nvgpu_report_ctxsw_err(struct gk20a *g, u32 hw_unit, u32 err_id,
* - Forms error packet and checks whether it exceeds the max size.
* - Sends error packet to report error to 3LSS.
*
* @return 0 in case of success, <0 in case of failure.
* @retval -EINVAL in case of (1) invalid HW unit ID, (2) invalid error ID,
* (3) clock get time API failed, (4) the size of error packet exceeds
* maximum allowed size.
* @return None
* @retval None
*/
int nvgpu_report_gr_err(struct gk20a *g, u32 hw_unit, u32 inst,
void nvgpu_report_gr_err(struct gk20a *g, u32 hw_unit, u32 inst,
u32 err_id, struct gr_err_info *err_info, u32 sub_err_type);
/**
@@ -461,12 +451,10 @@ int nvgpu_report_gr_err(struct gk20a *g, u32 hw_unit, u32 inst,
* - Forms error packet and checks whether it exceeds the max size.
* - Sends error packet to report error to 3LSS.
*
* @return 0 in case of success, <0 in case of failure.
* @retval -EINVAL in case of (1) invalid HW unit ID, (2) invalid error ID,
* (3) clock get time API failed, (4) the size of error packet exceeds
* maximum allowed size.
* @return None
* @retval None
*/
int nvgpu_report_pmu_err(struct gk20a *g, u32 hw_unit, u32 err_id,
void nvgpu_report_pmu_err(struct gk20a *g, u32 hw_unit, u32 err_id,
u32 sub_err_type, u32 status);
/**
@@ -486,12 +474,10 @@ int nvgpu_report_pmu_err(struct gk20a *g, u32 hw_unit, u32 err_id,
* - Forms error packet and checks whether it exceeds the max size.
* - Sends error packet to report error to 3LSS.
*
* @return 0 in case of success, <0 in case of failure.
* @retval -EINVAL in case of (1) invalid HW unit ID, (2) invalid error ID,
* (3) clock get time API failed, (4) the size of error packet exceeds
* maximum allowed size.
* @return None
* @retval None
*/
int nvgpu_report_pri_err(struct gk20a *g, u32 hw_unit, u32 inst,
void nvgpu_report_pri_err(struct gk20a *g, u32 hw_unit, u32 inst,
u32 err_id, u32 err_addr, u32 err_code);
/**
@@ -511,12 +497,10 @@ int nvgpu_report_pri_err(struct gk20a *g, u32 hw_unit, u32 inst,
* - Forms error packet and checks whether it exceeds the max size.
* - Sends error packet to report error to 3LSS.
*
* @return 0 in case of success, <0 in case of failure.
* @retval -EINVAL in case of (1) invalid HW unit ID, (2) invalid error ID,
* (3) clock get time API failed, (4) the size of error packet exceeds
* maximum allowed size.
* @return None
* @retval None
*/
int nvgpu_report_mmu_err(struct gk20a *g, u32 hw_unit,
void nvgpu_report_mmu_err(struct gk20a *g, u32 hw_unit,
u32 err_id, struct mmu_fault_info *fault_info,
u32 status, u32 sub_err_type);

32
drivers/gpu/nvgpu/os/linux/sdl/sdl_stub.c
View File

@@ -25,51 +25,51 @@
struct gk20a;
struct mmu_fault_info;
int nvgpu_report_host_err(struct gk20a *g, u32 hw_unit,
void nvgpu_report_host_err(struct gk20a *g, u32 hw_unit,
u32 inst, u32 err_id, u32 intr_info)
{
return 0;
return;
}
int nvgpu_report_ecc_err(struct gk20a *g, u32 hw_unit, u32 inst,
void nvgpu_report_ecc_err(struct gk20a *g, u32 hw_unit, u32 inst,
u32 err_id, u64 err_addr, u64 err_count)
{
return 0;
return;
}
int nvgpu_report_gr_err(struct gk20a *g, u32 hw_unit, u32 inst,
void nvgpu_report_gr_err(struct gk20a *g, u32 hw_unit, u32 inst,
u32 err_id, struct gr_err_info *err_info, u32 sub_err_type)
{
return 0;
return;
}
int nvgpu_report_pmu_err(struct gk20a *g, u32 hw_unit, u32 err_id,
void nvgpu_report_pmu_err(struct gk20a *g, u32 hw_unit, u32 err_id,
u32 sub_err_type, u32 status)
{
return 0;
return;
}
int nvgpu_report_ce_err(struct gk20a *g, u32 hw_unit,
void nvgpu_report_ce_err(struct gk20a *g, u32 hw_unit,
u32 inst, u32 err_id, u32 intr_info)
{
return 0;
return;
}
int nvgpu_report_pri_err(struct gk20a *g, u32 hw_unit, u32 inst,
void nvgpu_report_pri_err(struct gk20a *g, u32 hw_unit, u32 inst,
u32 err_id, u32 err_addr, u32 err_code)
{
return 0;
return;
}
int nvgpu_report_ctxsw_err(struct gk20a *g, u32 hw_unit, u32 err_id,
void nvgpu_report_ctxsw_err(struct gk20a *g, u32 hw_unit, u32 err_id,
void *data)
{
return 0;
return;
}
int nvgpu_report_mmu_err(struct gk20a *g, u32 hw_unit,
void nvgpu_report_mmu_err(struct gk20a *g, u32 hw_unit,
u32 err_id, struct mmu_fault_info *fault_info,
u32 status, u32 sub_err_type)
{
return 0;
return;
}

32
drivers/gpu/nvgpu/os/posix/stubs.c
View File

@@ -47,51 +47,51 @@ void nvgpu_ecc_sysfs_remove(struct gk20a *g)
{
}
int nvgpu_report_host_err(struct gk20a *g, u32 hw_unit,
void nvgpu_report_host_err(struct gk20a *g, u32 hw_unit,
u32 inst, u32 err_id, u32 intr_info)
{
return 0;
return;
}
int nvgpu_report_ecc_err(struct gk20a *g, u32 hw_unit, u32 inst,
void nvgpu_report_ecc_err(struct gk20a *g, u32 hw_unit, u32 inst,
u32 err_id, u64 err_addr, u64 err_count)
{
return 0;
return;
}
int nvgpu_report_gr_err(struct gk20a *g, u32 hw_unit, u32 inst,
void nvgpu_report_gr_err(struct gk20a *g, u32 hw_unit, u32 inst,
u32 err_id, struct gr_err_info *err_info, u32 sub_err_type)
{
return 0;
return;
}
int nvgpu_report_pmu_err(struct gk20a *g, u32 hw_unit, u32 err_id,
void nvgpu_report_pmu_err(struct gk20a *g, u32 hw_unit, u32 err_id,
u32 sub_err_type, u32 status)
{
return 0;
return;
}
int nvgpu_report_ce_err(struct gk20a *g, u32 hw_unit,
void nvgpu_report_ce_err(struct gk20a *g, u32 hw_unit,
u32 inst, u32 err_id, u32 intr_info)
{
return 0;
return;
}
int nvgpu_report_pri_err(struct gk20a *g, u32 hw_unit, u32 inst,
void nvgpu_report_pri_err(struct gk20a *g, u32 hw_unit, u32 inst,
u32 err_id, u32 err_addr, u32 err_code)
{
return 0;
return;
}
int nvgpu_report_ctxsw_err(struct gk20a *g, u32 hw_unit, u32 err_id,
void nvgpu_report_ctxsw_err(struct gk20a *g, u32 hw_unit, u32 err_id,
void *data)
{
return 0;
return;
}
int nvgpu_report_mmu_err(struct gk20a *g, u32 hw_unit,
void nvgpu_report_mmu_err(struct gk20a *g, u32 hw_unit,
u32 err_id, struct mmu_fault_info *fault_info,
u32 status, u32 sub_err_type)
{
return 0;
return;
}