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gpu: nvgpu: whitelist MISRA violations for WARN_ON/BUG_ON

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Whitelist false positive violations cause by a Coverity bug that
that overrides the WARN_ON/BUG_ON macros. See nvbug 2277532 for
details on the bug.

JIRA NVGPU-4031

Change-Id: I395f97c89580195485e93275663a062f26ab6fc7
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2207326
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-09-27 11:09:50 -04:00
committed by Alex Waterman
parent 8ec2b11d04
commit 9378675213
11 changed files with 145 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/gpu/nvgpu/common/fifo/channel.c
View File

@@ -90,8 +90,14 @@ static struct nvgpu_channel *allocate_channel(struct nvgpu_fifo *f)
ch = nvgpu_list_first_entry(&f->free_chs, nvgpu_channel, ch = nvgpu_list_first_entry(&f->free_chs, nvgpu_channel,
free_chs); free_chs);
nvgpu_list_del(&ch->free_chs); nvgpu_list_del(&ch->free_chs);
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(nvgpu_atomic_read(&ch->ref_count) != 0); WARN_ON(nvgpu_atomic_read(&ch->ref_count) != 0);
WARN_ON(ch->referenceable); WARN_ON(ch->referenceable);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
f->used_channels = nvgpu_safe_add_u32(f->used_channels, 1U); f->used_channels = nvgpu_safe_add_u32(f->used_channels, 1U);
} }
nvgpu_mutex_release(&f->free_chs_mutex); nvgpu_mutex_release(&f->free_chs_mutex);
@@ -1966,12 +1972,18 @@ void nvgpu_channel_put__func(struct nvgpu_channel *ch, const char *caller)
/* More puts than gets. Channel is probably going to get /* More puts than gets. Channel is probably going to get
* stuck. */ * stuck. */
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(nvgpu_atomic_read(&ch->ref_count) < 0); WARN_ON(nvgpu_atomic_read(&ch->ref_count) < 0);
/* Also, more puts than gets. ref_count can go to 0 only if /* Also, more puts than gets. ref_count can go to 0 only if
* the channel is closing. Channel is probably going to get * the channel is closing. Channel is probably going to get
* stuck. */ * stuck. */
WARN_ON(nvgpu_atomic_read(&ch->ref_count) == 0 && ch->referenceable); WARN_ON(nvgpu_atomic_read(&ch->ref_count) == 0 && ch->referenceable);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
} }
struct nvgpu_channel *nvgpu_channel_from_id__func(struct gk20a *g, struct nvgpu_channel *nvgpu_channel_from_id__func(struct gk20a *g,
@@ -2025,7 +2037,11 @@ struct nvgpu_channel *nvgpu_channel_open_new(struct gk20a *g,
trace_nvgpu_channel_open_new(ch->chid); trace_nvgpu_channel_open_new(ch->chid);
#endif #endif
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
BUG_ON(ch->g != NULL); BUG_ON(ch->g != NULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
ch->g = g; ch->g = g;
/* Runlist for the channel */ /* Runlist for the channel */

6
drivers/gpu/nvgpu/common/fifo/runlist.c
View File

@@ -387,7 +387,13 @@ static int gk20a_runlist_reconstruct_locked(struct gk20a *g, u32 runlist_id,
return -E2BIG; return -E2BIG;
} }
runlist->count = num_entries; runlist->count = num_entries;
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(runlist->count > f->num_runlist_entries); WARN_ON(runlist->count > f->num_runlist_entries);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
} else { } else {
runlist->count = 0; runlist->count = 0;
} }

6
drivers/gpu/nvgpu/common/fifo/tsg.c
View File

@@ -844,7 +844,13 @@ void nvgpu_tsg_abort(struct gk20a *g, struct nvgpu_tsg *tsg, bool preempt)
nvgpu_log_fn(g, " "); nvgpu_log_fn(g, " ");
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(tsg->abortable == false); WARN_ON(tsg->abortable == false);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
g->ops.tsg.disable(tsg); g->ops.tsg.disable(tsg);

14
drivers/gpu/nvgpu/common/mm/allocators/buddy_allocator.c
View File

@@ -115,7 +115,13 @@ static void balloc_compute_max_order(struct nvgpu_buddy_allocator *a)
static void balloc_allocator_align(struct nvgpu_buddy_allocator *a) static void balloc_allocator_align(struct nvgpu_buddy_allocator *a)
{ {
a->start = ALIGN(a->base, a->blk_size); a->start = ALIGN(a->base, a->blk_size);
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(a->start != a->base); WARN_ON(a->start != a->base);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
nvgpu_assert(a->blk_size > 0ULL); nvgpu_assert(a->blk_size > 0ULL);
a->end = nvgpu_safe_add_u64(a->base, a->length) & a->end = nvgpu_safe_add_u64(a->base, a->length) &
~(a->blk_size - 1U); ~(a->blk_size - 1U);
@@ -327,7 +333,11 @@ static void nvgpu_buddy_allocator_destroy(struct nvgpu_allocator *na)
* Now clean up the unallocated buddies. * Now clean up the unallocated buddies.
*/ */
for (i = 0U; i < GPU_BALLOC_ORDER_LIST_LEN; i++) { for (i = 0U; i < GPU_BALLOC_ORDER_LIST_LEN; i++) {
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
BUG_ON(a->buddy_list_alloced[i] != 0U); BUG_ON(a->buddy_list_alloced[i] != 0U);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
while (!nvgpu_list_empty(balloc_get_order_list(a, i))) { while (!nvgpu_list_empty(balloc_get_order_list(a, i))) {
bud = nvgpu_list_first_entry( bud = nvgpu_list_first_entry(
@@ -770,7 +780,11 @@ static u64 balloc_do_alloc_fixed(struct nvgpu_buddy_allocator *a,
* in the lists that hold buddies. This leads to some very strange * in the lists that hold buddies. This leads to some very strange
* crashes. * crashes.
*/ */
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
BUG_ON(pte_size == BALLOC_PTE_SIZE_INVALID); BUG_ON(pte_size == BALLOC_PTE_SIZE_INVALID);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
shifted_base = balloc_base_shift(a, base); shifted_base = balloc_base_shift(a, base);
if (shifted_base == 0U) { if (shifted_base == 0U) {

60
drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
View File

@@ -115,7 +115,13 @@ u32 nvgpu_mem_rd32(struct gk20a *g, struct nvgpu_mem *mem, u64 w)
if (mem->aperture == APERTURE_SYSMEM) { if (mem->aperture == APERTURE_SYSMEM) {
u32 *ptr = mem->cpu_va; u32 *ptr = mem->cpu_va;
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(ptr == NULL); WARN_ON(ptr == NULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
data = ptr[w]; data = ptr[w];
} }
#ifdef CONFIG_NVGPU_DGPU #ifdef CONFIG_NVGPU_DGPU
@@ -141,20 +147,38 @@ u64 nvgpu_mem_rd32_pair(struct gk20a *g, struct nvgpu_mem *mem, u32 lo, u32 hi)
u32 nvgpu_mem_rd(struct gk20a *g, struct nvgpu_mem *mem, u64 offset) u32 nvgpu_mem_rd(struct gk20a *g, struct nvgpu_mem *mem, u64 offset)
{ {
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON((offset & 3ULL) != 0ULL); WARN_ON((offset & 3ULL) != 0ULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
return nvgpu_mem_rd32(g, mem, offset / (u64)sizeof(u32)); return nvgpu_mem_rd32(g, mem, offset / (u64)sizeof(u32));
} }
void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem, void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem,
u64 offset, void *dest, u64 size) u64 offset, void *dest, u64 size)
{ {
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON((offset & 3ULL) != 0ULL); WARN_ON((offset & 3ULL) != 0ULL);
WARN_ON((size & 3ULL) != 0ULL); WARN_ON((size & 3ULL) != 0ULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
if (mem->aperture == APERTURE_SYSMEM) { if (mem->aperture == APERTURE_SYSMEM) {
u8 *src = (u8 *)mem->cpu_va + offset; u8 *src = (u8 *)mem->cpu_va + offset;
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(mem->cpu_va == NULL); WARN_ON(mem->cpu_va == NULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
nvgpu_memcpy((u8 *)dest, src, size); nvgpu_memcpy((u8 *)dest, src, size);
} }
#ifdef CONFIG_NVGPU_DGPU #ifdef CONFIG_NVGPU_DGPU
@@ -172,7 +196,13 @@ void nvgpu_mem_wr32(struct gk20a *g, struct nvgpu_mem *mem, u64 w, u32 data)
if (mem->aperture == APERTURE_SYSMEM) { if (mem->aperture == APERTURE_SYSMEM) {
u32 *ptr = mem->cpu_va; u32 *ptr = mem->cpu_va;
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(ptr == NULL); WARN_ON(ptr == NULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
ptr[w] = data; ptr[w] = data;
} }
#ifdef CONFIG_NVGPU_DGPU #ifdef CONFIG_NVGPU_DGPU
@@ -192,20 +222,38 @@ void nvgpu_mem_wr32(struct gk20a *g, struct nvgpu_mem *mem, u64 w, u32 data)
void nvgpu_mem_wr(struct gk20a *g, struct nvgpu_mem *mem, u64 offset, u32 data) void nvgpu_mem_wr(struct gk20a *g, struct nvgpu_mem *mem, u64 offset, u32 data)
{ {
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON((offset & 3ULL) != 0ULL); WARN_ON((offset & 3ULL) != 0ULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
nvgpu_mem_wr32(g, mem, offset / (u64)sizeof(u32), data); nvgpu_mem_wr32(g, mem, offset / (u64)sizeof(u32), data);
} }
void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u64 offset, void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u64 offset,
void *src, u64 size) void *src, u64 size)
{ {
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON((offset & 3ULL) != 0ULL); WARN_ON((offset & 3ULL) != 0ULL);
WARN_ON((size & 3ULL) != 0ULL); WARN_ON((size & 3ULL) != 0ULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
if (mem->aperture == APERTURE_SYSMEM) { if (mem->aperture == APERTURE_SYSMEM) {
u8 *dest = (u8 *)mem->cpu_va + offset; u8 *dest = (u8 *)mem->cpu_va + offset;
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(mem->cpu_va == NULL); WARN_ON(mem->cpu_va == NULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
nvgpu_memcpy(dest, (u8 *)src, size); nvgpu_memcpy(dest, (u8 *)src, size);
} }
#ifdef CONFIG_NVGPU_DGPU #ifdef CONFIG_NVGPU_DGPU
@@ -224,16 +272,28 @@ void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u64 offset,
void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u64 offset, void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u64 offset,
u32 c, u64 size) u32 c, u64 size)
{ {
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 3, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 3, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 3, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON((offset & 3ULL) != 0ULL); WARN_ON((offset & 3ULL) != 0ULL);
WARN_ON((size & 3ULL) != 0ULL); WARN_ON((size & 3ULL) != 0ULL);
WARN_ON((c & ~0xffU) != 0U); WARN_ON((c & ~0xffU) != 0U);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
c &= 0xffU; c &= 0xffU;
if (mem->aperture == APERTURE_SYSMEM) { if (mem->aperture == APERTURE_SYSMEM) {
u8 *dest = (u8 *)mem->cpu_va + offset; u8 *dest = (u8 *)mem->cpu_va + offset;
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(mem->cpu_va == NULL); WARN_ON(mem->cpu_va == NULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
(void) memset(dest, (int)c, size); (void) memset(dest, (int)c, size);
} }
#ifdef CONFIG_NVGPU_DGPU #ifdef CONFIG_NVGPU_DGPU

10
drivers/gpu/nvgpu/common/mm/vm.c
View File

@@ -279,7 +279,13 @@ void nvgpu_vm_mapping_batch_finish_locked(
int err; int err;
/* hanging kref_put batch pointer? */ /* hanging kref_put batch pointer? */
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(vm->kref_put_batch == mapping_batch); WARN_ON(vm->kref_put_batch == mapping_batch);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
if (mapping_batch->need_tlb_invalidate) { if (mapping_batch->need_tlb_invalidate) {
struct gk20a *g = gk20a_from_vm(vm); struct gk20a *g = gk20a_from_vm(vm);
@@ -929,7 +935,11 @@ int nvgpu_vm_get_buffers(struct vm_gk20a *vm,
nvgpu_rbtree_enum_next(&node, node); nvgpu_rbtree_enum_next(&node, node);
} }
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
BUG_ON(i != vm->num_user_mapped_buffers); BUG_ON(i != vm->num_user_mapped_buffers);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
*num_buffers = vm->num_user_mapped_buffers; *num_buffers = vm->num_user_mapped_buffers;
*mapped_buffers = buffer_list; *mapped_buffers = buffer_list;

12
drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b_fusa.c
View File

@@ -253,7 +253,11 @@ u32 gm20b_pbdma_acquire_val(u64 timeout)
timeout *= 1000000UL; /* ms -> ns */ timeout *= 1000000UL; /* ms -> ns */
do_div(timeout, 1024U); /* in unit of 1024ns */ do_div(timeout, 1024U); /* in unit of 1024ns */
tmp = nvgpu_fls(timeout >> 32U); tmp = nvgpu_fls(timeout >> 32U);
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
BUG_ON(tmp > U64(U32_MAX)); BUG_ON(tmp > U64(U32_MAX));
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
val_len = (u32)tmp + 32U; val_len = (u32)tmp + 32U;
if (val_len == 32U) { if (val_len == 32U) {
val_len = nvgpu_safe_cast_u64_to_u32(nvgpu_fls(timeout)); val_len = nvgpu_safe_cast_u64_to_u32(nvgpu_fls(timeout));
@@ -263,11 +267,19 @@ u32 gm20b_pbdma_acquire_val(u64 timeout)
mantissa = pbdma_acquire_timeout_man_max_v(); mantissa = pbdma_acquire_timeout_man_max_v();
} else if (val_len > 16U) { } else if (val_len > 16U) {
exponent = val_len - 16U; exponent = val_len - 16U;
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
BUG_ON((timeout >> exponent) > U64(U32_MAX)); BUG_ON((timeout >> exponent) > U64(U32_MAX));
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
mantissa = (u32)(timeout >> exponent); mantissa = (u32)(timeout >> exponent);
} else { } else {
exponent = 0; exponent = 0;
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
BUG_ON(timeout > U64(U32_MAX)); BUG_ON(timeout > U64(U32_MAX));
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
mantissa = (u32)timeout; mantissa = (u32)timeout;
} }

6
drivers/gpu/nvgpu/hal/fifo/runlist_ram_gv11b_fusa.c
View File

@@ -44,7 +44,13 @@ void gv11b_runlist_get_tsg_entry(struct nvgpu_tsg *tsg,
u32 timeout = timeslice; u32 timeout = timeslice;
u32 scale = 0U; u32 scale = 0U;
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(timeslice == 0U); WARN_ON(timeslice == 0U);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
while (timeout > RL_MAX_TIMESLICE_TIMEOUT) { while (timeout > RL_MAX_TIMESLICE_TIMEOUT) {
timeout >>= 1U; timeout >>= 1U;

4
drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c
View File

@@ -137,7 +137,11 @@ void gm20b_gr_falcon_bind_instblk(struct gk20a *g,
nvgpu_writel(g, gr_fecs_arb_ctx_adr_r(), 0x0); nvgpu_writel(g, gr_fecs_arb_ctx_adr_r(), 0x0);
inst_ptr >>= 12; inst_ptr >>= 12;
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
BUG_ON(u64_hi32(inst_ptr) != 0U); BUG_ON(u64_hi32(inst_ptr) != 0U);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
inst_ptr_u32 = (u32)inst_ptr; inst_ptr_u32 = (u32)inst_ptr;
nvgpu_writel(g, gr_fecs_new_ctx_r(), nvgpu_writel(g, gr_fecs_new_ctx_r(),
gr_fecs_new_ctx_ptr_f(inst_ptr_u32) | gr_fecs_new_ctx_ptr_f(inst_ptr_u32) |

5
drivers/gpu/nvgpu/include/nvgpu/bug.h
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@@ -27,6 +27,7 @@
#else #else
#include <nvgpu/posix/bug.h> #include <nvgpu/posix/bug.h>
#endif #endif
#include <nvgpu/static_analysis.h>
/* /*
* Define an assert macro that code within nvgpu can use. * Define an assert macro that code within nvgpu can use.
@@ -56,7 +57,11 @@
*/ */
static inline void nvgpu_assert(bool cond) static inline void nvgpu_assert(bool cond)
{ {
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
BUG_ON(!cond); BUG_ON(!cond);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
} }
#endif #endif

7
drivers/gpu/nvgpu/include/nvgpu/static_analysis.h
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@@ -30,7 +30,6 @@
*/ */
#include <nvgpu/types.h> #include <nvgpu/types.h>
#include <nvgpu/bug.h>
/** @name Coverity Whitelisting /** @name Coverity Whitelisting
* These macros are used for whitelisting coverity violations. The macros are * These macros are used for whitelisting coverity violations. The macros are
@@ -165,6 +164,12 @@
#endif #endif
/**@}*/ /* "Coverity Whitelisting" doxygen group */ /**@}*/ /* "Coverity Whitelisting" doxygen group */
/*
* bug.h needs the whitelist macros, so wait to include it until after those
* are defined.
*/
#include <nvgpu/bug.h>
static inline u32 nvgpu_safe_add_u32(u32 ui_a, u32 ui_b) static inline u32 nvgpu_safe_add_u32(u32 ui_a, u32 ui_b)
{ {
if (UINT_MAX - ui_a < ui_b) { if (UINT_MAX - ui_a < ui_b) {