diff --git a/drivers/gpu/nvgpu/common/fifo/runlist.c b/drivers/gpu/nvgpu/common/fifo/runlist.c
index afe77bff9..5092d6a68 100644
--- a/drivers/gpu/nvgpu/common/fifo/runlist.c
+++ b/drivers/gpu/nvgpu/common/fifo/runlist.c
@@ -45,7 +45,7 @@ static u32 nvgpu_runlist_append_tsg(struct gk20a *g,
 
 	/* add TSG entry */
 	nvgpu_log_info(g, "add TSG %d to runlist", tsg->tsgid);
-	g->ops.runlist.get_tsg_runlist_entry(tsg, *runlist_entry);
+	g->ops.runlist.get_tsg_entry(tsg, *runlist_entry);
 	nvgpu_log_info(g, "tsg rl entries left %d runlist [0] %x [1] %x",
 			*entries_left,
 			(*runlist_entry)[0], (*runlist_entry)[1]);
@@ -69,7 +69,7 @@ static u32 nvgpu_runlist_append_tsg(struct gk20a *g,
 
 		nvgpu_log_info(g, "add channel %d to runlist",
 			ch->chid);
-		g->ops.runlist.get_ch_runlist_entry(ch, *runlist_entry);
+		g->ops.runlist.get_ch_entry(ch, *runlist_entry);
 		nvgpu_log_info(g, "rl entries left %d runlist [0] %x [1] %x",
 			*entries_left,
 			(*runlist_entry)[0], (*runlist_entry)[1]);
@@ -382,10 +382,10 @@ int gk20a_runlist_update_locked(struct gk20a *g, u32 runlist_id,
 		return ret;
 	}
 
-	g->ops.runlist.runlist_hw_submit(g, runlist_id, runlist->count, buf_id);
+	g->ops.runlist.hw_submit(g, runlist_id, runlist->count, buf_id);
 
 	if (wait_for_finish) {
-		ret = g->ops.runlist.runlist_wait_pending(g, runlist_id);
+		ret = g->ops.runlist.wait_pending(g, runlist_id);
 
 		if (ret == -ETIMEDOUT) {
 			nvgpu_err(g, "runlist %d update timeout", runlist_id);
@@ -422,14 +422,14 @@ int nvgpu_fifo_reschedule_runlist(struct channel_gk20a *ch, bool preempt_next,
 			&g->pmu, PMU_MUTEX_ID_FIFO, &token);
 	}
 
-	g->ops.runlist.runlist_hw_submit(
+	g->ops.runlist.hw_submit(
 		g, ch->runlist_id, runlist->count, runlist->cur_buffer);
 
 	if (preempt_next) {
 		g->ops.runlist.reschedule_preempt_next_locked(ch, wait_preempt);
 	}
 
-	g->ops.runlist.runlist_wait_pending(g, ch->runlist_id);
+	g->ops.runlist.wait_pending(g, ch->runlist_id);
 
 	if (mutex_ret == 0) {
 		nvgpu_pmu_mutex_release(
@@ -571,7 +571,7 @@ void gk20a_fifo_set_runlist_state(struct gk20a *g, u32 runlists_mask,
 						PMU_MUTEX_ID_FIFO, &token);
 	}
 
-	g->ops.runlist.runlist_write_state(g, runlists_mask, runlist_state);
+	g->ops.runlist.write_state(g, runlists_mask, runlist_state);
 
 	if (mutex_ret == 0) {
 		nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token);
@@ -624,7 +624,7 @@ int nvgpu_init_runlist(struct gk20a *g, struct fifo_gk20a *f)
 
 	nvgpu_log_fn(g, " ");
 
-	f->max_runlists = g->ops.runlist.eng_runlist_base_size();
+	f->max_runlists = g->ops.runlist.count_max();
 	f->runlist_info = nvgpu_kzalloc(g,
 					sizeof(struct fifo_runlist_info_gk20a) *
 					f->max_runlists);
diff --git a/drivers/gpu/nvgpu/common/fifo/runlist_gk20a.c b/drivers/gpu/nvgpu/common/fifo/runlist_gk20a.c
index 77d967f50..3a1b71f48 100644
--- a/drivers/gpu/nvgpu/common/fifo/runlist_gk20a.c
+++ b/drivers/gpu/nvgpu/common/fifo/runlist_gk20a.c
@@ -37,7 +37,7 @@
 #define FECS_METHOD_WFI_RESTORE 0x80000U
 #define FECS_MAILBOX_0_ACK_RESTORE 0x4U
 
-int gk20a_fifo_reschedule_runlist(struct channel_gk20a *ch, bool preempt_next)
+int gk20a_runlist_reschedule(struct channel_gk20a *ch, bool preempt_next)
 {
 	return nvgpu_fifo_reschedule_runlist(ch, preempt_next, true);
 }
@@ -103,7 +103,7 @@ int gk20a_fifo_reschedule_preempt_next(struct channel_gk20a *ch,
 	return ret;
 }
 
-int gk20a_fifo_set_runlist_interleave(struct gk20a *g,
+int gk20a_runlist_set_interleave(struct gk20a *g,
 				u32 id,
 				u32 runlist_id,
 				u32 new_level)
@@ -115,17 +115,17 @@ int gk20a_fifo_set_runlist_interleave(struct gk20a *g,
 	return 0;
 }
 
-u32 gk20a_fifo_runlist_base_size(void)
+u32 gk20a_runlist_count_max(void)
 {
 	return fifo_eng_runlist_base__size_1_v();
 }
 
-u32 gk20a_fifo_runlist_entry_size(void)
+u32 gk20a_runlist_entry_size(void)
 {
 	return ram_rl_entry_size_v();
 }
 
-void gk20a_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist)
+void gk20a_runlist_get_tsg_entry(struct tsg_gk20a *tsg, u32 *runlist)
 {
 
 	u32 runlist_entry_0 = ram_rl_entry_id_f(tsg->tsgid) |
@@ -156,13 +156,13 @@ void gk20a_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist)
 
 }
 
-void gk20a_get_ch_runlist_entry(struct channel_gk20a *ch, u32 *runlist)
+void gk20a_runlist_get_ch_entry(struct channel_gk20a *ch, u32 *runlist)
 {
 	runlist[0] = ram_rl_entry_chid_f(ch->chid);
 	runlist[1] = 0;
 }
 
-void gk20a_fifo_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
+void gk20a_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
 	u32 count, u32 buffer_index)
 {
 	struct fifo_runlist_info_gk20a *runlist = NULL;
@@ -189,7 +189,7 @@ void gk20a_fifo_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
 	nvgpu_spinlock_release(&g->fifo.runlist_submit_lock);
 }
 
-int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id)
+int gk20a_runlist_wait_pending(struct gk20a *g, u32 runlist_id)
 {
 	struct nvgpu_timeout timeout;
 	u32 delay = GR_IDLE_CHECK_DEFAULT;
@@ -217,7 +217,7 @@ int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id)
 	return ret;
 }
 
-void gk20a_fifo_runlist_write_state(struct gk20a *g, u32 runlists_mask,
+void gk20a_runlist_write_state(struct gk20a *g, u32 runlists_mask,
 					 u32 runlist_state)
 {
 	u32 reg_val;
diff --git a/drivers/gpu/nvgpu/common/fifo/runlist_gk20a.h b/drivers/gpu/nvgpu/common/fifo/runlist_gk20a.h
index c5a51c3e6..5f932b86e 100644
--- a/drivers/gpu/nvgpu/common/fifo/runlist_gk20a.h
+++ b/drivers/gpu/nvgpu/common/fifo/runlist_gk20a.h
@@ -28,21 +28,21 @@ struct channel_gk20a;
 struct tsg_gk20a;
 struct gk20a;
 
-int gk20a_fifo_reschedule_runlist(struct channel_gk20a *ch, bool preempt_next);
+int gk20a_runlist_reschedule(struct channel_gk20a *ch, bool preempt_next);
 int gk20a_fifo_reschedule_preempt_next(struct channel_gk20a *ch,
 		bool wait_preempt);
-int gk20a_fifo_set_runlist_interleave(struct gk20a *g,
+int gk20a_runlist_set_interleave(struct gk20a *g,
 		u32 id,
 		u32 runlist_id,
 		u32 new_level);
-u32 gk20a_fifo_runlist_base_size(void);
-u32 gk20a_fifo_runlist_entry_size(void);
-void gk20a_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist);
-void gk20a_get_ch_runlist_entry(struct channel_gk20a *ch, u32 *runlist);
-void gk20a_fifo_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
+u32 gk20a_runlist_count_max(void);
+u32 gk20a_runlist_entry_size(void);
+void gk20a_runlist_get_tsg_entry(struct tsg_gk20a *tsg, u32 *runlist);
+void gk20a_runlist_get_ch_entry(struct channel_gk20a *ch, u32 *runlist);
+void gk20a_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
 		u32 count, u32 buffer_index);
-int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id);
-void gk20a_fifo_runlist_write_state(struct gk20a *g, u32 runlists_mask,
+int gk20a_runlist_wait_pending(struct gk20a *g, u32 runlist_id);
+void gk20a_runlist_write_state(struct gk20a *g, u32 runlists_mask,
 		u32 runlist_state);
 
 #endif /* NVGPU_RUNLIST_GK20A_H */
diff --git a/drivers/gpu/nvgpu/common/fifo/runlist_gv100.c b/drivers/gpu/nvgpu/common/fifo/runlist_gv100.c
index 84d33b06c..572773869 100644
--- a/drivers/gpu/nvgpu/common/fifo/runlist_gv100.c
+++ b/drivers/gpu/nvgpu/common/fifo/runlist_gv100.c
@@ -24,7 +24,7 @@
 
 #include <nvgpu/hw/gv100/hw_fifo_gv100.h>
 
-u32 gv100_fifo_runlist_base_size(void)
+u32 gv100_runlist_count_max(void)
 {
 	return fifo_eng_runlist_base__size_1_v();
 }
diff --git a/drivers/gpu/nvgpu/common/fifo/runlist_gv100.h b/drivers/gpu/nvgpu/common/fifo/runlist_gv100.h
index 2a530ee2d..a361bb14a 100644
--- a/drivers/gpu/nvgpu/common/fifo/runlist_gv100.h
+++ b/drivers/gpu/nvgpu/common/fifo/runlist_gv100.h
@@ -24,6 +24,6 @@
 
 #include <nvgpu/types.h>
 
-u32 gv100_fifo_runlist_base_size(void);
+u32 gv100_runlist_count_max(void);
 
 #endif /* NVGPU_RUNLIST_GV100_H */
diff --git a/drivers/gpu/nvgpu/common/fifo/runlist_gv11b.c b/drivers/gpu/nvgpu/common/fifo/runlist_gv11b.c
index 13cc6c58e..f3d0569fa 100644
--- a/drivers/gpu/nvgpu/common/fifo/runlist_gv11b.c
+++ b/drivers/gpu/nvgpu/common/fifo/runlist_gv11b.c
@@ -31,24 +31,24 @@
 #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
 
-int gv11b_fifo_reschedule_runlist(struct channel_gk20a *ch, bool preempt_next)
+int gv11b_runlist_reschedule(struct channel_gk20a *ch, bool preempt_next)
 {
 	/* gv11b allows multiple outstanding preempts,
 	   so always preempt next for best reschedule effect */
 	return nvgpu_fifo_reschedule_runlist(ch, true, false);
 }
 
-u32 gv11b_fifo_runlist_base_size(void)
+u32 gv11b_runlist_count_max(void)
 {
 	return fifo_eng_runlist_base__size_1_v();
 }
 
-u32 gv11b_fifo_runlist_entry_size(void)
+u32 gv11b_runlist_entry_size(void)
 {
 	return ram_rl_entry_size_v();
 }
 
-void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist)
+void gv11b_runlist_get_tsg_entry(struct tsg_gk20a *tsg, u32 *runlist)
 {
 	struct gk20a *g = tsg->g;
 	u32 runlist_entry_0 = ram_rl_entry_type_tsg_v();
@@ -75,7 +75,7 @@ void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist)
 
 }
 
-void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist)
+void gv11b_runlist_get_ch_entry(struct channel_gk20a *c, u32 *runlist)
 {
 	struct gk20a *g = c->g;
 	u32 addr_lo, addr_hi;
diff --git a/drivers/gpu/nvgpu/common/fifo/runlist_gv11b.h b/drivers/gpu/nvgpu/common/fifo/runlist_gv11b.h
index a7f134639..26283a042 100644
--- a/drivers/gpu/nvgpu/common/fifo/runlist_gv11b.h
+++ b/drivers/gpu/nvgpu/common/fifo/runlist_gv11b.h
@@ -27,10 +27,10 @@
 struct channel_gk20a;
 struct tsg_gk20a;
 
-int gv11b_fifo_reschedule_runlist(struct channel_gk20a *ch, bool preempt_next);
-u32 gv11b_fifo_runlist_base_size(void);
-u32 gv11b_fifo_runlist_entry_size(void);
-void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist);
-void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist);
+int gv11b_runlist_reschedule(struct channel_gk20a *ch, bool preempt_next);
+u32 gv11b_runlist_count_max(void);
+u32 gv11b_runlist_entry_size(void);
+void gv11b_runlist_get_tsg_entry(struct tsg_gk20a *tsg, u32 *runlist);
+void gv11b_runlist_get_ch_entry(struct channel_gk20a *c, u32 *runlist);
 
 #endif /* NVGPU_RUNLIST_GV11B_H */
diff --git a/drivers/gpu/nvgpu/common/fifo/runlist_tu104.c b/drivers/gpu/nvgpu/common/fifo/runlist_tu104.c
index 05e8fd55d..6fb889316 100644
--- a/drivers/gpu/nvgpu/common/fifo/runlist_tu104.c
+++ b/drivers/gpu/nvgpu/common/fifo/runlist_tu104.c
@@ -32,17 +32,17 @@
 #include <nvgpu/hw/tu104/hw_fifo_tu104.h>
 #include <nvgpu/hw/tu104/hw_ram_tu104.h>
 
-u32 tu104_fifo_runlist_base_size(void)
+u32 tu104_runlist_count_max(void)
 {
 	return fifo_runlist_base_lo__size_1_v();
 }
 
-u32 tu104_fifo_runlist_entry_size(void)
+u32 tu104_runlist_entry_size(void)
 {
 	return ram_rl_entry_size_v();
 }
 
-void tu104_fifo_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
+void tu104_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
 	u32 count, u32 buffer_index)
 {
 	struct fifo_runlist_info_gk20a *runlist = NULL;
@@ -72,7 +72,7 @@ void tu104_fifo_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
 		fifo_runlist_submit_length_f(count));
 }
 
-int tu104_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id)
+int tu104_runlist_wait_pending(struct gk20a *g, u32 runlist_id)
 {
 	struct nvgpu_timeout timeout;
 	u32 delay = GR_IDLE_CHECK_DEFAULT;
diff --git a/drivers/gpu/nvgpu/common/fifo/runlist_tu104.h b/drivers/gpu/nvgpu/common/fifo/runlist_tu104.h
index c47716e95..afdae3f23 100644
--- a/drivers/gpu/nvgpu/common/fifo/runlist_tu104.h
+++ b/drivers/gpu/nvgpu/common/fifo/runlist_tu104.h
@@ -26,10 +26,10 @@
 
 struct gk20a;
 
-u32 tu104_fifo_runlist_base_size(void);
-u32 tu104_fifo_runlist_entry_size(void);
-void tu104_fifo_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
+u32 tu104_runlist_count_max(void);
+u32 tu104_runlist_entry_size(void);
+void tu104_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
 		u32 count, u32 buffer_index);
-int tu104_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id);
+int tu104_runlist_wait_pending(struct gk20a *g, u32 runlist_id);
 
 #endif /* NVGPU_RUNLIST_TU104_H */
diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c
index 87dd58dd5..535c40757 100644
--- a/drivers/gpu/nvgpu/common/fifo/tsg.c
+++ b/drivers/gpu/nvgpu/common/fifo/tsg.c
@@ -373,7 +373,7 @@ int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level)
 	case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW:
 	case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
 	case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH:
-		ret = g->ops.runlist.set_runlist_interleave(g, tsg->tsgid,
+		ret = g->ops.runlist.set_interleave(g, tsg->tsgid,
 							0, level);
 		if (ret == 0) {
 			tsg->interleave_level = level;
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index e032de634..3223666a7 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -642,7 +642,7 @@ int gk20a_init_fifo_setup_sw_common(struct gk20a *g)
 	g->ops.fifo.init_pbdma_intr_descs(f); /* just filling in data/tables */
 
 	f->num_channels = g->ops.channel.count(g);
-	f->runlist_entry_size =  g->ops.runlist.runlist_entry_size();
+	f->runlist_entry_size = g->ops.runlist.entry_size();
 	f->num_runlist_entries = fifo_eng_runlist_length_max_v();
 	f->num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
 	f->max_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index 5d76913bf..270d2f9fa 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -83,7 +83,7 @@ struct fifo_runlist_info_gk20a {
 	u32  pbdma_bitmask;      /* pbdmas supported for this runlist*/
 	u32  eng_bitmask;        /* engines using this runlist */
 	u32  reset_eng_bitmask;  /* engines to be reset during recovery */
-	u32  count;              /* cached runlist_hw_submit parameter */
+	u32  count;              /* cached hw_submit parameter */
 	bool stopped;
 	bool support_tsg;
 	/* protect ch/tsg/runlist preempt & runlist update */
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index dcfa69316..97fcf37ba 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -567,14 +567,14 @@ static const struct gpu_ops gm20b_ops = {
 	.runlist = {
 		.update_for_channel = gk20a_runlist_update_for_channel,
 		.reload = gk20a_runlist_reload,
-		.set_runlist_interleave = gk20a_fifo_set_runlist_interleave,
-		.eng_runlist_base_size = gk20a_fifo_runlist_base_size,
-		.runlist_entry_size = gk20a_fifo_runlist_entry_size,
-		.get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
-		.get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
-		.runlist_hw_submit = gk20a_fifo_runlist_hw_submit,
-		.runlist_wait_pending = gk20a_fifo_runlist_wait_pending,
-		.runlist_write_state = gk20a_fifo_runlist_write_state,
+		.set_interleave = gk20a_runlist_set_interleave,
+		.count_max = gk20a_runlist_count_max,
+		.entry_size = gk20a_runlist_entry_size,
+		.get_tsg_entry = gk20a_runlist_get_tsg_entry,
+		.get_ch_entry = gk20a_runlist_get_ch_entry,
+		.hw_submit = gk20a_runlist_hw_submit,
+		.wait_pending = gk20a_runlist_wait_pending,
+		.write_state = gk20a_runlist_write_state,
 	},
 	.channel = {
 		.bind = gm20b_channel_bind,
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index efaea6d89..1b7244366 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -616,18 +616,18 @@ static const struct gpu_ops gp10b_ops = {
 			gm20b_read_engine_status_info,
 	},
 	.runlist = {
-		.reschedule_runlist = gk20a_fifo_reschedule_runlist,
+		.reschedule = gk20a_runlist_reschedule,
 		.reschedule_preempt_next_locked = gk20a_fifo_reschedule_preempt_next,
 		.update_for_channel = gk20a_runlist_update_for_channel,
 		.reload = gk20a_runlist_reload,
-		.set_runlist_interleave = gk20a_fifo_set_runlist_interleave,
-		.eng_runlist_base_size = gk20a_fifo_runlist_base_size,
-		.runlist_entry_size = gk20a_fifo_runlist_entry_size,
-		.get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
-		.get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
-		.runlist_hw_submit = gk20a_fifo_runlist_hw_submit,
-		.runlist_wait_pending = gk20a_fifo_runlist_wait_pending,
-		.runlist_write_state = gk20a_fifo_runlist_write_state,
+		.set_interleave = gk20a_runlist_set_interleave,
+		.count_max = gk20a_runlist_count_max,
+		.entry_size = gk20a_runlist_entry_size,
+		.get_tsg_entry = gk20a_runlist_get_tsg_entry,
+		.get_ch_entry = gk20a_runlist_get_ch_entry,
+		.hw_submit = gk20a_runlist_hw_submit,
+		.wait_pending = gk20a_runlist_wait_pending,
+		.write_state = gk20a_runlist_write_state,
 	},
 	.channel = {
 		.bind = gm20b_channel_bind,
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index d09148e33..261847769 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -789,14 +789,14 @@ static const struct gpu_ops gv100_ops = {
 	.runlist = {
 		.update_for_channel = gk20a_runlist_update_for_channel,
 		.reload = gk20a_runlist_reload,
-		.set_runlist_interleave = gk20a_fifo_set_runlist_interleave,
-		.eng_runlist_base_size = gv100_fifo_runlist_base_size,
-		.runlist_entry_size = gv11b_fifo_runlist_entry_size,
-		.get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry,
-		.get_ch_runlist_entry = gv11b_get_ch_runlist_entry,
-		.runlist_hw_submit = gk20a_fifo_runlist_hw_submit,
-		.runlist_wait_pending = gk20a_fifo_runlist_wait_pending,
-		.runlist_write_state = gk20a_fifo_runlist_write_state,
+		.set_interleave = gk20a_runlist_set_interleave,
+		.count_max = gv100_runlist_count_max,
+		.entry_size = gv11b_runlist_entry_size,
+		.get_tsg_entry = gv11b_runlist_get_tsg_entry,
+		.get_ch_entry = gv11b_runlist_get_ch_entry,
+		.hw_submit = gk20a_runlist_hw_submit,
+		.wait_pending = gk20a_runlist_wait_pending,
+		.write_state = gk20a_runlist_write_state,
 	},
 	.channel = {
 		.bind = gm20b_channel_bind,
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index aabcbdaa9..33063a814 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -744,18 +744,18 @@ static const struct gpu_ops gv11b_ops = {
 			read_engine_status_info_gv100,
 	},
 	.runlist = {
-		.reschedule_runlist = gv11b_fifo_reschedule_runlist,
+		.reschedule = gv11b_runlist_reschedule,
 		.reschedule_preempt_next_locked = gk20a_fifo_reschedule_preempt_next,
 		.update_for_channel = gk20a_runlist_update_for_channel,
 		.reload = gk20a_runlist_reload,
-		.set_runlist_interleave = gk20a_fifo_set_runlist_interleave,
-		.eng_runlist_base_size = gv11b_fifo_runlist_base_size,
-		.runlist_entry_size = gv11b_fifo_runlist_entry_size,
-		.get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry,
-		.get_ch_runlist_entry = gv11b_get_ch_runlist_entry,
-		.runlist_hw_submit = gk20a_fifo_runlist_hw_submit,
-		.runlist_wait_pending = gk20a_fifo_runlist_wait_pending,
-		.runlist_write_state = gk20a_fifo_runlist_write_state,
+		.set_interleave = gk20a_runlist_set_interleave,
+		.count_max = gv11b_runlist_count_max,
+		.entry_size = gv11b_runlist_entry_size,
+		.get_tsg_entry = gv11b_runlist_get_tsg_entry,
+		.get_ch_entry = gv11b_runlist_get_ch_entry,
+		.hw_submit = gk20a_runlist_hw_submit,
+		.wait_pending = gk20a_runlist_wait_pending,
+		.write_state = gk20a_runlist_write_state,
 	},
 	.channel = {
 		.bind = gm20b_channel_bind,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index ea261ce7a..90a03142a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -854,8 +854,7 @@ struct gpu_ops {
 		} err_ops;
 	} fifo;
 	struct {
-		int (*reschedule_runlist)(struct channel_gk20a *ch,
-				bool preempt_next);
+		int (*reschedule)(struct channel_gk20a *ch, bool preempt_next);
 		int (*reschedule_preempt_next_locked)(struct channel_gk20a *ch,
 				bool wait_preempt);
 		int (*update_for_channel)(struct gk20a *g, u32 runlist_id,
@@ -863,19 +862,16 @@ struct gpu_ops {
 				bool wait_for_finish);
 		int (*reload)(struct gk20a *g, u32 runlist_id,
 				bool add, bool wait_for_finish);
-		int (*set_runlist_interleave)(struct gk20a *g, u32 id,
-					u32 runlist_id,
-					u32 new_level);
-		u32 (*eng_runlist_base_size)(void);
-		u32 (*runlist_entry_size)(void);
-		void (*get_tsg_runlist_entry)(struct tsg_gk20a *tsg,
-					u32 *runlist);
-		void (*get_ch_runlist_entry)(struct channel_gk20a *ch,
-					u32 *runlist);
-		void (*runlist_hw_submit)(struct gk20a *g, u32 runlist_id,
+		int (*set_interleave)(struct gk20a *g, u32 id,
+					u32 runlist_id, u32 new_level);
+		u32 (*count_max)(void);
+		u32 (*entry_size)(void);
+		void (*get_tsg_entry)(struct tsg_gk20a *tsg, u32 *runlist);
+		void (*get_ch_entry)(struct channel_gk20a *ch, u32 *runlist);
+		void (*hw_submit)(struct gk20a *g, u32 runlist_id,
 			u32 count, u32 buffer_index);
-		int (*runlist_wait_pending)(struct gk20a *g, u32 runlist_id);
-		void (*runlist_write_state)(struct gk20a *g, u32 runlists_mask,
+		int (*wait_pending)(struct gk20a *g, u32 runlist_id);
+		void (*write_state)(struct gk20a *g, u32 runlists_mask,
 				u32 runlist_state);
 	} runlist;
 
diff --git a/drivers/gpu/nvgpu/libnvgpu-drv.export b/drivers/gpu/nvgpu/libnvgpu-drv.export
index 6c3634276..922b495d0 100644
--- a/drivers/gpu/nvgpu/libnvgpu-drv.export
+++ b/drivers/gpu/nvgpu/libnvgpu-drv.export
@@ -26,8 +26,8 @@ find_first_zero_bit
 find_next_bit
 gk20a_alloc_inst_block
 gk20a_bus_set_bar0_window
-gk20a_get_ch_runlist_entry
-gk20a_get_tsg_runlist_entry
+gk20a_runlist_get_ch_entry
+gk20a_runlist_get_tsg_entry
 gk20a_locked_gmmu_map
 gk20a_locked_gmmu_unmap
 gm20b_fb_tlb_invalidate
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_channel.c b/drivers/gpu/nvgpu/os/linux/ioctl_channel.c
index e24e0ddb3..2f34b8ad3 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_channel.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_channel.c
@@ -1366,7 +1366,7 @@ long gk20a_channel_ioctl(struct file *filp,
 			err = -EPERM;
 			break;
 		}
-		if (!ch->g->ops.runlist.reschedule_runlist) {
+		if (!ch->g->ops.runlist.reschedule) {
 			err = -ENOSYS;
 			break;
 		}
@@ -1377,7 +1377,7 @@ long gk20a_channel_ioctl(struct file *filp,
 				__func__, cmd);
 			break;
 		}
-		err = ch->g->ops.runlist.reschedule_runlist(ch,
+		err = ch->g->ops.runlist.reschedule(ch,
 			NVGPU_RESCHEDULE_RUNLIST_PREEMPT_NEXT &
 			((struct nvgpu_reschedule_runlist_args *)buf)->flags);
 		gk20a_idle(ch->g);
diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c
index db3d90e7b..b883cb99a 100644
--- a/drivers/gpu/nvgpu/tu104/hal_tu104.c
+++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c
@@ -820,14 +820,14 @@ static const struct gpu_ops tu104_ops = {
 	.runlist = {
 		.update_for_channel = gk20a_runlist_update_for_channel,
 		.reload = gk20a_runlist_reload,
-		.set_runlist_interleave = gk20a_fifo_set_runlist_interleave,
-		.eng_runlist_base_size = tu104_fifo_runlist_base_size,
-		.runlist_entry_size = tu104_fifo_runlist_entry_size,
-		.get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry,
-		.get_ch_runlist_entry = gv11b_get_ch_runlist_entry,
-		.runlist_hw_submit = tu104_fifo_runlist_hw_submit,
-		.runlist_wait_pending = tu104_fifo_runlist_wait_pending,
-		.runlist_write_state = gk20a_fifo_runlist_write_state,
+		.set_interleave = gk20a_runlist_set_interleave,
+		.count_max = tu104_runlist_count_max,
+		.entry_size = tu104_runlist_entry_size,
+		.get_tsg_entry = gv11b_runlist_get_tsg_entry,
+		.get_ch_entry = gv11b_runlist_get_ch_entry,
+		.hw_submit = tu104_runlist_hw_submit,
+		.wait_pending = tu104_runlist_wait_pending,
+		.write_state = gk20a_runlist_write_state,
 	},
 	.channel = {
 		.bind = gm20b_channel_bind,
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index 1020c0db4..5835548fc 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -618,7 +618,7 @@ int vgpu_fifo_wait_engine_idle(struct gk20a *g)
 	return 0;
 }
 
-int vgpu_fifo_set_runlist_interleave(struct gk20a *g,
+int vgpu_runlist_set_interleave(struct gk20a *g,
 					u32 id,
 					u32 runlist_id,
 					u32 new_level)
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h
index a6ac03a2a..c40f5f445 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h
@@ -49,7 +49,7 @@ int vgpu_runlist_update_for_channel(struct gk20a *g, u32 runlist_id,
 int vgpu_runlist_reload(struct gk20a *g, u32 runlist_id,
 			      bool add, bool wait_for_finish);
 int vgpu_fifo_wait_engine_idle(struct gk20a *g);
-int vgpu_fifo_set_runlist_interleave(struct gk20a *g,
+int vgpu_runlist_set_interleave(struct gk20a *g,
 					u32 id,
 					u32 runlist_id,
 					u32 new_level);
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index c11a45be4..b4481c870 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -425,16 +425,16 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.read_engine_status_info = NULL,
 	},
 	.runlist = {
-		.reschedule_runlist = NULL,
+		.reschedule = NULL,
 		.update_for_channel = vgpu_runlist_update_for_channel,
 		.reload = vgpu_runlist_reload,
-		.set_runlist_interleave = vgpu_fifo_set_runlist_interleave,
-		.eng_runlist_base_size = gk20a_fifo_runlist_base_size,
-		.runlist_entry_size = NULL,
-		.get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
-		.get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
-		.runlist_hw_submit = NULL,
-		.runlist_wait_pending = NULL,
+		.set_interleave = vgpu_runlist_set_interleave,
+		.count_max = gk20a_runlist_count_max,
+		.entry_size = NULL,
+		.get_tsg_entry = gk20a_runlist_get_tsg_entry,
+		.get_ch_entry = gk20a_runlist_get_ch_entry,
+		.hw_submit = NULL,
+		.wait_pending = NULL,
 	},
 	.channel = {
 		.bind = vgpu_channel_bind,
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
index f897f66ea..cd1b0e0c0 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -501,16 +501,16 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.read_engine_status_info = NULL,
 	},
 	.runlist = {
-		.reschedule_runlist = NULL,
+		.reschedule = NULL,
 		.update_for_channel = vgpu_runlist_update_for_channel,
 		.reload = vgpu_runlist_reload,
-		.set_runlist_interleave = vgpu_fifo_set_runlist_interleave,
-		.eng_runlist_base_size = gv11b_fifo_runlist_base_size,
-		.runlist_entry_size = NULL,
-		.get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry,
-		.get_ch_runlist_entry = gv11b_get_ch_runlist_entry,
-		.runlist_hw_submit = NULL,
-		.runlist_wait_pending = NULL,
+		.set_interleave = vgpu_runlist_set_interleave,
+		.count_max = gv11b_runlist_count_max,
+		.entry_size = NULL,
+		.get_tsg_entry = gv11b_runlist_get_tsg_entry,
+		.get_ch_entry = gv11b_runlist_get_ch_entry,
+		.hw_submit = NULL,
+		.wait_pending = NULL,
 	},
 	.channel = {
 		.bind = vgpu_channel_bind,
diff --git a/userspace/units/fifo/runlist/nvgpu-runlist.c b/userspace/units/fifo/runlist/nvgpu-runlist.c
index d81983882..386c09c2c 100644
--- a/userspace/units/fifo/runlist/nvgpu-runlist.c
+++ b/userspace/units/fifo/runlist/nvgpu-runlist.c
@@ -60,8 +60,8 @@ static void setup_fifo(struct gk20a *g, unsigned long *tsg_map,
 	 * entries are enough. The logic is same across chips.
 	 */
 	f->runlist_entry_size = 2 * sizeof(u32);
-	g->ops.runlist.get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry;
-	g->ops.runlist.get_ch_runlist_entry = gk20a_get_ch_runlist_entry;
+	g->ops.runlist.get_tsg_entry = gk20a_runlist_get_tsg_entry;
+	g->ops.runlist.get_ch_entry = gk20a_runlist_get_ch_entry;
 
 	g->runlist_interleave = interleave;