From 943eb77b201fe42c2894e4fb4737338c87c57d2e Mon Sep 17 00:00:00 2001 From: Divya Date: Thu, 18 May 2023 17:01:23 +0000 Subject: [PATCH] gpu: nvgpu: add pmu HALs Add following PMU Hals: - get_pmu_msgq_head - set_pmu_msgq_head - set_pmu_new_instblk JIRA NVGPU-9758 Change-Id: Iba1e37a299309e0e31970a8fbdf248d662bd759b Signed-off-by: Divya Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2906872 Reviewed-by: svcacv Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: Rajesh Devaraj Reviewed-by: Mahantesh Kumbar GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/hal/init/hal_ga100.c | 3 +++ drivers/gpu/nvgpu/hal/init/hal_ga10b.c | 4 ++++ drivers/gpu/nvgpu/hal/init/hal_gm20b.c | 3 +++ drivers/gpu/nvgpu/hal/init/hal_gv11b.c | 3 +++ drivers/gpu/nvgpu/hal/init/hal_tu104.c | 3 +++ drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c | 2 +- drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c | 7 +++---- drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.h | 3 +++ drivers/gpu/nvgpu/hal/pmu/pmu_gk20a_fusa.c | 15 +++++++++++++++ drivers/gpu/nvgpu/hal/pmu/pmu_gm20b.c | 2 +- drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.c | 4 ++-- drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c | 2 +- drivers/gpu/nvgpu/hal/pmu/pmu_tu104.c | 4 ++-- drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h | 3 +++ 14 files changed, 47 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c index 0b467ee67..fad7a1ab6 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c @@ -1377,6 +1377,9 @@ static const struct gops_pmu ga100_ops_pmu = { .set_bar0_fecs_error = gk20a_pmu_set_bar0_fecs_error, .get_mailbox = gk20a_pmu_get_mailbox, .get_pmu_debug = gk20a_pmu_get_pmu_debug, + .get_pmu_msgq_head = gk20a_pmu_get_pmu_msgq_head, + .set_pmu_msgq_head = gk20a_pmu_set_pmu_msgq_head, + .set_pmu_new_instblk = gk20a_pmu_set_new_instblk, .pmu_isr = gk20a_pmu_isr, .pmu_init_perfmon_counter = ga10b_pmu_init_perfmon_counter, .pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config, diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index e2e317c1d..f5b8a7a17 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -1435,6 +1435,10 @@ static const struct gops_pmu ga10b_ops_pmu = { .set_bar0_fecs_error = gk20a_pmu_set_bar0_fecs_error, .get_mailbox = gk20a_pmu_get_mailbox, .get_pmu_debug = gk20a_pmu_get_pmu_debug, + .get_pmu_msgq_head = gk20a_pmu_get_pmu_msgq_head, + .set_pmu_msgq_head = gk20a_pmu_set_pmu_msgq_head, + .set_pmu_new_instblk = gk20a_pmu_set_new_instblk, + #ifdef CONFIG_NVGPU_LS_PMU .pmu_seq_cleanup = nvgpu_pmu_seq_free_release, .get_inst_block_config = ga10b_pmu_get_inst_block_config, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index 363e663bd..98956d84a 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -882,6 +882,9 @@ static const struct gops_pmu gm20b_ops_pmu = { .set_bar0_fecs_error = gk20a_pmu_set_bar0_fecs_error, .get_mailbox = gk20a_pmu_get_mailbox, .get_pmu_debug = gk20a_pmu_get_pmu_debug, + .get_pmu_msgq_head = gk20a_pmu_get_pmu_msgq_head, + .set_pmu_msgq_head = gk20a_pmu_set_pmu_msgq_head, + .set_pmu_new_instblk = gk20a_pmu_set_new_instblk, .pmu_isr = gk20a_pmu_isr, .pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter, .pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index 05bc8e904..51eb42740 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -1194,6 +1194,9 @@ static const struct gops_pmu gv11b_ops_pmu = { .set_bar0_fecs_error = gk20a_pmu_set_bar0_fecs_error, .get_mailbox = gk20a_pmu_get_mailbox, .get_pmu_debug = gk20a_pmu_get_pmu_debug, + .get_pmu_msgq_head = gk20a_pmu_get_pmu_msgq_head, + .set_pmu_msgq_head = gk20a_pmu_set_pmu_msgq_head, + .set_pmu_new_instblk = gk20a_pmu_set_new_instblk, .pmu_isr = gk20a_pmu_isr, .handle_ext_irq = gv11b_pmu_handle_ext_irq, #ifdef CONFIG_NVGPU_LS_PMU diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index f7427bbcd..83e38d510 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -1257,6 +1257,9 @@ static const struct gops_pmu tu104_ops_pmu = { .set_bar0_fecs_error = gk20a_pmu_set_bar0_fecs_error, .get_mailbox = gk20a_pmu_get_mailbox, .get_pmu_debug = gk20a_pmu_get_pmu_debug, + .get_pmu_msgq_head = gk20a_pmu_get_pmu_msgq_head, + .set_pmu_msgq_head = gk20a_pmu_set_pmu_msgq_head, + .set_pmu_new_instblk = gk20a_pmu_set_new_instblk, .pmu_isr = gk20a_pmu_isr, .pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter, .pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config, diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c b/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c index f1d8aaca5..c6e274d32 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c @@ -101,7 +101,7 @@ static int ga10b_pmu_ns_falcon_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu, pwr_falcon_itfen_ctxen_enable_f()); inst_block_ptr = nvgpu_inst_block_ptr(g, &mm->pmu.inst_block); - nvgpu_writel(g, pwr_pmu_new_instblk_r(), + g->ops.pmu.set_pmu_new_instblk(g, pwr_pmu_new_instblk_ptr_f(inst_block_ptr) | pwr_pmu_new_instblk_valid_f(1) | (nvgpu_is_enabled(g, NVGPU_USE_COHERENT_SYSMEM) ? diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c index 52656983b..084134b64 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c @@ -341,10 +341,9 @@ int gk20a_pmu_queue_head(struct gk20a *g, u32 queue_id, u32 queue_index, } else { if (!set) { *head = pwr_pmu_msgq_head_val_v( - gk20a_readl(g, pwr_pmu_msgq_head_r())); + g->ops.pmu.get_pmu_msgq_head(g)); } else { - gk20a_writel(g, - pwr_pmu_msgq_head_r(), + g->ops.pmu.set_pmu_msgq_head(g, pwr_pmu_msgq_head_val_f(*head)); } } @@ -645,7 +644,7 @@ int gk20a_pmu_ns_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu, pwr_falcon_itfen_ctxen_enable_f()); tmp_addr = nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12; nvgpu_assert(u64_hi32(tmp_addr) == 0U); - gk20a_writel(g, pwr_pmu_new_instblk_r(), + g->ops.pmu.set_pmu_new_instblk(g, pwr_pmu_new_instblk_ptr_f((u32)tmp_addr) | pwr_pmu_new_instblk_valid_f(1) | pwr_pmu_new_instblk_target_sys_coh_f()); diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.h b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.h index b485b53e9..c63ac2a6a 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.h @@ -56,6 +56,9 @@ void gk20a_pmu_set_mutex_reg(struct gk20a *g, u32 i, u32 data); u32 gk20a_pmu_get_mutex_id(struct gk20a *g); u32 gk20a_pmu_get_mutex_id_release(struct gk20a *g); void gk20a_pmu_set_mutex_id_release(struct gk20a *g, u32 data); +u32 gk20a_pmu_get_pmu_msgq_head(struct gk20a *g); +void gk20a_pmu_set_pmu_msgq_head(struct gk20a *g, u32 data); +void gk20a_pmu_set_new_instblk(struct gk20a *g, u32 data); #ifdef CONFIG_NVGPU_LS_PMU void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu); diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a_fusa.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a_fusa.c index 74b3f61b0..c49abe686 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a_fusa.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a_fusa.c @@ -148,6 +148,21 @@ void gk20a_pmu_set_mutex_id_release(struct gk20a *g, u32 data) nvgpu_writel(g, pwr_pmu_mutex_id_release_r(), data); } +u32 gk20a_pmu_get_pmu_msgq_head(struct gk20a *g) +{ + return nvgpu_readl(g, pwr_pmu_msgq_head_r()); +} + +void gk20a_pmu_set_pmu_msgq_head(struct gk20a *g, u32 data) +{ + nvgpu_writel(g, pwr_pmu_msgq_head_r(), data); +} + +void gk20a_pmu_set_new_instblk(struct gk20a *g, u32 data) +{ + nvgpu_writel(g, pwr_pmu_new_instblk_r(), data); +} + void gk20a_pmu_isr(struct gk20a *g) { struct nvgpu_pmu *pmu = g->pmu; diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gm20b.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gm20b.c index d545e2972..0e76b6564 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gm20b.c @@ -207,7 +207,7 @@ void gm20b_pmu_flcn_setup_boot_config(struct gk20a *g) */ inst_block_ptr = nvgpu_inst_block_ptr(g, &mm->pmu.inst_block); - gk20a_writel(g, pwr_pmu_new_instblk_r(), + g->ops.pmu.set_pmu_new_instblk(g, pwr_pmu_new_instblk_ptr_f(inst_block_ptr) | pwr_pmu_new_instblk_valid_f(1U) | (nvgpu_is_enabled(g, NVGPU_USE_COHERENT_SYSMEM) ? diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.c index 8afa94061..921e5dc62 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -166,7 +166,7 @@ int gv11b_pmu_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu, pwr_falcon_itfen_ctxen_enable_f()); inst_block_ptr = nvgpu_inst_block_ptr(g, &mm->pmu.inst_block); - nvgpu_writel(g, pwr_pmu_new_instblk_r(), + g->ops.pmu.set_pmu_new_instblk(g, pwr_pmu_new_instblk_ptr_f(inst_block_ptr) | pwr_pmu_new_instblk_valid_f(1) | (nvgpu_is_enabled(g, NVGPU_USE_COHERENT_SYSMEM) ? diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c index ea3b01369..e010cbf6b 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c @@ -223,7 +223,7 @@ void gv11b_pmu_flcn_setup_boot_config(struct gk20a *g) */ inst_block_ptr = nvgpu_inst_block_ptr(g, &mm->pmu.inst_block); - nvgpu_writel(g, pwr_pmu_new_instblk_r(), + g->ops.pmu.set_pmu_new_instblk(g, pwr_pmu_new_instblk_ptr_f(inst_block_ptr) | pwr_pmu_new_instblk_valid_f(1U) | (nvgpu_is_enabled(g, NVGPU_USE_COHERENT_SYSMEM) ? diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_tu104.c b/drivers/gpu/nvgpu/hal/pmu/pmu_tu104.c index e630c9e2a..af2b7950b 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_tu104.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_tu104.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -99,7 +99,7 @@ void tu104_pmu_setup_apertures(struct gk20a *g) gk20a_readl(g, pwr_falcon_itfen_r()) | pwr_falcon_itfen_ctxen_enable_f()); inst_block_ptr = nvgpu_inst_block_ptr(g, &mm->pmu.inst_block); - gk20a_writel(g, pwr_pmu_new_instblk_r(), + g->ops.pmu.set_pmu_new_instblk(g, pwr_pmu_new_instblk_ptr_f(inst_block_ptr) | pwr_pmu_new_instblk_valid_f(1) | nvgpu_aperture_mask(g, &mm->pmu.inst_block, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h index 376f60dae..7ace8b672 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h @@ -498,6 +498,9 @@ struct gops_pmu { u32 (*pmu_get_mutex_id)(struct gk20a *g); u32 (*pmu_get_mutex_id_release)(struct gk20a *g); void (*pmu_set_mutex_id_release)(struct gk20a *g, u32 data); + u32 (*get_pmu_msgq_head)(struct gk20a *g); + void (*set_pmu_msgq_head)(struct gk20a *g, u32 data); + void (*set_pmu_new_instblk)(struct gk20a *g, u32 data); #ifdef CONFIG_NVGPU_LS_PMU u32 (*get_inst_block_config)(struct gk20a *g);