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gpu: nvgpu: flags to query specific clk domains
Added NVGPU_GPU_CLK_FLAG_SPECIFIC_DOMAINS to indicate that a request (get clock info/range) applies only to domains specified in clock entries. If flag is not set, request returns all clock domains. Jira DNVGPU-125 Change-Id: I11bffbdf491ebffa7f47bd327037b0b8cfcbde31 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1227998 (cherry picked from commit 7613dd30e120a82d342da402b4e0b070512dddad) Reviewed-on: http://git-master/r/1243108 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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@@ -524,20 +524,24 @@ struct nvgpu_gpu_clk_range {
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__u32 max_mhz;
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};
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/* Request on specific clock domains */
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#define NVGPU_GPU_CLK_FLAG_SPECIFIC_DOMAINS (1UL << 0)
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struct nvgpu_gpu_clk_range_args {
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/* Flags (not currently used) */
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/* Flags. If NVGPU_GPU_CLK_FLAG_SPECIFIC_DOMAINS the request will
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apply only to domains specified in clock entries. In this case
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caller must set clock domain in each entry. Otherwise, the
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ioctl will return all clock domains.
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*/
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__u32 flags;
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/* in/out: max number of entries in clk_range_entries buffer. If zero,
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NVGPU_GPU_IOCTL_CLK_GET_RANGE will return 0 and max_entries will be
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set to the max number of clock domains. If there are more entries
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than max_entries, then ioctl will return -EINVAL.
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*/
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__u16 max_entries;
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__u16 pad0;
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/* out: number of nvgpu_gpu_clk_range entries contained in
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clk_range_entries */
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/* in/out: Number of entries in clk_range_entries buffer. If zero,
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NVGPU_GPU_IOCTL_CLK_GET_RANGE will return 0 and
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num_entries will be set to number of clock domains.
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*/
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__u16 num_entries;
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/* in: Pointer to clock range entries in the caller's address space.
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@@ -606,14 +610,18 @@ struct nvgpu_gpu_clk_info {
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struct nvgpu_gpu_clk_get_info_args {
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/* in: Flags (not currently used). */
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/* Flags. If NVGPU_GPU_CLK_FLAG_SPECIFIC_DOMAINS the request will
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apply only to domains specified in clock entries. In this case
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caller must set clock domain in each entry. Otherwise, the
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ioctl will return all clock domains.
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*/
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__u32 flags;
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__u16 pad0;
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/* in/out: Number of clock info entries contained in clk_info_entries.
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If zero, NVGPU_GPU_IOCTL_CLK_GET_INFO will return 0 and
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max_entries will be set to number of clock domains. Also,
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num_entries will be set to number of clock domains. Also,
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last_req_nr will be updated, which allows checking if a given
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request has completed. If there are more entries than max_entries,
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then ioctl will return -EINVAL.
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@@ -623,8 +631,9 @@ struct nvgpu_gpu_clk_get_info_args {
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/* in: Pointer to nvgpu_gpu_clk_info entries in the caller's address
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space. Buffer size must be at least:
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num_entries * sizeof(struct nvgpu_gpu_clk_info)
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For each entry, the clk_domain to be queried should be set. Note
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that clk_info_entries passed to an NVGPU_GPU_IOCTL_CLK_SET_INFO,
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If NVGPU_GPU_CLK_FLAG_SPECIFIC_DOMAINS is set, caller should set
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clk_domain to be queried in each entry. With this flag,
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clk_info_entries passed to an NVGPU_GPU_IOCTL_CLK_SET_INFO,
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can be re-used on completion for a NVGPU_GPU_IOCTL_CLK_GET_INFO.
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This allows checking actual_mhz.
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*/
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