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gpu: nvgpu: gk20a: fix MISRA 10.4 Violations [1/2]
MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fixes violation where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: Ifb8cb992a5cb9b04440f162918a8ed2ae17ec928 Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1822587 GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -274,7 +274,7 @@ int gk20a_finalize_poweron(struct gk20a *g)
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* via fuse. We will not support TPC-PG in those cases.
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*/
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if (g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0) != 0x0) {
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if (g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0) != 0x0U) {
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g->can_tpc_powergate = false;
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g->tpc_pg_mask = 0x0;
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}
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@@ -404,7 +404,7 @@ int gk20a_finalize_poweron(struct gk20a *g)
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g->ops.xve.available_speeds(g, &speed);
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/* Set to max speed */
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speed = 1 << (fls(speed) - 1);
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speed = BIT32(fls(speed) - 1U);
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err = g->ops.xve.set_speed(g, speed);
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if (err != 0) {
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nvgpu_err(g, "Failed to set PCIe bus speed!");
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