From 9508cc6f42f19a52d262848514875f3a0faab4f8 Mon Sep 17 00:00:00 2001 From: rmylavarapu Date: Tue, 18 Feb 2020 18:25:26 +0530 Subject: [PATCH] gpu: nvgpu: sbr: Load and execute PUB Implmented functions to load and execute PUB which is the safety POR. PUB has following functionality: 1) Lower PLM 2) Reset PMU 3) FBPA register access to devtools Secure Boot and Runtime (SBR) microcode comprises of single PLM Update Binary (PUB) which will execute on SEC2 Engine Falcon. NVGPU shall load and execute PUB and wait for falcon halt. On successful halt NVGPU shall proceed with ns ucode loading on respective falcons. NVGPU-4549 Change-Id: I8ea897a026bbe2b1714823aba51bfa51864dd68a Signed-off-by: rmylavarapu Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292330 Tested-by: mobile promotions Reviewed-by: mobile promotions --- arch/nvgpu-common.yaml | 8 ++ drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/Makefile.sources | 1 + drivers/gpu/nvgpu/common/mm/mm.c | 3 +- drivers/gpu/nvgpu/common/sbr/sbr.c | 132 ++++++++++++++++++++++++ drivers/gpu/nvgpu/common/sbr/sbr.h | 50 +++++++++ drivers/gpu/nvgpu/hal/init/hal_tu104.c | 5 + drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 3 + drivers/gpu/nvgpu/include/nvgpu/sbr.h | 28 +++++ 9 files changed, 230 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/nvgpu/common/sbr/sbr.c create mode 100644 drivers/gpu/nvgpu/common/sbr/sbr.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/sbr.h diff --git a/arch/nvgpu-common.yaml b/arch/nvgpu-common.yaml index 800703cc1..a3f974f98 100644 --- a/arch/nvgpu-common.yaml +++ b/arch/nvgpu-common.yaml @@ -252,6 +252,14 @@ acr: common/acr/acr_sw_tu104.c, common/acr/acr_sw_tu104.h ] +sbr: + safe: yes + owner: Ramesh M + gpu: dgpu + sources: [ common/sbr/sbr.c, + common/sbr/sbr.h, + include/nvgpu/sbr.h ] + engine_queues: owner: Sagar K children: diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 1d47bd3fe..2cdf3db54 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -139,6 +139,7 @@ nvgpu-y += \ common/acr/acr_sw_gp10b.o \ common/acr/acr_sw_gv11b.o \ common/acr/acr_sw_tu104.o \ + common/sbr/sbr.o \ common/pmu/super_surface/super_surface.o \ common/pmu/lsfm/lsfm.o \ common/pmu/lsfm/lsfm_sw_gm20b.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 96cd3f3e0..024c29e88 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -579,6 +579,7 @@ srcs += common/sec2/sec2.c \ common/mm/vidmem.c \ common/pramin.c \ common/ce/ce_app.c \ + common/sbr/sbr.c \ hal/mm/mm_gv100.c \ hal/mm/mm_tu104.c \ hal/mc/mc_gv100.c \ diff --git a/drivers/gpu/nvgpu/common/mm/mm.c b/drivers/gpu/nvgpu/common/mm/mm.c index 10018ca43..3c77ddfd1 100644 --- a/drivers/gpu/nvgpu/common/mm/mm.c +++ b/drivers/gpu/nvgpu/common/mm/mm.c @@ -543,7 +543,8 @@ static int nvgpu_init_mm_setup_sw(struct gk20a *g) * allocated before all other buffers */ - if (!nvgpu_is_enabled(g, NVGPU_MM_UNIFIED_MEMORY)) { + if (!nvgpu_is_enabled(g, NVGPU_MM_UNIFIED_MEMORY) && + nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { err = nvgpu_acr_alloc_blob_prerequisite(g, g->acr, 0); if (err != 0) { return err; diff --git a/drivers/gpu/nvgpu/common/sbr/sbr.c b/drivers/gpu/nvgpu/common/sbr/sbr.c new file mode 100644 index 000000000..b43af6c93 --- /dev/null +++ b/drivers/gpu/nvgpu/common/sbr/sbr.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include + +#include "sbr.h" + +static void pub_ucode_patch_sig(struct gk20a *g, + unsigned int *p_img, unsigned int *p_prod_sig, + unsigned int *p_dbg_sig, unsigned int *p_patch_loc, + unsigned int *p_patch_ind, u32 sig_size) +{ + unsigned int i, j, *p_sig; + nvgpu_info(g, " "); + + if (!g->ops.pmu.is_debug_mode_enabled(g)) { + p_sig = p_prod_sig; + nvgpu_info(g, "PRODUCTION MODE\n"); + } else { + p_sig = p_dbg_sig; + nvgpu_info(g, "DEBUG MODE\n"); + } + + /* Patching logic:*/ + sig_size = sig_size / 4U; + for (i = 0U; i < (sizeof(*p_patch_loc)>>2U); i++) { + for (j = 0U; j < sig_size; j++) { + p_img[nvgpu_safe_add_u32((p_patch_loc[i]>>2U), j)] = + p_sig[nvgpu_safe_add_u32((p_patch_ind[i]<<2U), j)]; + } + } +} + +int nvgpu_sbr_pub_load_and_execute(struct gk20a *g) +{ + struct nvgpu_firmware *pub_fw = NULL; + struct pub_bin_hdr *hs_bin_hdr = NULL; + struct pub_fw_header *fw_hdr = NULL; + u32 *ucode_header = NULL; + u32 *ucode = NULL; + u32 data = 0; + int err = 0; + + nvgpu_log_fn(g, " "); + + if (!g->ops.pmu.is_debug_mode_enabled(g)) { + pub_fw = nvgpu_request_firmware(g, PUB_PROD_BIN, + NVGPU_REQUEST_FIRMWARE_NO_SOC); + } else { + pub_fw = nvgpu_request_firmware(g, PUB_DBG_BIN, + NVGPU_REQUEST_FIRMWARE_NO_SOC); + } + + if (pub_fw == NULL) { + nvgpu_err(g, "pub ucode get fail"); + err = -ENOENT; + goto exit; + } + + hs_bin_hdr = (struct pub_bin_hdr *)(void *)pub_fw->data; + fw_hdr = (struct pub_fw_header *)(void *)(pub_fw->data + + hs_bin_hdr->header_offset); + ucode_header = (u32 *)(void *)(pub_fw->data + + fw_hdr->hdr_offset); + ucode = (u32 *)(void *)(pub_fw->data + hs_bin_hdr->data_offset); + + /* Patch Ucode signatures */ + pub_ucode_patch_sig(g, ucode, + (u32 *)(void *)(pub_fw->data + fw_hdr->sig_prod_offset), + (u32 *)(void *)(pub_fw->data + fw_hdr->sig_dbg_offset), + (u32 *)(void *)(pub_fw->data + fw_hdr->patch_loc), + (u32 *)(void *)(pub_fw->data + fw_hdr->patch_sig), + fw_hdr->sig_dbg_size); + + err = nvgpu_falcon_hs_ucode_load_bootstrap(&g->sec2.flcn, ucode, + ucode_header); + if (err != 0) { + nvgpu_err(g, "pub ucode load & bootstrap failed"); + goto exit; + } + + if (nvgpu_falcon_wait_for_halt(&g->sec2.flcn, PUB_TIMEOUT) != 0) { + nvgpu_err(g, "pub ucode boot timed out"); + err = -ETIMEDOUT; + goto exit; + } + + data = nvgpu_falcon_mailbox_read(&g->sec2.flcn, FALCON_MAILBOX_0); + if (data != 0U) { + nvgpu_err(g, "pub ucode boot failed, err %x", data); + err = -EAGAIN; + goto exit; + } + +exit: +#ifdef CONFIG_NVGPU_FALCON_DEBUG + if (err != 0) { + nvgpu_falcon_dump_stats(&g->sec2.flcn); + } +#endif + + if (pub_fw != NULL) { + nvgpu_release_firmware(g, pub_fw); + } + + nvgpu_log_fn(g, "pub loaded & executed with status %d", err); + return err; +} + diff --git a/drivers/gpu/nvgpu/common/sbr/sbr.h b/drivers/gpu/nvgpu/common/sbr/sbr.h new file mode 100644 index 000000000..a4913115b --- /dev/null +++ b/drivers/gpu/nvgpu/common/sbr/sbr.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_COMMON_SBR_H_ +#define NVGPU_COMMON_SBR_H_ + +#define PUB_PROD_BIN "pub.bin" +#define PUB_DBG_BIN "pub_dbg.bin" +#define PUB_TIMEOUT 100U /* msec */ + +struct pub_bin_hdr { + u32 bin_magic; + u32 bin_ver; + u32 bin_size; + u32 header_offset; + u32 data_offset; + u32 data_size; +}; + +struct pub_fw_header { + u32 sig_dbg_offset; + u32 sig_dbg_size; + u32 sig_prod_offset; + u32 sig_prod_size; + u32 patch_loc; + u32 patch_sig; + u32 hdr_offset; + u32 hdr_size; +}; + +#endif /* NVGPU_COMMON_SBR_H_ */ diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 6b2a7bbe8..cd7001061 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -219,6 +219,7 @@ #include #include #include +#include #include @@ -251,6 +252,9 @@ static const struct gpu_ops tu104_ops = { .acr_init = nvgpu_acr_init, .acr_construct_execute = nvgpu_acr_construct_execute, }, + .sbr = { + .sbr_pub_load_and_execute = nvgpu_sbr_pub_load_and_execute, + }, .bios = { #ifdef CONFIG_NVGPU_DGPU .bios_sw_init = nvgpu_bios_sw_init, @@ -1580,6 +1584,7 @@ int tu104_init_hal(struct gk20a *g) gops->bios = tu104_ops.bios; gops->acr = tu104_ops.acr; + gops->sbr = tu104_ops.sbr; gops->ecc = tu104_ops.ecc; gops->fbp = tu104_ops.fbp; gops->ltc = tu104_ops.ltc; diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index b458f6b82..3f3706d9d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -268,6 +268,9 @@ struct gpu_ops { int (*acr_init)(struct gk20a *g); int (*acr_construct_execute)(struct gk20a *g); } acr; + struct { + int (*sbr_pub_load_and_execute)(struct gk20a *g); + } sbr; struct gops_ecc ecc; struct gops_ltc ltc; diff --git a/drivers/gpu/nvgpu/include/nvgpu/sbr.h b/drivers/gpu/nvgpu/include/nvgpu/sbr.h new file mode 100644 index 000000000..b80966346 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/sbr.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_INCLUDE_SBR_H_ +#define NVGPU_INCLUDE_SBR_H_ + +int nvgpu_sbr_pub_load_and_execute(struct gk20a *g); + +#endif /* NVGPU_INCLUDE_SBR_H_ */