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gpu: nvgpu: Use GPU's own fuse registers

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Read fuse values from GPU's own fuse registers instead of Tegra fuse
registers whenever possible. This reduces the number of dependencies
to Linux fuse code.

Some fuses do not have a corresponding register in GPU, so they're
left as is.

Change-Id: Id9f2f4da897f3e20b20c300a67f705e3fa5ba35a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1318278
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
This commit is contained in:
Terje Bergstrom
2017-03-09 14:10:00 -08:00
committed by mobile promotions
parent 16ee09bb59
commit 95ef0315b9
4 changed files with 12 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -14,8 +14,6 @@
*/
#include <linux/types.h>
#include <linux/version.h>
#include <soc/tegra/fuse.h>
#include "gk20a/gk20a.h"
#include "gk20a/dbg_gpu_gk20a.h"
@@ -39,10 +37,7 @@
#include "therm_gm20b.h"
#include <nvgpu/hw/gm20b/hw_proj_gm20b.h>
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
#define FUSE_OPT_PRIV_SEC_DIS_0 0x264
#endif
#include <nvgpu/hw/gm20b/hw_fuse_gm20b.h>
#define PRIV_SECURITY_DISABLE 0x01
@@ -197,8 +192,8 @@ int gm20b_init_hal(struct gk20a *g)
if (platform->is_fmodel) {
gops->privsecurity = 1;
} else {
tegra_fuse_readl(FUSE_OPT_PRIV_SEC_DIS_0, &val);
if (val & PRIV_SECURITY_DISABLE) {
val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
if (!val) {
gk20a_dbg_info("priv security is disabled in HW");
gops->privsecurity = 0;
} else {
@@ -210,8 +205,8 @@ int gm20b_init_hal(struct gk20a *g)
gk20a_dbg_info("running ASIM with PRIV security disabled");
gops->privsecurity = 0;
} else {
tegra_fuse_readl(FUSE_OPT_PRIV_SEC_DIS_0, &val);
if (val & PRIV_SECURITY_DISABLE) {
val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
if (!val) {
gops->privsecurity = 0;
} else {
gk20a_dbg_info("priv security is not supported but enabled");

7
drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h
View File

@@ -16,13 +16,6 @@
#ifndef _GP10B_SYSFS_H_
#define _GP10B_SYSFS_H_
#include <linux/version.h>
/*ECC Fuse*/
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
#define FUSE_OPT_ECC_EN 0x358
#endif
void gp10b_create_sysfs(struct device *dev);
void gp10b_remove_sysfs(struct device *dev);

3
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -36,6 +36,7 @@
#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
#include <nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h>
#include <nvgpu/hw/gp10b/hw_mc_gp10b.h>
#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
#define NVGPU_GFXP_WFI_TIMEOUT_US 100LL
@@ -1948,7 +1949,7 @@ static u32 get_ecc_override_val(struct gk20a *g)
{
u32 val;
tegra_fuse_readl(FUSE_OPT_ECC_EN, &val);
val = gk20a_readl(g, fuse_opt_ecc_en_r());
if (val)
return gk20a_readl(g, gr_fecs_feature_override_ecc_r());

15
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -17,7 +17,6 @@
#include <linux/printk.h>
#include <linux/version.h>
#include <linux/types.h>
#include <soc/tegra/fuse.h>
#include "gk20a/gk20a.h"
#include "gk20a/dbg_gpu_gk20a.h"
@@ -46,11 +45,7 @@
#include "gp10b.h"
#include <nvgpu/hw/gp10b/hw_proj_gp10b.h>
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
#define FUSE_OPT_PRIV_SEC_EN_0 0x264
#endif
#define PRIV_SECURITY_ENABLED 0x01
#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
static struct gpu_ops gp10b_ops = {
.clock_gating = {
@@ -205,8 +200,8 @@ int gp10b_init_hal(struct gk20a *g)
gops->privsecurity = 0;
gops->securegpccs = 0;
} else {
tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0, &val);
if (val & PRIV_SECURITY_ENABLED) {
val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
if (val) {
gops->privsecurity = 1;
gops->securegpccs =1;
} else {
@@ -221,8 +216,8 @@ int gp10b_init_hal(struct gk20a *g)
gops->privsecurity = 0;
gops->securegpccs = 0;
} else {
tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0, &val);
if (val & PRIV_SECURITY_ENABLED) {
val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
if (val) {
gk20a_dbg_info("priv security is not supported but enabled");
gops->privsecurity = 1;
gops->securegpccs =1;