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gpu: nvgpu: pass gr_ctx to alloc_channel_patch_ctx
Simplify object ownership by passing the gr_ctx around directly instead of reading from tsg via a channel; the caller holds the gr_ctx already. Also pass the channel vm instead of the whole channel. Jira NVGPU-1149 Change-Id: Id9d65841f09459e7acfc8c4ce4c6de7db054dbd8 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1925427 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -78,9 +78,6 @@ static void gr_gk20a_free_channel_pm_ctx(struct gk20a *g,
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struct vm_gk20a *vm,
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struct nvgpu_gr_ctx *gr_ctx);
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/* channel patch ctx buffer */
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static int gr_gk20a_alloc_channel_patch_ctx(struct gk20a *g,
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struct channel_gk20a *c);
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static void gr_gk20a_free_channel_patch_ctx(struct gk20a *g,
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struct vm_gk20a *vm,
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struct nvgpu_gr_ctx *gr_ctx);
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@@ -2810,22 +2807,16 @@ u32 gr_gk20a_get_patch_slots(struct gk20a *g)
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}
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static int gr_gk20a_alloc_channel_patch_ctx(struct gk20a *g,
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struct channel_gk20a *c)
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struct vm_gk20a *ch_vm,
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struct nvgpu_gr_ctx *gr_ctx)
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{
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struct tsg_gk20a *tsg;
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struct patch_desc *patch_ctx;
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struct vm_gk20a *ch_vm = c->vm;
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u32 alloc_size;
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int err = 0;
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nvgpu_log_fn(g, " ");
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tsg = tsg_gk20a_from_ch(c);
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if (tsg == NULL) {
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return -EINVAL;
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}
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patch_ctx = &tsg->gr_ctx->patch_ctx;
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patch_ctx = &gr_ctx->patch_ctx;
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alloc_size = g->ops.gr.get_patch_slots(g) *
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PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY;
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@@ -2925,7 +2916,8 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags)
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/* allocate patch buffer */
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if (!nvgpu_mem_is_valid(&gr_ctx->patch_ctx.mem)) {
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gr_ctx->patch_ctx.data_count = 0;
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err = gr_gk20a_alloc_channel_patch_ctx(g, c);
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err = gr_gk20a_alloc_channel_patch_ctx(g, c->vm,
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gr_ctx);
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if (err != 0) {
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nvgpu_err(g,
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"fail to allocate patch buffer");
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