gpu: nvgpu: disable nvlink support in safety build

Since nvlink support is not required for initial safety release, disable
corresponding functionality.
nvgpu_mss_nvlink_init_credits defn. and call is now compiled out using
CONFIG_TEGRA_NVLINK config option.

JIRA NVGPU-3062

Change-Id: I402ed123f07f96125d640fb340957da4828d714a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119584
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-05-14 12:58:44 +05:30
committed by mobile promotions
parent b6919ce302
commit 96268cb631
8 changed files with 30 additions and 22 deletions

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@@ -51,4 +51,8 @@ NVGPU_COMMON_CFLAGS += -DCONFIG_GK20A_CTXSW_TRACE
IGPU_VIRT_SUPPORT := 1 IGPU_VIRT_SUPPORT := 1
NVGPU_COMMON_CFLAGS += -DIGPU_VIRT_SUPPORT NVGPU_COMMON_CFLAGS += -DIGPU_VIRT_SUPPORT
# Enable nvlink support for normal build.
NVGPU_NVLINK_SUPPORT := 1
NVGPU_COMMON_CFLAGS += -DCONFIG_TEGRA_NVLINK
endif endif

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@@ -37,7 +37,6 @@ srcs += os/posix/nvgpu.c \
os/posix/posix-clk_arb.c \ os/posix/posix-clk_arb.c \
os/posix/posix-channel.c \ os/posix/posix-channel.c \
os/posix/posix-tsg.c \ os/posix/posix-tsg.c \
os/posix/posix-nvlink.c \
os/posix/stubs.c \ os/posix/stubs.c \
os/posix/posix-sim.c \ os/posix/posix-sim.c \
os/posix/posix-nvhost.c \ os/posix/posix-nvhost.c \
@@ -45,6 +44,10 @@ srcs += os/posix/nvgpu.c \
os/posix/posix-dt.c \ os/posix/posix-dt.c \
os/posix/posix-vidmem.c \ os/posix/posix-vidmem.c \
os/posix/fecs_trace_posix.c os/posix/fecs_trace_posix.c
ifdef NVGPU_NVLINK_SUPPORT
srcs += os/posix/posix-nvlink.c
endif
endif endif
# POSIX sources shared between the POSIX and QNX builds. # POSIX sources shared between the POSIX and QNX builds.
@@ -95,7 +98,6 @@ srcs += common/sim/sim.c \
common/ecc.c \ common/ecc.c \
common/ce/ce.c \ common/ce/ce.c \
common/vbios/bios.c \ common/vbios/bios.c \
common/vbios/nvlink_bios.c \
common/vbios/bios_sw_gp106.c \ common/vbios/bios_sw_gp106.c \
common/vbios/bios_sw_gv100.c \ common/vbios/bios_sw_gv100.c \
common/vbios/bios_sw_tu104.c \ common/vbios/bios_sw_tu104.c \
@@ -232,15 +234,6 @@ srcs += common/sim/sim.c \
common/clk_arb/clk_arb.c \ common/clk_arb/clk_arb.c \
common/clk_arb/clk_arb_gp10b.c \ common/clk_arb/clk_arb_gp10b.c \
common/clk_arb/clk_arb_gv100.c \ common/clk_arb/clk_arb_gv100.c \
common/nvlink/probe.c \
common/nvlink/init/device_reginit.c \
common/nvlink/init/device_reginit_gv100.c \
common/nvlink/intr_and_err_handling_gv100.c \
common/nvlink/minion.c \
common/nvlink/link_mode_transitions.c \
common/nvlink/nvlink_gv100.c \
common/nvlink/nvlink_tu104.c \
common/nvlink/nvlink.c \
common/fence/fence.c \ common/fence/fence.c \
hal/mm/mm_gk20a.c \ hal/mm/mm_gk20a.c \
hal/mm/mm_gm20b.c \ hal/mm/mm_gm20b.c \
@@ -422,10 +415,6 @@ srcs += common/sim/sim.c \
hal/netlist/netlist_tu104.c \ hal/netlist/netlist_tu104.c \
hal/nvdec/nvdec_gp106.c \ hal/nvdec/nvdec_gp106.c \
hal/nvdec/nvdec_tu104.c \ hal/nvdec/nvdec_tu104.c \
hal/nvlink/minion_gv100.c \
hal/nvlink/minion_tu104.c \
hal/nvlink/link_mode_transitions_gv100.c \
hal/nvlink/link_mode_transitions_tu104.c \
hal/gsp/gsp_gv100.c \ hal/gsp/gsp_gv100.c \
hal/sec2/sec2_gp106.c \ hal/sec2/sec2_gp106.c \
hal/sec2/sec2_tu104.c \ hal/sec2/sec2_tu104.c \
@@ -510,3 +499,20 @@ srcs += common/vgpu/init/init_vgpu.c \
common/vgpu/gv11b/vgpu_tsg_gv11b.c \ common/vgpu/gv11b/vgpu_tsg_gv11b.c \
common/vgpu/gp10b/vgpu_hal_gp10b.c common/vgpu/gp10b/vgpu_hal_gp10b.c
endif endif
ifeq ($(NVGPU_NVLINK_SUPPORT), 1)
srcs += common/vbios/nvlink_bios.c \
common/nvlink/probe.c \
common/nvlink/init/device_reginit.c \
common/nvlink/init/device_reginit_gv100.c \
common/nvlink/intr_and_err_handling_gv100.c \
common/nvlink/minion.c \
common/nvlink/link_mode_transitions.c \
common/nvlink/nvlink_gv100.c \
common/nvlink/nvlink_tu104.c \
common/nvlink/nvlink.c \
hal/nvlink/minion_gv100.c \
hal/nvlink/minion_tu104.c \
hal/nvlink/link_mode_transitions_gv100.c \
hal/nvlink/link_mode_transitions_tu104.c
endif

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@@ -62,8 +62,7 @@ NV_COMPONENT_CFLAGS += \
-DCONFIG_TEGRA_ACR=1 \ -DCONFIG_TEGRA_ACR=1 \
-DCONFIG_TEGRA_GR_VIRTUALIZATION \ -DCONFIG_TEGRA_GR_VIRTUALIZATION \
-DCONFIG_GK20A_VIDMEM=1 \ -DCONFIG_GK20A_VIDMEM=1 \
-DCONFIG_PCI_MSI \ -DCONFIG_PCI_MSI
-DCONFIG_TEGRA_NVLINK
-include $(NV_COMPONENT_DIR)/Makefile.shared.configs -include $(NV_COMPONENT_DIR)/Makefile.shared.configs
NV_COMPONENT_CFLAGS += $(NVGPU_COMMON_CFLAGS) NV_COMPONENT_CFLAGS += $(NVGPU_COMMON_CFLAGS)

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@@ -53,7 +53,9 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g)
nvgpu_log(g, gpu_dbg_info, "nvlink soc credits init done by bpmp"); nvgpu_log(g, gpu_dbg_info, "nvlink soc credits init done by bpmp");
} else { } else {
#ifndef __NVGPU_POSIX__ #ifndef __NVGPU_POSIX__
#ifdef CONFIG_TEGRA_NVLINK
nvgpu_mss_nvlink_init_credits(g); nvgpu_mss_nvlink_init_credits(g);
#endif
#endif #endif
} }
} }

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@@ -251,7 +251,6 @@ int nvgpu_nvlink_minion_load_ucode(struct gk20a *g,
return err; return err;
} }
#endif /* CONFIG_TEGRA_NVLINK */
void nvgpu_mss_nvlink_init_credits(struct gk20a *g) void nvgpu_mss_nvlink_init_credits(struct gk20a *g)
{ {
@@ -287,6 +286,7 @@ void nvgpu_mss_nvlink_init_credits(struct gk20a *g)
val = readl_relaxed(soc4 + 4); val = readl_relaxed(soc4 + 4);
writel_relaxed(val, soc4 + 4); writel_relaxed(val, soc4 + 4);
} }
#endif /* CONFIG_TEGRA_NVLINK */
int nvgpu_nvlink_deinit(struct gk20a *g) int nvgpu_nvlink_deinit(struct gk20a *g)
{ {

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@@ -44,7 +44,6 @@ CONFIGS := \
-DCONFIG_GK20A_VIDMEM=1 \ -DCONFIG_GK20A_VIDMEM=1 \
-DCONFIG_PCI_MSI \ -DCONFIG_PCI_MSI \
-DCONFIG_SUPPORT_PMU_PSTATE \ -DCONFIG_SUPPORT_PMU_PSTATE \
-DCONFIG_TEGRA_NVLINK \
-DNVGPU_UNITTEST_FAULT_INJECTION_ENABLEMENT -DNVGPU_UNITTEST_FAULT_INJECTION_ENABLEMENT
# Uncomment these to enable the config. # Uncomment these to enable the config.

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@@ -124,7 +124,6 @@ NV_COMPONENT_CFLAGS += \
-DCONFIG_GK20A_VIDMEM=1 \ -DCONFIG_GK20A_VIDMEM=1 \
-DCONFIG_PCI_MSI \ -DCONFIG_PCI_MSI \
-DCONFIG_SUPPORT_PMU_PSTATE \ -DCONFIG_SUPPORT_PMU_PSTATE \
-DCONFIG_TEGRA_NVLINK \
-DNVGPU_UNITTEST_FAULT_INJECTION_ENABLEMENT -DNVGPU_UNITTEST_FAULT_INJECTION_ENABLEMENT
-include ../drivers/gpu/nvgpu/Makefile.shared.configs -include ../drivers/gpu/nvgpu/Makefile.shared.configs

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@@ -67,8 +67,7 @@ NV_COMPONENT_CFLAGS += \
-DCONFIG_ARCH_TEGRA_18x_SOC=1 \ -DCONFIG_ARCH_TEGRA_18x_SOC=1 \
-DCONFIG_GK20A_VIDMEM=1 \ -DCONFIG_GK20A_VIDMEM=1 \
-DCONFIG_PCI_MSI \ -DCONFIG_PCI_MSI \
-DCONFIG_SUPPORT_PMU_PSTATE \ -DCONFIG_SUPPORT_PMU_PSTATE
-DCONFIG_TEGRA_NVLINK
-include $(NV_SOURCE)/kernel/nvgpu/drivers/gpu/nvgpu/Makefile.shared.configs -include $(NV_SOURCE)/kernel/nvgpu/drivers/gpu/nvgpu/Makefile.shared.configs
NV_COMPONENT_CFLAGS += $(NVGPU_COMMON_CFLAGS) NV_COMPONENT_CFLAGS += $(NVGPU_COMMON_CFLAGS)