gpu: nvgpu: reset HWPM regs while binding HWPM in global mode

Add new HAL g->ops.gr.reset_hwpm_pmm_registers() to reset all HWPM regs
while binding HWPM in global mode in nvgpu_profiler_bind_hwpm()

Add below new HALs to get sys/gpc/fbp register list and count
g->ops.perf.get_hwpm_sys_perfmon_regs()
g->ops.perf.get_hwpm_gpc_perfmon_regs()
g->ops.perf.get_hwpm_fbp_perfmon_regs()

Auto generate all the HWPM regs in below arrays for gv11b/tu104
static const u32 hwpm_sys_perfmon_regs[]
static const u32 hwpm_gpc_perfmon_regs[]
static const u32 hwpm_fbp_perfmon_regs[]

Bug 2510974
Jira NVGPU-5360

Change-Id: I2ca5c04ed75c7b30ae942807bf018a24551d7ba0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2414934
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

arch/nvgpu-hal-new.yaml

@@ -738,7 +738,9 @@ perf:
   sources: [ hal/perf/perf_gm20b.c,
              hal/perf/perf_gm20b.h,
              hal/perf/perf_gv11b.c,
-             hal/perf/perf_gv11b.h ]
+             hal/perf/perf_gv11b.h,
+             hal/perf/perf_tu104.c,
+             hal/perf/perf_tu104.h ]
 
 pramin:
   safe: yes

drivers/gpu/nvgpu/Makefile

@@ -323,6 +323,7 @@ nvgpu-y += \
 	hal/init/hal_gv11b_litter.o \
 	hal/init/hal_init.o \
 	hal/perf/perf_gv11b.o \
+	hal/perf/perf_tu104.o \
 	hal/power_features/cg/gp10b_gating_reglist.o \
 	hal/power_features/cg/gv11b_gating_reglist.o \
 	hal/regops/regops_gv11b.o \

drivers/gpu/nvgpu/Makefile.sources

@@ -374,6 +374,7 @@ srcs += common/debugger.c \
 	hal/ltc/ltc_gm20b_dbg.c \
 	hal/ptimer/ptimer_gp10b.c \
 	hal/perf/perf_gv11b.c \
+	hal/perf/perf_tu104.c \
 	hal/gr/gr/gr_gk20a.c \
 	hal/gr/gr/gr_gm20b.c \
 	hal/gr/gr/gr_gp10b.c \

drivers/gpu/nvgpu/common/profiler/profiler.c

@@ -303,6 +303,9 @@ static int nvgpu_profiler_bind_hwpm(struct nvgpu_profiler_object *prof, bool str
 		if (prof->ctxsw[NVGPU_PROFILER_PM_RESOURCE_TYPE_HWPM_LEGACY]) {
 			err = g->ops.gr.update_hwpm_ctxsw_mode(g, prof->tsg, 0, mode);
 		} else {
+			if (g->ops.gr.reset_hwpm_pmm_registers != NULL) {
+				g->ops.gr.reset_hwpm_pmm_registers(g);
+			}
 			g->ops.gr.init_hwpm_pmm_register(g);
 		}
 	} else {

drivers/gpu/nvgpu/hal/gr/gr/gr_gv100.c

@@ -154,6 +154,47 @@ void gr_gv100_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon,
 	*num_gpc_perfmon = perfmon_index;
 }
 
+void gr_gv100_reset_hwpm_pmm_registers(struct gk20a *g)
+{
+	u32 count;
+	const u32 *perfmon_regs;
+	u32 i;
+
+	if (g->num_sys_perfmon == 0U) {
+		g->ops.gr.get_num_hwpm_perfmon(g, &g->num_sys_perfmon,
+				&g->num_fbp_perfmon, &g->num_gpc_perfmon);
+	}
+
+	perfmon_regs = g->ops.perf.get_hwpm_sys_perfmon_regs(&count);
+
+	for (i = 0U; i < count; i++) {
+		g->ops.gr.set_pmm_register(g, perfmon_regs[i], 0U, 1U,
+			g->ops.perf.get_pmmsys_per_chiplet_offset(),
+			g->num_sys_perfmon);
+	}
+
+	/*
+	 * All the registers are broadcast ones so trigger
+	 * g->ops.gr.set_pmm_register() only with 1 chiplet even for
+	 * GPC and FBP chiplets.
+	 */
+	perfmon_regs = g->ops.perf.get_hwpm_fbp_perfmon_regs(&count);
+
+	for (i = 0U; i < count; i++) {
+		g->ops.gr.set_pmm_register(g, perfmon_regs[i], 0U, 1U,
+			g->ops.perf.get_pmmfbp_per_chiplet_offset(),
+			g->num_fbp_perfmon);
+	}
+
+	perfmon_regs = g->ops.perf.get_hwpm_gpc_perfmon_regs(&count);
+
+	for (i = 0U; i < count; i++) {
+		g->ops.gr.set_pmm_register(g, perfmon_regs[i], 0U, 1U,
+			g->ops.perf.get_pmmgpc_per_chiplet_offset(),
+			g->num_gpc_perfmon);
+	}
+}
+
 void gr_gv100_init_hwpm_pmm_register(struct gk20a *g)
 {
 	if (g->num_sys_perfmon == 0U) {

drivers/gpu/nvgpu/hal/gr/gr/gr_gv100.h

@@ -38,6 +38,7 @@ void gr_gv100_split_fbpa_broadcast_addr(struct gk20a *g, u32 addr,
 	u32 num_fbpas,
 	u32 *priv_addr_table, u32 *t);
 void gr_gv100_init_hwpm_pmm_register(struct gk20a *g);
+void gr_gv100_reset_hwpm_pmm_registers(struct gk20a *g);
 void gr_gv100_set_pmm_register(struct gk20a *g, u32 offset, u32 val,
 		u32 num_chiplets, u32 chiplet_stride, u32 num_perfmons);
 void gr_gv100_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon,

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -654,6 +654,7 @@ static const struct gops_gr gv11b_ops_gr = {
 	.set_pmm_register = gr_gv100_set_pmm_register,
 	.update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode,
 	.init_hwpm_pmm_register = gr_gv100_init_hwpm_pmm_register,
+	.reset_hwpm_pmm_registers = gr_gv100_reset_hwpm_pmm_registers,
 	.clear_sm_error_state = gv11b_gr_clear_sm_error_state,
 	.suspend_contexts = gr_gp10b_suspend_contexts,
 	.resume_contexts = gr_gk20a_resume_contexts,
@@ -1227,6 +1228,9 @@ static const struct gops_perf gv11b_ops_perf = {
 	.get_pmmgpc_per_chiplet_offset = gv11b_perf_get_pmmgpc_per_chiplet_offset,
 	.get_pmmfbp_per_chiplet_offset = gv11b_perf_get_pmmfbp_per_chiplet_offset,
 	.update_get_put = gv11b_perf_update_get_put,
+	.get_hwpm_sys_perfmon_regs = gv11b_perf_get_hwpm_sys_perfmon_regs,
+	.get_hwpm_gpc_perfmon_regs = gv11b_perf_get_hwpm_gpc_perfmon_regs,
+	.get_hwpm_fbp_perfmon_regs = gv11b_perf_get_hwpm_fbp_perfmon_regs,
 };
 #endif
 

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -168,6 +168,7 @@
 #include "hal/gsp/gsp_tu104.h"
 #ifdef CONFIG_NVGPU_DEBUGGER
 #include "hal/perf/perf_gv11b.h"
+#include "hal/perf/perf_tu104.h"
 #endif
 #ifdef CONFIG_NVGPU_DGPU
 #include "hal/sec2/sec2_tu104.h"
@@ -697,6 +698,7 @@ static const struct gops_gr tu104_ops_gr = {
 	.set_mmu_debug_mode = gm20b_gr_set_mmu_debug_mode,
 	.update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode,
 	.init_hwpm_pmm_register = gr_gv100_init_hwpm_pmm_register,
+	.reset_hwpm_pmm_registers = gr_gv100_reset_hwpm_pmm_registers,
 	.clear_sm_error_state = gv11b_gr_clear_sm_error_state,
 	.suspend_contexts = gr_gp10b_suspend_contexts,
 	.resume_contexts = gr_gk20a_resume_contexts,
@@ -1295,6 +1297,9 @@ static const struct gops_perf tu104_ops_perf = {
 	.get_pmmgpc_per_chiplet_offset = gv11b_perf_get_pmmgpc_per_chiplet_offset,
 	.get_pmmfbp_per_chiplet_offset = gv11b_perf_get_pmmfbp_per_chiplet_offset,
 	.update_get_put = gv11b_perf_update_get_put,
+	.get_hwpm_sys_perfmon_regs = tu104_perf_get_hwpm_sys_perfmon_regs,
+	.get_hwpm_gpc_perfmon_regs = tu104_perf_get_hwpm_gpc_perfmon_regs,
+	.get_hwpm_fbp_perfmon_regs = tu104_perf_get_hwpm_fbp_perfmon_regs,
 };
 #endif
 

drivers/gpu/nvgpu/hal/perf/perf_gv11b.c

@@ -160,3 +160,201 @@ u32 gv11b_perf_get_pmmfbp_per_chiplet_offset(void)
 {
 	return (perf_pmmfbp_extent_v() - perf_pmmfbp_base_v() + 1U);
 }
+
+static const u32 hwpm_sys_perfmon_regs[] =
+{
+	/* This list is autogenerated. Do not edit. */
+	0x00240040,
+	0x00240044,
+	0x00240048,
+	0x0024004c,
+	0x00240050,
+	0x00240054,
+	0x00240058,
+	0x0024005c,
+	0x00240060,
+	0x00240064,
+	0x00240068,
+	0x0024006c,
+	0x00240070,
+	0x00240074,
+	0x00240078,
+	0x0024007c,
+	0x00240080,
+	0x00240084,
+	0x00240088,
+	0x0024008c,
+	0x00240090,
+	0x00240094,
+	0x00240098,
+	0x0024009c,
+	0x002400a0,
+	0x002400a4,
+	0x002400a8,
+	0x002400ac,
+	0x002400b0,
+	0x002400b4,
+	0x002400b8,
+	0x002400bc,
+	0x002400c0,
+	0x002400c4,
+	0x002400c8,
+	0x002400cc,
+	0x002400d0,
+	0x002400d4,
+	0x002400d8,
+	0x002400dc,
+	0x002400e0,
+	0x002400e4,
+	0x002400e8,
+	0x002400ec,
+	0x002400f8,
+	0x002400fc,
+	0x00240104,
+	0x00240108,
+	0x0024010c,
+	0x00240110,
+	0x00240120,
+	0x00240114,
+	0x00240118,
+	0x0024011c,
+	0x00240124,
+};
+
+static const u32 hwpm_gpc_perfmon_regs[] =
+{
+	/* This list is autogenerated. Do not edit. */
+	0x00278040,
+	0x00278044,
+	0x00278048,
+	0x0027804c,
+	0x00278050,
+	0x00278054,
+	0x00278058,
+	0x0027805c,
+	0x00278060,
+	0x00278064,
+	0x00278068,
+	0x0027806c,
+	0x00278070,
+	0x00278074,
+	0x00278078,
+	0x0027807c,
+	0x00278080,
+	0x00278084,
+	0x00278088,
+	0x0027808c,
+	0x00278090,
+	0x00278094,
+	0x00278098,
+	0x0027809c,
+	0x002780a0,
+	0x002780a4,
+	0x002780a8,
+	0x002780ac,
+	0x002780b0,
+	0x002780b4,
+	0x002780b8,
+	0x002780bc,
+	0x002780c0,
+	0x002780c4,
+	0x002780c8,
+	0x002780cc,
+	0x002780d0,
+	0x002780d4,
+	0x002780d8,
+	0x002780dc,
+	0x002780e0,
+	0x002780e4,
+	0x002780e8,
+	0x002780ec,
+	0x002780f8,
+	0x002780fc,
+	0x00278104,
+	0x00278108,
+	0x0027810c,
+	0x00278110,
+	0x00278120,
+	0x00278114,
+	0x00278118,
+	0x0027811c,
+	0x00278124,
+};
+
+static const u32 hwpm_fbp_perfmon_regs[] =
+{
+	/* This list is autogenerated. Do not edit. */
+	0x0027c040,
+	0x0027c044,
+	0x0027c048,
+	0x0027c04c,
+	0x0027c050,
+	0x0027c054,
+	0x0027c058,
+	0x0027c05c,
+	0x0027c060,
+	0x0027c064,
+	0x0027c068,
+	0x0027c06c,
+	0x0027c070,
+	0x0027c074,
+	0x0027c078,
+	0x0027c07c,
+	0x0027c080,
+	0x0027c084,
+	0x0027c088,
+	0x0027c08c,
+	0x0027c090,
+	0x0027c094,
+	0x0027c098,
+	0x0027c09c,
+	0x0027c0a0,
+	0x0027c0a4,
+	0x0027c0a8,
+	0x0027c0ac,
+	0x0027c0b0,
+	0x0027c0b4,
+	0x0027c0b8,
+	0x0027c0bc,
+	0x0027c0c0,
+	0x0027c0c4,
+	0x0027c0c8,
+	0x0027c0cc,
+	0x0027c0d0,
+	0x0027c0d4,
+	0x0027c0d8,
+	0x0027c0dc,
+	0x0027c0e0,
+	0x0027c0e4,
+	0x0027c0e8,
+	0x0027c0ec,
+	0x0027c0f8,
+	0x0027c0fc,
+	0x0027c104,
+	0x0027c108,
+	0x0027c10c,
+	0x0027c110,
+	0x0027c120,
+	0x0027c114,
+	0x0027c118,
+	0x0027c11c,
+	0x0027c124,
+};
+
+const u32 *gv11b_perf_get_hwpm_sys_perfmon_regs(u32 *count)
+{
+	*count = sizeof(hwpm_sys_perfmon_regs) / sizeof(hwpm_sys_perfmon_regs[0]);
+	return hwpm_sys_perfmon_regs;
+}
+
+const u32 *gv11b_perf_get_hwpm_gpc_perfmon_regs(u32 *count)
+{
+	*count = sizeof(hwpm_gpc_perfmon_regs) / sizeof(hwpm_gpc_perfmon_regs[0]);
+	return hwpm_gpc_perfmon_regs;
+}
+
+const u32 *gv11b_perf_get_hwpm_fbp_perfmon_regs(u32 *count)
+{
+	*count = sizeof(hwpm_fbp_perfmon_regs) / sizeof(hwpm_fbp_perfmon_regs[0]);
+	return hwpm_fbp_perfmon_regs;
+}

drivers/gpu/nvgpu/hal/perf/perf_gv11b.h

@@ -52,5 +52,9 @@ u32 gv11b_perf_get_pmmsys_per_chiplet_offset(void);
 u32 gv11b_perf_get_pmmgpc_per_chiplet_offset(void);
 u32 gv11b_perf_get_pmmfbp_per_chiplet_offset(void);
 
+const u32 *gv11b_perf_get_hwpm_sys_perfmon_regs(u32 *count);
+const u32 *gv11b_perf_get_hwpm_gpc_perfmon_regs(u32 *count);
+const u32 *gv11b_perf_get_hwpm_fbp_perfmon_regs(u32 *count);
+
 #endif /* CONFIG_NVGPU_DEBUGGER */
 #endif

drivers/gpu/nvgpu/hal/perf/perf_tu104.c

@@ -0,0 +1,262 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+
+#include "perf_tu104.h"
+
+static const u32 hwpm_sys_perfmon_regs[] =
+{
+	/* This list is autogenerated. Do not edit. */
+	0x00240000,
+	0x00240004,
+	0x00240008,
+	0x0024000c,
+	0x00240010,
+	0x00240014,
+	0x00240020,
+	0x00240024,
+	0x00240028,
+	0x0024002c,
+	0x00240030,
+	0x00240034,
+	0x00240040,
+	0x00240044,
+	0x00240048,
+	0x0024004c,
+	0x00240050,
+	0x00240054,
+	0x00240058,
+	0x0024005c,
+	0x00240060,
+	0x00240064,
+	0x00240068,
+	0x0024006c,
+	0x00240070,
+	0x00240074,
+	0x00240078,
+	0x0024007c,
+	0x00240080,
+	0x00240084,
+	0x00240088,
+	0x0024008c,
+	0x00240090,
+	0x00240094,
+	0x00240098,
+	0x0024009c,
+	0x002400a0,
+	0x002400a4,
+	0x002400a8,
+	0x002400ac,
+	0x002400b0,
+	0x002400b4,
+	0x002400b8,
+	0x002400bc,
+	0x002400c0,
+	0x002400c4,
+	0x002400c8,
+	0x002400cc,
+	0x002400d0,
+	0x002400d4,
+	0x002400d8,
+	0x002400dc,
+	0x002400e0,
+	0x002400e4,
+	0x002400e8,
+	0x002400ec,
+	0x002400f8,
+	0x002400fc,
+	0x00240104,
+	0x00240108,
+	0x0024010c,
+	0x00240110,
+	0x00240120,
+	0x00240114,
+	0x00240118,
+	0x0024011c,
+	0x00240124,
+	0x00240100,
+};
+
+static const u32 hwpm_gpc_perfmon_regs[] =
+{
+	/* This list is autogenerated. Do not edit. */
+	0x00278000,
+	0x00278004,
+	0x00278008,
+	0x0027800c,
+	0x00278010,
+	0x00278014,
+	0x00278020,
+	0x00278024,
+	0x00278028,
+	0x0027802c,
+	0x00278030,
+	0x00278034,
+	0x00278040,
+	0x00278044,
+	0x00278048,
+	0x0027804c,
+	0x00278050,
+	0x00278054,
+	0x00278058,
+	0x0027805c,
+	0x00278060,
+	0x00278064,
+	0x00278068,
+	0x0027806c,
+	0x00278070,
+	0x00278074,
+	0x00278078,
+	0x0027807c,
+	0x00278080,
+	0x00278084,
+	0x00278088,
+	0x0027808c,
+	0x00278090,
+	0x00278094,
+	0x00278098,
+	0x0027809c,
+	0x002780a0,
+	0x002780a4,
+	0x002780a8,
+	0x002780ac,
+	0x002780b0,
+	0x002780b4,
+	0x002780b8,
+	0x002780bc,
+	0x002780c0,
+	0x002780c4,
+	0x002780c8,
+	0x002780cc,
+	0x002780d0,
+	0x002780d4,
+	0x002780d8,
+	0x002780dc,
+	0x002780e0,
+	0x002780e4,
+	0x002780e8,
+	0x002780ec,
+	0x002780f8,
+	0x002780fc,
+	0x00278104,
+	0x00278108,
+	0x0027810c,
+	0x00278110,
+	0x00278120,
+	0x00278114,
+	0x00278118,
+	0x0027811c,
+	0x00278124,
+	0x00278100,
+};
+
+static const u32 hwpm_fbp_perfmon_regs[] =
+{
+	/* This list is autogenerated. Do not edit. */
+	0x0027c000,
+	0x0027c004,
+	0x0027c008,
+	0x0027c00c,
+	0x0027c010,
+	0x0027c014,
+	0x0027c020,
+	0x0027c024,
+	0x0027c028,
+	0x0027c02c,
+	0x0027c030,
+	0x0027c034,
+	0x0027c040,
+	0x0027c044,
+	0x0027c048,
+	0x0027c04c,
+	0x0027c050,
+	0x0027c054,
+	0x0027c058,
+	0x0027c05c,
+	0x0027c060,
+	0x0027c064,
+	0x0027c068,
+	0x0027c06c,
+	0x0027c070,
+	0x0027c074,
+	0x0027c078,
+	0x0027c07c,
+	0x0027c080,
+	0x0027c084,
+	0x0027c088,
+	0x0027c08c,
+	0x0027c090,
+	0x0027c094,
+	0x0027c098,
+	0x0027c09c,
+	0x0027c0a0,
+	0x0027c0a4,
+	0x0027c0a8,
+	0x0027c0ac,
+	0x0027c0b0,
+	0x0027c0b4,
+	0x0027c0b8,
+	0x0027c0bc,
+	0x0027c0c0,
+	0x0027c0c4,
+	0x0027c0c8,
+	0x0027c0cc,
+	0x0027c0d0,
+	0x0027c0d4,
+	0x0027c0d8,
+	0x0027c0dc,
+	0x0027c0e0,
+	0x0027c0e4,
+	0x0027c0e8,
+	0x0027c0ec,
+	0x0027c0f8,
+	0x0027c0fc,
+	0x0027c104,
+	0x0027c108,
+	0x0027c10c,
+	0x0027c110,
+	0x0027c120,
+	0x0027c114,
+	0x0027c118,
+	0x0027c11c,
+	0x0027c124,
+	0x0027c100,
+};
+
+const u32 *tu104_perf_get_hwpm_sys_perfmon_regs(u32 *count)
+{
+	*count = sizeof(hwpm_sys_perfmon_regs) / sizeof(hwpm_sys_perfmon_regs[0]);
+	return hwpm_sys_perfmon_regs;
+}
+
+const u32 *tu104_perf_get_hwpm_gpc_perfmon_regs(u32 *count)
+{
+	*count = sizeof(hwpm_gpc_perfmon_regs) / sizeof(hwpm_gpc_perfmon_regs[0]);
+	return hwpm_gpc_perfmon_regs;
+}
+
+const u32 *tu104_perf_get_hwpm_fbp_perfmon_regs(u32 *count)
+{
+	*count = sizeof(hwpm_fbp_perfmon_regs) / sizeof(hwpm_fbp_perfmon_regs[0]);
+	return hwpm_fbp_perfmon_regs;
+}

drivers/gpu/nvgpu/hal/perf/perf_tu104.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_TU104_PERF
+#define NVGPU_TU104_PERF
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+
+#include <nvgpu/types.h>
+
+const u32 *tu104_perf_get_hwpm_sys_perfmon_regs(u32 *count);
+const u32 *tu104_perf_get_hwpm_gpc_perfmon_regs(u32 *count);
+const u32 *tu104_perf_get_hwpm_fbp_perfmon_regs(u32 *count);
+
+#endif /* CONFIG_NVGPU_DEBUGGER */
+#endif

drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h

@@ -60,6 +60,9 @@ struct gops_perf {
 	u32 (*get_pmmfbp_per_chiplet_offset)(void);
 	int (*update_get_put)(struct gk20a *g, u64 bytes_consumed,
 		bool update_available_bytes, u64 *put_ptr, bool *overflowed);
+	const u32 *(*get_hwpm_sys_perfmon_regs)(u32 *count);
+	const u32 *(*get_hwpm_fbp_perfmon_regs)(u32 *count);
+	const u32 *(*get_hwpm_gpc_perfmon_regs)(u32 *count);
 };
 struct gops_perfbuf {
 	int (*perfbuf_enable)(struct gk20a *g, u64 offset, u32 size);

drivers/gpu/nvgpu/include/nvgpu/gops/gr.h

@@ -1089,6 +1089,7 @@ struct gops_gr {
 				     u32 *num_gpc_perfmon);
 	void (*set_pmm_register)(struct gk20a *g, u32 offset, u32 val,
 			 u32 num_chiplets, u32 chiplet_stride, u32 num_perfmons);
+	void (*reset_hwpm_pmm_registers)(struct gk20a *g);
 	int (*dump_gr_regs)(struct gk20a *g,
 			    struct nvgpu_debug_context *o);
 	int (*update_pc_sampling)(struct nvgpu_channel *ch,