gpu: nvgpu: vgpu: add cmd to get RM server constants

Moving getting constant attributes into one cmd which will be
called only once.

This patch adds basic infrastructure and gpu arch info, max_freq
and num_channels support.

JIRA VFND-2103

Change-Id: I100599b49f29c99966f9e90ea381b1f3c09177a3
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1189832
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>

drivers/gpu/nvgpu/vgpu/fifo_vgpu.c

@@ -237,6 +237,7 @@ static int vgpu_init_fifo_setup_sw(struct gk20a *g)
 {
 	struct fifo_gk20a *f = &g->fifo;
 	struct device *d = dev_from_gk20a(g);
+	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
 	int chid, err = 0;
 
 	gk20a_dbg_fn("");
@@ -247,13 +248,7 @@ static int vgpu_init_fifo_setup_sw(struct gk20a *g)
 	}
 
 	f->g = g;
-
+	f->num_channels = priv->constants.num_channels;
-	err = vgpu_get_attribute(vgpu_get_handle(g),
-				TEGRA_VGPU_ATTRIB_NUM_CHANNELS,
-				&f->num_channels);
-	if (err)
-		return -ENXIO;
-
 	f->max_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
 
 	f->userd_entry_size = 1 << ram_userd_base_shift_v();

drivers/gpu/nvgpu/vgpu/vgpu.c

@@ -271,22 +271,11 @@ int vgpu_pm_prepare_poweroff(struct device *dev)
 static void vgpu_detect_chip(struct gk20a *g)
 {
 	struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics;
+	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
 
-	u32 mc_boot_0_value;
+	gpu->arch = priv->constants.arch;
-
+	gpu->impl = priv->constants.impl;
-	if (vgpu_get_attribute(vgpu_get_handle(g),
+	gpu->rev = priv->constants.rev;
-			TEGRA_VGPU_ATTRIB_PMC_BOOT_0,
-			&mc_boot_0_value)) {
-		gk20a_err(dev_from_gk20a(g), "failed to detect chip");
-		return;
-	}
-
-	gpu->arch = mc_boot_0_architecture_v(mc_boot_0_value) <<
-		NVGPU_GPU_ARCHITECTURE_SHIFT;
-	gpu->impl = mc_boot_0_implementation_v(mc_boot_0_value);
-	gpu->rev =
-		(mc_boot_0_major_revision_v(mc_boot_0_value) << 4) |
-		mc_boot_0_minor_revision_v(mc_boot_0_value);
 
 	gk20a_dbg_info("arch: %x, impl: %x, rev: %x\n",
 			g->gpu_characteristics.arch,
@@ -296,7 +285,7 @@ static void vgpu_detect_chip(struct gk20a *g)
 
 static int vgpu_init_gpu_characteristics(struct gk20a *g)
 {
-	u32 max_freq;
+	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
 	int err;
 
 	gk20a_dbg_fn("");
@@ -305,11 +294,7 @@ static int vgpu_init_gpu_characteristics(struct gk20a *g)
 	if (err)
 		return err;
 
-	if (vgpu_get_attribute(vgpu_get_handle(g),
+	g->gpu_characteristics.max_freq = priv->constants.max_freq;
-			TEGRA_VGPU_ATTRIB_MAX_FREQ, &max_freq))
-		return -ENOMEM;
-
-	g->gpu_characteristics.max_freq = max_freq;
 	g->gpu_characteristics.map_buffer_batch_limit = 0;
 	return 0;
 }
@@ -500,6 +485,29 @@ static int vgpu_pm_init(struct device *dev)
 	return err;
 }
 
+static int vgpu_get_constants(struct gk20a *g)
+{
+	struct tegra_vgpu_cmd_msg msg = {};
+	struct tegra_vgpu_constants_params *p = &msg.params.constants;
+	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
+	int err;
+
+	gk20a_dbg_fn("");
+
+	msg.cmd = TEGRA_VGPU_CMD_GET_CONSTANTS;
+	msg.handle = vgpu_get_handle(g);
+	err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+	err = err ? err : msg.ret;
+
+	if (unlikely(err)) {
+		gk20a_err(g->dev, "%s failed, err=%d", __func__, err);
+		return err;
+	}
+
+	priv->constants = *p;
+	return 0;
+}
+
 int vgpu_probe(struct platform_device *pdev)
 {
 	struct gk20a *gk20a;
@@ -573,6 +581,12 @@ int vgpu_probe(struct platform_device *pdev)
 		return -ENOSYS;
 	}
 
+	err = vgpu_get_constants(gk20a);
+	if (err) {
+		vgpu_comm_deinit();
+		return err;
+	}
+
 	priv->intr_handler = kthread_run(vgpu_intr_thread, gk20a, "gk20a");
 	if (IS_ERR(priv->intr_handler))
 		return -ENOMEM;

drivers/gpu/nvgpu/vgpu/vgpu.h

@@ -25,6 +25,7 @@
 struct vgpu_priv_data {
 	u64 virt_handle;
 	struct task_struct *intr_handler;
+	struct tegra_vgpu_constants_params constants;
 };
 
 static inline

include/linux/tegra_vgpu.h

@@ -96,6 +96,7 @@ enum {
 	TEGRA_VGPU_CMD_READ_PTIMER = 59,
 	TEGRA_VGPU_CMD_SET_POWERGATE = 60,
 	TEGRA_VGPU_CMD_SET_GPU_CLK_RATE = 61,
+	TEGRA_VGPU_CMD_GET_CONSTANTS = 62,
 };
 
 struct tegra_vgpu_connect_params {
@@ -110,14 +111,14 @@ struct tegra_vgpu_channel_hwctx_params {
 };
 
 enum {
-	TEGRA_VGPU_ATTRIB_NUM_CHANNELS = 0,
+	TEGRA_VGPU_ATTRIB_NUM_CHANNELS = 0, /*deprecated */
 	TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE = 1,
 	TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE = 2,
 	TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3,
 	TEGRA_VGPU_ATTRIB_GPC_COUNT = 4,
 	TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5,
 	TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6,
-	TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7,
+	TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7, /* deprecated */
 	TEGRA_VGPU_ATTRIB_L2_SIZE = 8,
 	TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9,
 	TEGRA_VGPU_ATTRIB_NUM_FBPS = 10,
@@ -131,7 +132,7 @@ enum {
 	TEGRA_VGPU_ATTRIB_LTC_COUNT = 18,
 	TEGRA_VGPU_ATTRIB_TPC_COUNT = 19,
 	TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20,
-	TEGRA_VGPU_ATTRIB_MAX_FREQ = 21,
+	TEGRA_VGPU_ATTRIB_MAX_FREQ = 21, /* deprecated */
 };
 
 struct tegra_vgpu_attrib_params {
@@ -402,6 +403,14 @@ struct tegra_vgpu_gpu_clk_rate_params {
 	u32 rate; /* in kHz */
 };
 
+struct tegra_vgpu_constants_params {
+	u32 arch;
+	u32 impl;
+	u32 rev;
+	u32 max_freq;
+	u32 num_channels;
+};
+
 struct tegra_vgpu_cmd_msg {
 	u32 cmd;
 	int ret;
@@ -445,6 +454,7 @@ struct tegra_vgpu_cmd_msg {
 		struct tegra_vgpu_read_ptimer_params read_ptimer;
 		struct tegra_vgpu_set_powergate_params set_powergate;
 		struct tegra_vgpu_gpu_clk_rate_params gpu_clk_rate;
+		struct tegra_vgpu_constants_params constants;
 		char padding[192];
 	} params;
 };