gpu: nvgpu: update sec2.h header

Update sec2.c to not dereference struct gk20a and update sec2.h to
remove unneeded header files. Move sec2.h to include/nvgpu/sec2.

JIRA NVGPU-2074

Change-Id: I1a8f4b1913323693fae422ce27c4ec0ac29de24a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085752
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/acr/acr_sw_tu104.c

@@ -24,7 +24,6 @@
 
 #include <nvgpu/gk20a.h>
 #include <nvgpu/firmware.h>
-#include <nvgpu/sec2if/sec2_if_cmn.h>
 
 #include "acr_wpr.h"
 #include "acr_priv.h"

drivers/gpu/nvgpu/common/fifo/runlist.c

@@ -25,6 +25,7 @@
 #include <nvgpu/fifo.h>
 #include <nvgpu/runlist.h>
 #include <nvgpu/bug.h>
+#include <nvgpu/dma.h>
 
 void nvgpu_fifo_lock_active_runlists(struct gk20a *g)
 {

drivers/gpu/nvgpu/common/fifo/userd.c

@@ -29,6 +29,7 @@
 #include <nvgpu/fifo.h>
 #include <nvgpu/fifo/userd.h>
 #include <nvgpu/vm_area.h>
+#include <nvgpu/dma.h>
 
 #ifdef NVGPU_USERD
 int nvgpu_userd_init_slabs(struct gk20a *g)

drivers/gpu/nvgpu/common/gr/ctx.c

@@ -26,6 +26,7 @@
 #include <nvgpu/vm.h>
 #include <nvgpu/io.h>
 #include <nvgpu/gmmu.h>
+#include <nvgpu/dma.h>
 
 static void nvgpu_gr_ctx_unmap_global_ctx_buffers(struct gk20a *g,
 	struct nvgpu_gr_ctx *gr_ctx,

drivers/gpu/nvgpu/common/gr/global_ctx.c

@@ -25,6 +25,7 @@
 #include <nvgpu/nvgpu_mem.h>
 #include <nvgpu/kmem.h>
 #include <nvgpu/bug.h>
+#include <nvgpu/dma.h>
 
 #include <nvgpu/gr/global_ctx.h>
 

drivers/gpu/nvgpu/common/gr/gr_falcon.c

@@ -29,11 +29,11 @@
 #include <nvgpu/firmware.h>
 #include <nvgpu/sizes.h>
 #include <nvgpu/mm.h>
-#include <nvgpu/sec2.h>
 #include <nvgpu/acr.h>
 #include <nvgpu/power_features/pg.h>
 #include <nvgpu/pmu/lsfm.h>
 #include <nvgpu/sec2/lsfm.h>
+#include <nvgpu/dma.h>
 
 #include "gr_falcon_priv.h"
 

drivers/gpu/nvgpu/common/gr/subctx.c

@@ -24,6 +24,7 @@
 #include <nvgpu/gr/subctx.h>
 #include <nvgpu/gr/ctx.h>
 #include <nvgpu/gmmu.h>
+#include <nvgpu/dma.h>
 
 #include "common/gr/subctx_priv.h"
 

drivers/gpu/nvgpu/common/sec2/sec2.c

@@ -22,12 +22,9 @@
 
 #include <nvgpu/gk20a.h>
 #include <nvgpu/log.h>
-#include <nvgpu/bug.h>
+#include <nvgpu/sec2/sec2.h>
-#include <nvgpu/timers.h>
-#include <nvgpu/sec2.h>
 #include <nvgpu/sec2/queue.h>
 #include <nvgpu/sec2/seq.h>
-#include <nvgpu/sec2if/sec2_if_cmn.h>
 #include <nvgpu/sec2/allocator.h>
 #include <nvgpu/sec2/msg.h>
 

drivers/gpu/nvgpu/common/sec2/sec2_cmd.c

@@ -23,9 +23,8 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/pmu.h>
 #include <nvgpu/log.h>
-#include <nvgpu/sec2.h>
+#include <nvgpu/sec2/sec2.h>
 #include <nvgpu/sec2/queue.h>
-#include <nvgpu/sec2if/sec2_if_cmn.h>
 #include <nvgpu/sec2/cmd.h>
 
 /* command post operation functions */

drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c

@@ -25,7 +25,6 @@
 #include <nvgpu/sec2/msg.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/sec2/cmd.h>
-#include <nvgpu/sec2if/sec2_if_cmn.h>
 
 /* Add code below to handle SEC2 RTOS commands */
 /* LSF's bootstrap command */

drivers/gpu/nvgpu/common/sec2/sec2_msg.c

@@ -20,14 +20,13 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#include <nvgpu/sec2if/sec2_if_cmn.h>
 #include <nvgpu/sec2/allocator.h>
 #include <nvgpu/engine_queue.h>
 #include <nvgpu/sec2/queue.h>
 #include <nvgpu/flcnif_cmn.h>
+#include <nvgpu/sec2/sec2.h>
 #include <nvgpu/sec2/msg.h>
 #include <nvgpu/gk20a.h>
-#include <nvgpu/sec2.h>
 
 /* Message/Event request handlers */
 static int sec2_response_handle(struct nvgpu_sec2 *sec2,

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -100,7 +100,7 @@ typedef void (*global_ctx_mem_destroy_fn)(struct gk20a *g,
 #include <nvgpu/sim.h>
 #include <nvgpu/ecc.h>
 #include <nvgpu/tsg.h>
-#include <nvgpu/sec2.h>
+#include <nvgpu/sec2/sec2.h>
 #include <nvgpu/cbc.h>
 #include <nvgpu/ltc.h>
 #include <nvgpu/nvgpu_err.h>

drivers/gpu/nvgpu/include/nvgpu/sec2/msg.h

@@ -24,7 +24,7 @@
 #define NVGPU_SEC2_MSG_H
 
 #include <nvgpu/sec2/lsfm.h>
-#include <nvgpu/sec2/queue_cmn.h>
+#include <nvgpu/sec2/sec2_cmn.h>
 #include <nvgpu/flcnif_cmn.h>
 #include <nvgpu/types.h>
 

drivers/gpu/nvgpu/include/nvgpu/sec2/queue_cmn.h

@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef NVGPU_SEC2_CMN_H
-#define NVGPU_SEC2_CMN_H
-
-/*
- * Defines the logical queue IDs that must be used when submitting commands
- * to or reading messages from SEC2. The identifiers must begin with zero and
- * should increment sequentially. _CMDQ_LOG_ID__LAST must always be set to the
- * last command queue identifier. _NUM must always be set to the last
- * identifier plus one.
- */
-#define SEC2_NV_CMDQ_LOG_ID			0U
-#define SEC2_NV_CMDQ_LOG_ID__LAST	0U
-#define SEC2_NV_MSGQ_LOG_ID			1U
-#define SEC2_QUEUE_NUM				2U
-
-#endif /* NVGPU_SEC2_CMN_H */

drivers/gpu/nvgpu/include/nvgpu/sec2/sec2.h

@@ -23,16 +23,16 @@
 #ifndef NVGPU_SEC2_H
 #define NVGPU_SEC2_H
 
-#include <nvgpu/kmem.h>
-#include <nvgpu/dma.h>
 #include <nvgpu/nvgpu_mem.h>
 #include <nvgpu/allocator.h>
 #include <nvgpu/lock.h>
-#include <nvgpu/flcnif_cmn.h>
 #include <nvgpu/falcon.h>
-#include <nvgpu/engine_mem_queue.h>
 #include <nvgpu/sec2/seq.h>
-#include <nvgpu/sec2/queue_cmn.h>
+#include <nvgpu/sec2/sec2_cmn.h>
+
+struct gk20a;
+struct nv_flcn_msg_sec2;
+struct nvgpu_engine_mem_queue;
 
 #define nvgpu_sec2_dbg(g, fmt, args...) \
 	nvgpu_log(g, gpu_dbg_pmu, fmt, ##args)

drivers/gpu/nvgpu/include/nvgpu/sec2/sec2_cmn.h

@@ -20,8 +20,20 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef NVGPU_SEC2_IF_CMN_H
+#ifndef NVGPU_SEC2_CMN_H
-#define NVGPU_SEC2_IF_CMN_H
+#define NVGPU_SEC2_CMN_H
+
+/*
+ * Defines the logical queue IDs that must be used when submitting commands
+ * to or reading messages from SEC2. The identifiers must begin with zero and
+ * should increment sequentially. _CMDQ_LOG_ID__LAST must always be set to the
+ * last command queue identifier. _NUM must always be set to the last
+ * identifier plus one.
+ */
+#define SEC2_NV_CMDQ_LOG_ID			0U
+#define SEC2_NV_CMDQ_LOG_ID__LAST	0U
+#define SEC2_NV_MSGQ_LOG_ID			1U
+#define SEC2_QUEUE_NUM				2U
 
 /*
  * Define the maximum number of command sequences that can be in flight at
@@ -54,7 +66,8 @@
  * enumeration that gives name to each index based on type of memory-aperture
  * the index is used to access.
  *
- * Pre-Turing, NV_SEC2_DMAIDX_PHYS_VID_FN0 == NV_SEC2_DMAIDX_GUEST_PHYS_VID_BOUND.
+ * Pre-Turing,
+ * NV_SEC2_DMAIDX_PHYS_VID_FN0 == NV_SEC2_DMAIDX_GUEST_PHYS_VID_BOUND.
  * From Turing, engine context is stored in GPA, requiring a separate aperture.
  *
  * Traditionally, video falcons have used the 6th index for ucode, and we will
@@ -75,4 +88,4 @@
 #define NV_SEC2_DMAIDX_UCODE                     6U
 #define NV_SEC2_DMAIDX_GUEST_PHYS_SYS_NCOH_BOUND 7U
 
-#endif  /* NVGPU_SEC2_IF_CMN_H */
+#endif  /* NVGPU_SEC2_CMN_H */

drivers/gpu/nvgpu/tu104/sec2_tu104.c

@@ -28,7 +28,7 @@
 #include <nvgpu/timers.h>
 #include <nvgpu/falcon.h>
 #include <nvgpu/engine_mem_queue.h>
-#include <nvgpu/sec2.h>
+#include <nvgpu/sec2/sec2.h>
 #include <nvgpu/sec2/msg.h>
 #include <nvgpu/bug.h>
 

userspace/units/mm/gmmu/pd_cache/pd_cache.c

@@ -30,6 +30,7 @@
 #include <nvgpu/pd_cache.h>
 #include <nvgpu/enabled.h>
 
+#include <nvgpu/posix/dma.h>
 #include <nvgpu/posix/kmem.h>
 #include <nvgpu/posix/posix-fault-injection.h>
 

userspace/units/mm/nvgpu_mem/nvgpu_mem.c

@@ -30,6 +30,7 @@
 #include <nvgpu/pramin.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/sizes.h>
+#include <nvgpu/dma.h>
 #include <nvgpu/posix/io.h>
 #include <nvgpu/posix/posix-fault-injection.h>
 #include <os/posix/os_posix.h>