diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index ecc9c88ca..3c1bf3aaf 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -349,6 +349,8 @@ nvgpu-y += \ common/fifo/engines.o \ common/fifo/engine_status_gm20b.o \ common/fifo/engine_status_gv100.o \ + common/fifo/pbdma_status.o \ + common/fifo/pbdma_status_gm20b.o \ common/ecc.o \ common/ce2.o \ common/debugger.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 0ed2922f5..063960a19 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -193,6 +193,8 @@ srcs += common/sim.c \ common/fifo/engines.c \ common/fifo/engine_status_gm20b.c \ common/fifo/engine_status_gv100.c \ + common/fifo/pbdma_status.c \ + common/fifo/pbdma_status_gm20b.c \ common/mc/mc.c \ common/mc/mc_gm20b.c \ common/mc/mc_gp10b.c \ diff --git a/drivers/gpu/nvgpu/common/fifo/pbdma_status.c b/drivers/gpu/nvgpu/common/fifo/pbdma_status.c new file mode 100644 index 000000000..0c214d273 --- /dev/null +++ b/drivers/gpu/nvgpu/common/fifo/pbdma_status.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +bool nvgpu_pbdma_status_is_chsw_switch(struct nvgpu_pbdma_status_info + *pbdma_status) +{ + return pbdma_status->chsw_status == NVGPU_PBDMA_CHSW_STATUS_SWITCH; +} +bool nvgpu_pbdma_status_is_chsw_load(struct nvgpu_pbdma_status_info + *pbdma_status) +{ + return pbdma_status->chsw_status == NVGPU_PBDMA_CHSW_STATUS_LOAD; +} +bool nvgpu_pbdma_status_is_chsw_save(struct nvgpu_pbdma_status_info + *pbdma_status) +{ + return pbdma_status->chsw_status == NVGPU_PBDMA_CHSW_STATUS_SAVE; +} +bool nvgpu_pbdma_status_is_chsw_valid(struct nvgpu_pbdma_status_info + *pbdma_status) +{ + return pbdma_status->chsw_status == NVGPU_PBDMA_CHSW_STATUS_VALID; +} +bool nvgpu_pbdma_status_is_id_type_tsg(struct nvgpu_pbdma_status_info + *pbdma_status) +{ + return pbdma_status->id_type == PBDMA_STATUS_ID_TYPE_TSGID; +} +bool nvgpu_pbdma_status_is_next_id_type_tsg(struct nvgpu_pbdma_status_info + *pbdma_status) +{ + return pbdma_status->next_id_type == PBDMA_STATUS_NEXT_ID_TYPE_TSGID; +} diff --git a/drivers/gpu/nvgpu/common/fifo/pbdma_status_gm20b.c b/drivers/gpu/nvgpu/common/fifo/pbdma_status_gm20b.c new file mode 100644 index 000000000..2a97f6086 --- /dev/null +++ b/drivers/gpu/nvgpu/common/fifo/pbdma_status_gm20b.c @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include + +#include "pbdma_status_gm20b.h" + +static void populate_invalid_chsw_status_info( + struct nvgpu_pbdma_status_info *status_info) +{ + status_info->id = PBDMA_STATUS_ID_INVALID; + status_info->id_type = PBDMA_STATUS_ID_TYPE_INVALID; + status_info->next_id = PBDMA_STATUS_NEXT_ID_INVALID; + status_info->next_id_type = PBDMA_STATUS_NEXT_ID_TYPE_INVALID; + status_info->chsw_status = NVGPU_PBDMA_CHSW_STATUS_INVALID; +} + +static void populate_valid_chsw_status_info( + struct nvgpu_pbdma_status_info *status_info) +{ + bool id_type_tsg; + u32 engine_status = status_info->pbdma_reg_status; + + status_info->id = + fifo_pbdma_status_id_v(status_info->pbdma_reg_status); + id_type_tsg = fifo_pbdma_status_id_type_v(engine_status) == + fifo_pbdma_status_id_type_tsgid_v(); + status_info->id_type = + id_type_tsg ? PBDMA_STATUS_ID_TYPE_TSGID : + PBDMA_STATUS_ID_TYPE_CHID; + status_info->next_id = PBDMA_STATUS_NEXT_ID_INVALID; + status_info->next_id_type = PBDMA_STATUS_NEXT_ID_TYPE_INVALID; + status_info->chsw_status = NVGPU_PBDMA_CHSW_STATUS_VALID; +} + +static void populate_load_chsw_status_info( + struct nvgpu_pbdma_status_info *status_info) +{ + bool next_id_type_tsg; + u32 engine_status = status_info->pbdma_reg_status; + + status_info->id = PBDMA_STATUS_ID_INVALID; + status_info->id_type = PBDMA_STATUS_ID_TYPE_INVALID; + status_info->next_id = + fifo_pbdma_status_next_id_type_v( + status_info->pbdma_reg_status); + next_id_type_tsg = fifo_pbdma_status_next_id_type_v(engine_status) == + fifo_pbdma_status_next_id_type_tsgid_v(); + status_info->next_id_type = + next_id_type_tsg ? PBDMA_STATUS_NEXT_ID_TYPE_TSGID : + PBDMA_STATUS_NEXT_ID_TYPE_CHID; + status_info->chsw_status = NVGPU_PBDMA_CHSW_STATUS_LOAD; +} + +static void populate_save_chsw_status_info( + struct nvgpu_pbdma_status_info *status_info) +{ + bool id_type_tsg; + u32 engine_status = status_info->pbdma_reg_status; + + status_info->id = + fifo_pbdma_status_id_v(status_info->pbdma_reg_status); + id_type_tsg = fifo_pbdma_status_id_type_v(engine_status) == + fifo_pbdma_status_id_type_tsgid_v(); + status_info->id_type = + id_type_tsg ? PBDMA_STATUS_ID_TYPE_TSGID : + PBDMA_STATUS_ID_TYPE_CHID; + status_info->next_id = PBDMA_STATUS_NEXT_ID_INVALID; + status_info->next_id_type = PBDMA_STATUS_NEXT_ID_TYPE_INVALID; + status_info->chsw_status = NVGPU_PBDMA_CHSW_STATUS_SAVE; +} + +static void populate_switch_chsw_status_info( + struct nvgpu_pbdma_status_info *status_info) +{ + bool id_type_tsg; + bool next_id_type_tsg; + u32 engine_status = status_info->pbdma_reg_status; + + status_info->id = + fifo_pbdma_status_id_v(status_info->pbdma_reg_status); + id_type_tsg = fifo_pbdma_status_id_type_v(engine_status) == + fifo_pbdma_status_id_type_tsgid_v(); + status_info->id_type = + id_type_tsg ? PBDMA_STATUS_ID_TYPE_TSGID : + PBDMA_STATUS_ID_TYPE_CHID; + status_info->next_id = + fifo_pbdma_status_next_id_type_v( + status_info->pbdma_reg_status); + next_id_type_tsg = fifo_pbdma_status_next_id_type_v(engine_status) == + fifo_pbdma_status_next_id_type_tsgid_v(); + status_info->next_id_type = + next_id_type_tsg ? PBDMA_STATUS_NEXT_ID_TYPE_TSGID : + PBDMA_STATUS_NEXT_ID_TYPE_CHID; + status_info->chsw_status = NVGPU_PBDMA_CHSW_STATUS_SWITCH; +} + +void gm20b_read_pbdma_status_info(struct gk20a *g, u32 pbdma_id, + struct nvgpu_pbdma_status_info *status) +{ + u32 pbdma_reg_status; + u32 pbdma_channel_status; + + (void) memset(status, 0, sizeof(*status)); + + pbdma_reg_status = nvgpu_readl(g, fifo_pbdma_status_r(pbdma_id)); + + status->pbdma_reg_status = pbdma_reg_status; + + /* populate the chsw related info */ + pbdma_channel_status = fifo_pbdma_status_chan_status_v( + pbdma_reg_status); + + status->pbdma_channel_status = pbdma_channel_status; + + if (pbdma_channel_status == fifo_pbdma_status_chan_status_valid_v()) { + populate_valid_chsw_status_info(status); + } else if (pbdma_channel_status == + fifo_pbdma_status_chan_status_chsw_load_v()) { + populate_load_chsw_status_info(status); + } else if (pbdma_channel_status == + fifo_pbdma_status_chan_status_chsw_save_v()) { + populate_save_chsw_status_info(status); + } else if (pbdma_channel_status == + fifo_pbdma_status_chan_status_chsw_switch_v()) { + populate_switch_chsw_status_info(status); + } else { + populate_invalid_chsw_status_info(status); + } +} diff --git a/drivers/gpu/nvgpu/common/fifo/pbdma_status_gm20b.h b/drivers/gpu/nvgpu/common/fifo/pbdma_status_gm20b.h new file mode 100644 index 000000000..9f6f6856d --- /dev/null +++ b/drivers/gpu/nvgpu/common/fifo/pbdma_status_gm20b.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_PBDMA_STATUS_GM20B +#define NVGPU_PBDMA_STATUS_GM20B + +#include + +struct gk20a; +struct nvgpu_pbdma_status_info; + +void gm20b_read_pbdma_status_info(struct gk20a *g, u32 pbdma_id, + struct nvgpu_pbdma_status_info *status); + +#endif /* NVGPU_PBDMA_STATUS_GM20B */ diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 18b27f578..96a1223ad 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -62,6 +62,7 @@ #include "common/fifo/channel_gk20a.h" #include "common/fifo/channel_gm20b.h" #include "common/fifo/engine_status_gm20b.h" +#include "common/fifo/pbdma_status_gm20b.h" #include "gk20a/ce2_gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -572,6 +573,10 @@ static const struct gpu_ops gm20b_ops = { .read_engine_status_info = gm20b_read_engine_status_info, }, + .pbdma_status = { + .read_pbdma_status_info = + gm20b_read_pbdma_status_info, + }, .runlist = { .update_for_channel = gk20a_runlist_update_for_channel, .reload = gk20a_runlist_reload, @@ -828,6 +833,7 @@ int gm20b_init_hal(struct gk20a *g) gops->channel = gm20b_ops.channel; gops->sync = gm20b_ops.sync; gops->engine_status = gm20b_ops.engine_status; + gops->pbdma_status = gm20b_ops.pbdma_status; gops->netlist = gm20b_ops.netlist; gops->mm = gm20b_ops.mm; gops->therm = gm20b_ops.therm; diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index d0886e150..600a291e5 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -73,6 +73,7 @@ #include "common/fifo/channel_gk20a.h" #include "common/fifo/channel_gm20b.h" #include "common/fifo/engine_status_gm20b.h" +#include "common/fifo/pbdma_status_gm20b.h" #include "gk20a/fifo_gk20a.h" #include "gk20a/fecs_trace_gk20a.h" @@ -620,6 +621,10 @@ static const struct gpu_ops gp10b_ops = { .read_engine_status_info = gm20b_read_engine_status_info, }, + .pbdma_status = { + .read_pbdma_status_info = + gm20b_read_pbdma_status_info, + }, .runlist = { .reschedule = gk20a_runlist_reschedule, .reschedule_preempt_next_locked = gk20a_fifo_reschedule_preempt_next, @@ -908,6 +913,7 @@ int gp10b_init_hal(struct gk20a *g) gops->channel = gp10b_ops.channel; gops->sync = gp10b_ops.sync; gops->engine_status = gp10b_ops.engine_status; + gops->pbdma_status = gp10b_ops.pbdma_status; gops->netlist = gp10b_ops.netlist; #ifdef CONFIG_GK20A_CTXSW_TRACE gops->fecs_trace = gp10b_ops.fecs_trace; diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 7571d8ee9..f914d9fb0 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -84,6 +84,7 @@ #include "common/fifo/channel_gv11b.h" #include "common/fifo/channel_gv100.h" #include "common/fifo/engine_status_gv100.h" +#include "common/fifo/pbdma_status_gm20b.h" #include "gk20a/fifo_gk20a.h" #include "gk20a/fecs_trace_gk20a.h" @@ -787,6 +788,10 @@ static const struct gpu_ops gv100_ops = { .read_engine_status_info = read_engine_status_info_gv100, }, + .pbdma_status = { + .read_pbdma_status_info = + gm20b_read_pbdma_status_info, + }, .runlist = { .update_for_channel = gk20a_runlist_update_for_channel, .reload = gk20a_runlist_reload, @@ -1171,6 +1176,7 @@ int gv100_init_hal(struct gk20a *g) gops->channel = gv100_ops.channel; gops->sync = gv100_ops.sync; gops->engine_status = gv100_ops.engine_status; + gops->pbdma_status = gv100_ops.pbdma_status; gops->netlist = gv100_ops.netlist; gops->mm = gv100_ops.mm; #ifdef CONFIG_GK20A_CTXSW_TRACE diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 769caf93f..a8da4e209 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -70,6 +70,7 @@ #include "common/fifo/channel_gm20b.h" #include "common/fifo/channel_gv11b.h" #include "common/fifo/engine_status_gv100.h" +#include "common/fifo/pbdma_status_gm20b.h" #include "gk20a/fifo_gk20a.h" #include "gk20a/fecs_trace_gk20a.h" @@ -743,6 +744,10 @@ static const struct gpu_ops gv11b_ops = { .read_engine_status_info = read_engine_status_info_gv100, }, + .pbdma_status = { + .read_pbdma_status_info = + gm20b_read_pbdma_status_info, + }, .runlist = { .reschedule = gv11b_runlist_reschedule, .reschedule_preempt_next_locked = gk20a_fifo_reschedule_preempt_next, @@ -1039,6 +1044,7 @@ int gv11b_init_hal(struct gk20a *g) gops->channel = gv11b_ops.channel; gops->sync = gv11b_ops.sync; gops->engine_status = gv11b_ops.engine_status; + gops->pbdma_status = gv11b_ops.pbdma_status; gops->netlist = gv11b_ops.netlist; gops->mm = gv11b_ops.mm; #ifdef CONFIG_GK20A_CTXSW_TRACE diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 83b39503d..eb9018761 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -65,6 +65,7 @@ struct nvgpu_device_info; struct nvgpu_gr_subctx; struct nvgpu_channel_hw_state; struct nvgpu_engine_status_info; +struct nvgpu_pbdma_status_info; #include #include @@ -922,6 +923,10 @@ struct gpu_ops { void (*read_engine_status_info) (struct gk20a *g, u32 engine_id, struct nvgpu_engine_status_info *status); } engine_status; + struct { + void (*read_pbdma_status_info) (struct gk20a *g, + u32 engine_id, struct nvgpu_pbdma_status_info *status); + } pbdma_status; struct pmu_v { u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu); void (*set_pmu_cmdline_args_cpu_freq)(struct nvgpu_pmu *pmu, diff --git a/drivers/gpu/nvgpu/include/nvgpu/pbdma_status.h b/drivers/gpu/nvgpu/include/nvgpu/pbdma_status.h new file mode 100644 index 000000000..cfb44b100 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pbdma_status.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_PBDMA_STATUS_H +#define NVGPU_PBDMA_STATUS_H + +#include + +#define PBDMA_STATUS_ID_TYPE_CHID 0U +#define PBDMA_STATUS_ID_TYPE_TSGID 1U +#define PBDMA_STATUS_ID_TYPE_INVALID (~U32(0U)) + +#define PBDMA_STATUS_NEXT_ID_TYPE_CHID PBDMA_STATUS_ID_TYPE_CHID +#define PBDMA_STATUS_NEXT_ID_TYPE_TSGID PBDMA_STATUS_ID_TYPE_TSGID +#define PBDMA_STATUS_NEXT_ID_TYPE_INVALID PBDMA_STATUS_ID_TYPE_INVALID + +#define PBDMA_STATUS_ID_INVALID (~U32(0U)) +#define PBDMA_STATUS_NEXT_ID_INVALID PBDMA_STATUS_ID_INVALID + +enum nvgpu_pbdma_status_chsw_status { + NVGPU_PBDMA_CHSW_STATUS_INVALID, + NVGPU_PBDMA_CHSW_STATUS_VALID, + NVGPU_PBDMA_CHSW_STATUS_LOAD, + NVGPU_PBDMA_CHSW_STATUS_SAVE, + NVGPU_PBDMA_CHSW_STATUS_SWITCH, +}; + +struct nvgpu_pbdma_status_info { + u32 pbdma_reg_status; + u32 pbdma_channel_status; + u32 id; + u32 id_type; + u32 next_id; + u32 next_id_type; + + enum nvgpu_pbdma_status_chsw_status chsw_status; +}; + +bool nvgpu_pbdma_status_is_chsw_switch(struct nvgpu_pbdma_status_info + *pbdma_status); +bool nvgpu_pbdma_status_is_chsw_load(struct nvgpu_pbdma_status_info + *pbdma_status); +bool nvgpu_pbdma_status_is_chsw_save(struct nvgpu_pbdma_status_info + *pbdma_status); +bool nvgpu_pbdma_status_is_chsw_valid(struct nvgpu_pbdma_status_info + *pbdma_status); +bool nvgpu_pbdma_status_is_id_type_tsg(struct nvgpu_pbdma_status_info + *pbdma_status); +bool nvgpu_pbdma_status_is_next_id_type_tsg(struct nvgpu_pbdma_status_info + *pbdma_status); + +#endif /* NVGPU_PBDMA_STATUS_H */ diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index cb66789ed..499c221c5 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -88,6 +88,7 @@ #include "common/fifo/channel_gv11b.h" #include "common/fifo/channel_gv100.h" #include "common/fifo/engine_status_gv100.h" +#include "common/fifo/pbdma_status_gm20b.h" #include "gk20a/fifo_gk20a.h" #include "gk20a/fecs_trace_gk20a.h" @@ -817,6 +818,10 @@ static const struct gpu_ops tu104_ops = { .read_engine_status_info = read_engine_status_info_gv100, }, + .pbdma_status = { + .read_pbdma_status_info = + gm20b_read_pbdma_status_info, + }, .runlist = { .update_for_channel = gk20a_runlist_update_for_channel, .reload = gk20a_runlist_reload, @@ -1209,6 +1214,7 @@ int tu104_init_hal(struct gk20a *g) gops->channel = tu104_ops.channel; gops->sync = tu104_ops.sync; gops->engine_status = tu104_ops.engine_status; + gops->pbdma_status = tu104_ops.pbdma_status; gops->netlist = tu104_ops.netlist; gops->mm = tu104_ops.mm; #ifdef CONFIG_GK20A_CTXSW_TRACE diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 1a9301836..c3a319e50 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -432,6 +432,9 @@ static const struct gpu_ops vgpu_gp10b_ops = { .engine_status = { .read_engine_status_info = NULL, }, + .pbdma_status = { + .read_pbdma_status_info = NULL, + }, .runlist = { .reschedule = NULL, .update_for_channel = vgpu_runlist_update_for_channel, @@ -684,6 +687,7 @@ int vgpu_gp10b_init_hal(struct gk20a *g) gops->channel = vgpu_gp10b_ops.channel; gops->sync = vgpu_gp10b_ops.sync; gops->engine_status = vgpu_gp10b_ops.engine_status; + gops->pbdma_status = vgpu_gp10b_ops.pbdma_status; gops->netlist = vgpu_gp10b_ops.netlist; #ifdef CONFIG_GK20A_CTXSW_TRACE gops->fecs_trace = vgpu_gp10b_ops.fecs_trace; diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 222c24539..d2516a9c4 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -504,6 +504,9 @@ static const struct gpu_ops vgpu_gv11b_ops = { .engine_status = { .read_engine_status_info = NULL, }, + .pbdma_status = { + .read_pbdma_status_info = NULL, + }, .runlist = { .reschedule = NULL, .update_for_channel = vgpu_runlist_update_for_channel, @@ -755,6 +758,7 @@ int vgpu_gv11b_init_hal(struct gk20a *g) gops->channel = vgpu_gv11b_ops.channel; gops->sync = vgpu_gv11b_ops.sync; gops->engine_status = vgpu_gv11b_ops.engine_status; + gops->pbdma_status = vgpu_gv11b_ops.pbdma_status; gops->netlist = vgpu_gv11b_ops.netlist; gops->mm = vgpu_gv11b_ops.mm; #ifdef CONFIG_GK20A_CTXSW_TRACE