From 97ce51215b09daf23696d918a207aacba6b176cb Mon Sep 17 00:00:00 2001 From: vinodg Date: Tue, 7 Jan 2020 12:59:59 -0800 Subject: [PATCH] gpu: nvgpu: remove NVC0C0_SET_SHADER_EXCEPTIONS from gr intr test Remove unused NVC0C0_SET_SHADER_EXCEPTIONS from gr intr unit test. Update the mock io register with valid class number value. Jira NVGPU-4454 Change-Id: I1b6772c7c8d2c75f05d57cb5eb2a630aa7b6b6e0 Signed-off-by: vinodg Reviewed-on: https://git-master.nvidia.com/r/2275286 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: Seshendra Gadagottu Reviewed-by: Deepak Nibade GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions Tested-by: mobile promotions --- userspace/units/gr/intr/nvgpu-gr-intr.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/userspace/units/gr/intr/nvgpu-gr-intr.c b/userspace/units/gr/intr/nvgpu-gr-intr.c index cde1356e9..5e3623fe7 100644 --- a/userspace/units/gr/intr/nvgpu-gr-intr.c +++ b/userspace/units/gr/intr/nvgpu-gr-intr.c @@ -499,21 +499,16 @@ int test_gr_intr_without_channel(struct unit_module *m, struct test_gr_intr_sw_mthd_exceptions sw_excep[] = { [0] = { - .trapped_addr = NVC0C0_SET_SHADER_EXCEPTIONS, - .data[0] = NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE, - .data[1] = NVA297_SET_SHADER_EXCEPTIONS_ENABLE_TRUE, - }, - [1] = { .trapped_addr = NVC3C0_SET_SKEDCHECK, .data[0] = NVC397_SET_SKEDCHECK_18_ENABLE, .data[1] = NVC397_SET_SKEDCHECK_18_DISABLE, }, - [2] = { + [1] = { .trapped_addr = NVC3C0_SET_SHADER_CUT_COLLECTOR, .data[0] = NVC397_SET_SHADER_CUT_COLLECTOR_STATE_ENABLE, .data[1] = NVC397_SET_SHADER_CUT_COLLECTOR_STATE_DISABLE, }, - [3] = { + [2] = { .trapped_addr = 0, .data[0] = 0, .data[1] = 0, @@ -533,6 +528,10 @@ int test_gr_intr_sw_exceptions(struct unit_module *m, gr_intr_illegal_method_pending_f() | gr_intr_class_error_pending_f()); + /* valid class num */ + nvgpu_posix_io_writel_reg_space(g, + gr_fe_object_table_r(0), VOLTA_COMPUTE_A); + for (i = 0; i < arry_cnt; i++) { /* method & sub channel */ nvgpu_posix_io_writel_reg_space(g, gr_trapped_addr_r(),