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gpu: nvpgu: update ZBC table values for ga10b+

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- Patch updates the ZBC table values as per the POR values for safety
build.
- Fix the color table default values initialization for standard build
which was being done in floating point format for CROP while it should
be in FB format. As per the documentation "CROP ZBC table should be
programmed exactly the way the L2 table is programmed".

Bug 3585766

Change-Id: I47d11b6a230189ee0c818f850d36b93c0aea0e54
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2724935
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
prsethi
2022-06-05 06:16:32 +00:00
committed by mobile promotions
parent fdba1eef10
commit 9890a185e0
3 changed files with 116 additions and 305 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/gpu/nvgpu/hal/gr/zbc/zbc_ga10b.c
View File

@@ -87,7 +87,6 @@ void ga10b_gr_zbc_add_color(struct gk20a *g,
color_val, data_index_3))); color_val, data_index_3)));
} }
#ifndef CONFIG_NVGPU_NON_FUSA
static void ga10b_gr_zbc_load_default_sw_color_table(struct gk20a *g, static void ga10b_gr_zbc_load_default_sw_color_table(struct gk20a *g,
struct nvgpu_gr_zbc *zbc) struct nvgpu_gr_zbc *zbc)
{ {
@@ -98,6 +97,7 @@ static void ga10b_gr_zbc_load_default_sw_color_table(struct gk20a *g,
NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 1); NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 1);
NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 2); NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 2);
NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 3); NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 3);
#ifndef CONFIG_NVGPU_NON_FUSA
NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 4); NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 4);
NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 5); NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 5);
NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 6); NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 6);
@@ -123,10 +123,7 @@ static void ga10b_gr_zbc_load_default_sw_color_table(struct gk20a *g,
NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 24); NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 24);
NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 25); NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 25);
NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 26); NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 26);
NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 27); #endif
NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 28);
NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 29);
NVGPU_ZBC_SET_COLOR_ATTR(zbc->zbc_col_tbl, index, 30);
/* /*
* Reached to last entry, reduce index by 1 as it has increased * Reached to last entry, reduce index by 1 as it has increased
@@ -165,12 +162,6 @@ static void ga10b_gr_zbc_load_default_sw_stencil_table(struct gk20a *g,
index = nvgpu_safe_add_u32(index, 1U); index = nvgpu_safe_add_u32(index, 1U);
NVGPU_ZBC_SET_STENCIL_ATTR(zbc->zbc_s_tbl[index], 3); NVGPU_ZBC_SET_STENCIL_ATTR(zbc->zbc_s_tbl[index], 3);
index = nvgpu_safe_add_u32(index, 1U);
NVGPU_ZBC_SET_STENCIL_ATTR(zbc->zbc_s_tbl[index], 4);
index = nvgpu_safe_add_u32(index, 1U);
NVGPU_ZBC_SET_STENCIL_ATTR(zbc->zbc_s_tbl[index], 5);
zbc->max_used_stencil_index = index; zbc->max_used_stencil_index = index;
} }
@@ -188,4 +179,3 @@ void ga10b_gr_zbc_load_static_table(struct gk20a *g,
ga10b_gr_zbc_load_default_sw_stencil_table(g, zbc); ga10b_gr_zbc_load_default_sw_stencil_table(g, zbc);
} }
} }
#endif

403
drivers/gpu/nvgpu/hal/gr/zbc/zbc_ga10b.h
View File

@@ -35,321 +35,151 @@ void ga10b_gr_zbc_add_color(struct gk20a *g,
struct nvgpu_gr_zbc_entry *color_val, u32 index); struct nvgpu_gr_zbc_entry *color_val, u32 index);
void ga10b_gr_zbc_load_static_table(struct gk20a *g, void ga10b_gr_zbc_load_static_table(struct gk20a *g,
struct nvgpu_gr_zbc *zbc); struct nvgpu_gr_zbc *zbc);
#ifndef CONFIG_NVGPU_NON_FUSA
#define NVGPU_ZBC_SET_COLOR_ATTR(tbl, ind, i) \ #define NVGPU_ZBC_SET_COLOR_ATTR(tbl, ind, i) \
{ \ { \
(tbl)[ind].color_ds[0] = (NVGPU_ZBC_CL_DS_R_##i); \ (tbl)[ind].color_ds[0] = (NVGPU_ZBC_CL_VAL_1_IND_##i); \
(tbl)[ind].color_ds[1] = (NVGPU_ZBC_CL_DS_G_##i); \ (tbl)[ind].color_ds[1] = (NVGPU_ZBC_CL_VAL_2_IND_##i); \
(tbl)[ind].color_ds[2] = (NVGPU_ZBC_CL_DS_B_##i); \ (tbl)[ind].color_ds[2] = (NVGPU_ZBC_CL_VAL_3_IND_##i); \
(tbl)[ind].color_ds[3] = (NVGPU_ZBC_CL_DS_A_##i); \ (tbl)[ind].color_ds[3] = (NVGPU_ZBC_CL_VAL_4_IND_##i); \
(tbl)[ind].color_l2[0] = (NVGPU_ZBC_CL_L2_R_##i); \ (tbl)[ind].color_l2[0] = (NVGPU_ZBC_CL_VAL_1_IND_##i); \
(tbl)[ind].color_l2[1] = (NVGPU_ZBC_CL_L2_G_##i); \ (tbl)[ind].color_l2[1] = (NVGPU_ZBC_CL_VAL_2_IND_##i); \
(tbl)[ind].color_l2[2] = (NVGPU_ZBC_CL_L2_B_##i); \ (tbl)[ind].color_l2[2] = (NVGPU_ZBC_CL_VAL_3_IND_##i); \
(tbl)[ind].color_l2[3] = (NVGPU_ZBC_CL_L2_A_##i); \ (tbl)[ind].color_l2[3] = (NVGPU_ZBC_CL_VAL_4_IND_##i); \
(tbl)[ind].format = (NVGPU_ZBC_CL_FMT_##i); \
(tbl)[ind].ref_cnt = nvgpu_safe_add_u32((tbl)[ind].ref_cnt, 1U);\ (tbl)[ind].ref_cnt = nvgpu_safe_add_u32((tbl)[ind].ref_cnt, 1U);\
ind = nvgpu_safe_add_u32(ind, 1U); \ ind = nvgpu_safe_add_u32(ind, 1U); \
} }
#define NVGPU_ZBC_CL_DS_R_1 0x00000000U #define NVGPU_ZBC_CL_VAL_1_IND_1 0xff000000U
#define NVGPU_ZBC_CL_DS_G_1 0x00000000U #define NVGPU_ZBC_CL_VAL_2_IND_1 0xff000000U
#define NVGPU_ZBC_CL_DS_B_1 0x00000000U #define NVGPU_ZBC_CL_VAL_3_IND_1 0xff000000U
#define NVGPU_ZBC_CL_DS_A_1 0x3f800000U #define NVGPU_ZBC_CL_VAL_4_IND_1 0xff000000U
#define NVGPU_ZBC_CL_L2_R_1 0xff000000U
#define NVGPU_ZBC_CL_L2_G_1 0xff000000U
#define NVGPU_ZBC_CL_L2_B_1 0xff000000U
#define NVGPU_ZBC_CL_L2_A_1 0xff000000U
#define NVGPU_ZBC_CL_FMT_1 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_2 0x00000000U #define NVGPU_ZBC_CL_VAL_1_IND_2 0x00000000U
#define NVGPU_ZBC_CL_DS_G_2 0x00000000U #define NVGPU_ZBC_CL_VAL_2_IND_2 0x00000000U
#define NVGPU_ZBC_CL_DS_B_2 0x00000000U #define NVGPU_ZBC_CL_VAL_3_IND_2 0x00000000U
#define NVGPU_ZBC_CL_DS_A_2 0x00000000U #define NVGPU_ZBC_CL_VAL_4_IND_2 0x00000000U
#define NVGPU_ZBC_CL_L2_R_2 0x00000000U
#define NVGPU_ZBC_CL_L2_G_2 0x00000000U
#define NVGPU_ZBC_CL_L2_B_2 0x00000000U
#define NVGPU_ZBC_CL_L2_A_2 0x00000000U
#define NVGPU_ZBC_CL_FMT_2 GR_ZBC_TRANSPARENT_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_3 0x3f800000U #define NVGPU_ZBC_CL_VAL_1_IND_3 0xffffffffU
#define NVGPU_ZBC_CL_DS_G_3 0x3f800000U #define NVGPU_ZBC_CL_VAL_2_IND_3 0xffffffffU
#define NVGPU_ZBC_CL_DS_B_3 0x3f800000U #define NVGPU_ZBC_CL_VAL_3_IND_3 0xffffffffU
#define NVGPU_ZBC_CL_DS_A_3 0x3f800000U #define NVGPU_ZBC_CL_VAL_4_IND_3 0xffffffffU
#define NVGPU_ZBC_CL_L2_R_3 0xffffffffU
#define NVGPU_ZBC_CL_L2_G_3 0xffffffffU
#define NVGPU_ZBC_CL_L2_B_3 0xffffffffU
#define NVGPU_ZBC_CL_L2_A_3 0xffffffffU
#define NVGPU_ZBC_CL_FMT_3 GR_ZBC_SOLID_WHITE_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_4 0x001a8000U #ifndef CONFIG_NVGPU_NON_FUSA
#define NVGPU_ZBC_CL_DS_G_4 0x001b8000U #define NVGPU_ZBC_CL_VAL_1_IND_4 0x7f000000U
#define NVGPU_ZBC_CL_DS_B_4 0x001c8000U #define NVGPU_ZBC_CL_VAL_2_IND_4 0x7f000000U
#define NVGPU_ZBC_CL_DS_A_4 0x001d8000U #define NVGPU_ZBC_CL_VAL_3_IND_4 0x7f000000U
#define NVGPU_ZBC_CL_L2_R_4 0x001e8000U #define NVGPU_ZBC_CL_VAL_4_IND_4 0x7f000000U
#define NVGPU_ZBC_CL_L2_G_4 0x001f8000U
#define NVGPU_ZBC_CL_L2_B_4 0x00218000U
#define NVGPU_ZBC_CL_L2_A_4 0x00228000U
#define NVGPU_ZBC_CL_FMT_4 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_5 0xbadfU #define NVGPU_ZBC_CL_VAL_1_IND_5 0x40000000U
#define NVGPU_ZBC_CL_DS_G_5 0x00238000U #define NVGPU_ZBC_CL_VAL_2_IND_5 0x40000000U
#define NVGPU_ZBC_CL_DS_B_5 0x00248000U #define NVGPU_ZBC_CL_VAL_3_IND_5 0x40000000U
#define NVGPU_ZBC_CL_DS_A_5 0x00258000U #define NVGPU_ZBC_CL_VAL_4_IND_5 0x40000000U
#define NVGPU_ZBC_CL_L2_R_5 0x00268000U
#define NVGPU_ZBC_CL_L2_G_5 0x00278000U
#define NVGPU_ZBC_CL_L2_B_5 0x00288000U
#define NVGPU_ZBC_CL_L2_A_5 0x00298000U
#define NVGPU_ZBC_CL_FMT_5 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_6 0x002a8000U #define NVGPU_ZBC_CL_VAL_1_IND_6 0xbf000000U
#define NVGPU_ZBC_CL_DS_G_6 0x002b8000U #define NVGPU_ZBC_CL_VAL_2_IND_6 0xbf000000U
#define NVGPU_ZBC_CL_DS_B_6 0x002c8000U #define NVGPU_ZBC_CL_VAL_3_IND_6 0xbf000000U
#define NVGPU_ZBC_CL_DS_A_6 0x002d8000U #define NVGPU_ZBC_CL_VAL_4_IND_6 0xbf000000U
#define NVGPU_ZBC_CL_L2_R_6 0x002e8000U
#define NVGPU_ZBC_CL_L2_G_6 0x002f8000U
#define NVGPU_ZBC_CL_L2_B_6 0x00318000U
#define NVGPU_ZBC_CL_L2_A_6 0xbadf0U
#define NVGPU_ZBC_CL_FMT_6 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_7 0x00328000U #define NVGPU_ZBC_CL_VAL_1_IND_7 0xff0000ffU
#define NVGPU_ZBC_CL_DS_G_7 0x00338000U #define NVGPU_ZBC_CL_VAL_2_IND_7 0xff0000ffU
#define NVGPU_ZBC_CL_DS_B_7 0x00348000U #define NVGPU_ZBC_CL_VAL_3_IND_7 0xff0000ffU
#define NVGPU_ZBC_CL_DS_A_7 0x00358000U #define NVGPU_ZBC_CL_VAL_4_IND_7 0xff0000ffU
#define NVGPU_ZBC_CL_L2_R_7 0x00368000U
#define NVGPU_ZBC_CL_L2_G_7 0x00378000U
#define NVGPU_ZBC_CL_L2_B_7 0x00388000U
#define NVGPU_ZBC_CL_L2_A_7 0x00398000U
#define NVGPU_ZBC_CL_FMT_7 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_8 0x003a8000U #define NVGPU_ZBC_CL_VAL_1_IND_8 0x00ffffffU
#define NVGPU_ZBC_CL_DS_G_8 0x003b8000U #define NVGPU_ZBC_CL_VAL_2_IND_8 0x00ffffffU
#define NVGPU_ZBC_CL_DS_B_8 0x003c8000U #define NVGPU_ZBC_CL_VAL_3_IND_8 0x00ffffffU
#define NVGPU_ZBC_CL_DS_A_8 0x003d8000U #define NVGPU_ZBC_CL_VAL_4_IND_8 0x00ffffffU
#define NVGPU_ZBC_CL_L2_R_8 0x003e8000U
#define NVGPU_ZBC_CL_L2_G_8 0x003f8000U
#define NVGPU_ZBC_CL_L2_B_8 0x00418000U
#define NVGPU_ZBC_CL_L2_A_8 0x00428000U
#define NVGPU_ZBC_CL_FMT_8 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_9 0x00438000U #define NVGPU_ZBC_CL_VAL_1_IND_9 0x7fffffffU
#define NVGPU_ZBC_CL_DS_G_9 0x00448000U #define NVGPU_ZBC_CL_VAL_2_IND_9 0x7fffffffU
#define NVGPU_ZBC_CL_DS_B_9 0x00458000U #define NVGPU_ZBC_CL_VAL_3_IND_9 0x7fffffffU
#define NVGPU_ZBC_CL_DS_A_9 0x00468000U #define NVGPU_ZBC_CL_VAL_4_IND_9 0x7fffffffU
#define NVGPU_ZBC_CL_L2_R_9 0x00478000U
#define NVGPU_ZBC_CL_L2_G_9 0x00488000U
#define NVGPU_ZBC_CL_L2_B_9 0x00498000U
#define NVGPU_ZBC_CL_L2_A_9 0x004a8000U
#define NVGPU_ZBC_CL_FMT_9 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_10 0x004b8000U #define NVGPU_ZBC_CL_VAL_1_IND_10 0xffff0000U
#define NVGPU_ZBC_CL_DS_G_10 0x004c8000U #define NVGPU_ZBC_CL_VAL_2_IND_10 0xffff0000U
#define NVGPU_ZBC_CL_DS_B_10 0x004d8000U #define NVGPU_ZBC_CL_VAL_3_IND_10 0xffff0000U
#define NVGPU_ZBC_CL_DS_A_10 0x004e8000U #define NVGPU_ZBC_CL_VAL_4_IND_10 0xffff0000U
#define NVGPU_ZBC_CL_L2_R_10 0x004f8000U
#define NVGPU_ZBC_CL_L2_G_10 0x00518000U
#define NVGPU_ZBC_CL_L2_B_10 0x00528000U
#define NVGPU_ZBC_CL_L2_A_10 0x00538000U
#define NVGPU_ZBC_CL_FMT_10 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_11 0x00548000U #define NVGPU_ZBC_CL_VAL_1_IND_11 0x00000000U
#define NVGPU_ZBC_CL_DS_G_11 0x00558000U #define NVGPU_ZBC_CL_VAL_2_IND_11 0x3c000000U
#define NVGPU_ZBC_CL_DS_B_11 0x00568000U #define NVGPU_ZBC_CL_VAL_3_IND_11 0x00000000U
#define NVGPU_ZBC_CL_DS_A_11 0x00578000U #define NVGPU_ZBC_CL_VAL_4_IND_11 0x3c000000U
#define NVGPU_ZBC_CL_L2_R_11 0x00588000U
#define NVGPU_ZBC_CL_L2_G_11 0x00598000U
#define NVGPU_ZBC_CL_L2_B_11 0x005a8000U
#define NVGPU_ZBC_CL_L2_A_11 0x005b8000U
#define NVGPU_ZBC_CL_FMT_11 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_12 0x005c8000U #define NVGPU_ZBC_CL_VAL_1_IND_12 0x00000000U
#define NVGPU_ZBC_CL_DS_G_12 0x005d8000U #define NVGPU_ZBC_CL_VAL_2_IND_12 0x38000000U
#define NVGPU_ZBC_CL_DS_B_12 0x005e8000U #define NVGPU_ZBC_CL_VAL_3_IND_12 0x00000000U
#define NVGPU_ZBC_CL_DS_A_12 0x005f8000U #define NVGPU_ZBC_CL_VAL_4_IND_12 0x38000000U
#define NVGPU_ZBC_CL_L2_R_12 0x00618000U
#define NVGPU_ZBC_CL_L2_G_12 0x00628000U
#define NVGPU_ZBC_CL_L2_B_12 0x00638000U
#define NVGPU_ZBC_CL_L2_A_12 0x00648000U
#define NVGPU_ZBC_CL_FMT_12 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_13 0x00658000U #define NVGPU_ZBC_CL_VAL_1_IND_13 0x00000000U
#define NVGPU_ZBC_CL_DS_G_13 0x00668000U #define NVGPU_ZBC_CL_VAL_2_IND_13 0x34000000U
#define NVGPU_ZBC_CL_DS_B_13 0x00678000U #define NVGPU_ZBC_CL_VAL_3_IND_13 0x00000000U
#define NVGPU_ZBC_CL_DS_A_13 0x00688000U #define NVGPU_ZBC_CL_VAL_4_IND_13 0x34000000U
#define NVGPU_ZBC_CL_L2_R_13 0x00698000U
#define NVGPU_ZBC_CL_L2_G_13 0x006a8000U
#define NVGPU_ZBC_CL_L2_B_13 0x006b8000U
#define NVGPU_ZBC_CL_L2_A_13 0x006c8000U
#define NVGPU_ZBC_CL_FMT_13 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_14 0x006d8000U #define NVGPU_ZBC_CL_VAL_1_IND_14 0x00000000U
#define NVGPU_ZBC_CL_DS_G_14 0x006e8000U #define NVGPU_ZBC_CL_VAL_2_IND_14 0x3a000000U
#define NVGPU_ZBC_CL_DS_B_14 0x006f8000U #define NVGPU_ZBC_CL_VAL_3_IND_14 0x00000000U
#define NVGPU_ZBC_CL_DS_A_14 0x00718000U #define NVGPU_ZBC_CL_VAL_4_IND_14 0x3a000000U
#define NVGPU_ZBC_CL_L2_R_14 0x00728000U
#define NVGPU_ZBC_CL_L2_G_14 0x00738000U
#define NVGPU_ZBC_CL_L2_B_14 0x00748000U
#define NVGPU_ZBC_CL_L2_A_14 0x00758000U
#define NVGPU_ZBC_CL_FMT_14 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_15 0xbadfU #define NVGPU_ZBC_CL_VAL_1_IND_15 0x00000000U
#define NVGPU_ZBC_CL_DS_G_15 0x00768000U #define NVGPU_ZBC_CL_VAL_2_IND_15 0x3c003c00U
#define NVGPU_ZBC_CL_DS_B_15 0x00778000U #define NVGPU_ZBC_CL_VAL_3_IND_15 0x00000000U
#define NVGPU_ZBC_CL_DS_A_15 0x00788000U #define NVGPU_ZBC_CL_VAL_4_IND_15 0x3c003c00U
#define NVGPU_ZBC_CL_L2_R_15 0xbadfU
#define NVGPU_ZBC_CL_L2_G_15 0x00798000U
#define NVGPU_ZBC_CL_L2_B_15 0x007a8000U
#define NVGPU_ZBC_CL_L2_A_15 0x007b8000U
#define NVGPU_ZBC_CL_FMT_15 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_16 0x007c8000U #define NVGPU_ZBC_CL_VAL_1_IND_16 0x3c003c00U
#define NVGPU_ZBC_CL_DS_G_16 0x007d8000U #define NVGPU_ZBC_CL_VAL_2_IND_16 0x3c003c00U
#define NVGPU_ZBC_CL_DS_B_16 0x007e8000U #define NVGPU_ZBC_CL_VAL_3_IND_16 0x3c003c00U
#define NVGPU_ZBC_CL_DS_A_16 0x007f8000U #define NVGPU_ZBC_CL_VAL_4_IND_16 0x3c003c00U
#define NVGPU_ZBC_CL_L2_R_16 0x00818000U
#define NVGPU_ZBC_CL_L2_G_16 0x00828000U
#define NVGPU_ZBC_CL_L2_B_16 0x00838000U
#define NVGPU_ZBC_CL_L2_A_16 0x00848000U
#define NVGPU_ZBC_CL_FMT_16 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_17 0x00858000U #define NVGPU_ZBC_CL_VAL_1_IND_17 0x3c003c00U
#define NVGPU_ZBC_CL_DS_G_17 0x00868000U #define NVGPU_ZBC_CL_VAL_2_IND_17 0x00003c00U
#define NVGPU_ZBC_CL_DS_B_17 0x00878000U #define NVGPU_ZBC_CL_VAL_3_IND_17 0x3c003c00U
#define NVGPU_ZBC_CL_DS_A_17 0x00888000U #define NVGPU_ZBC_CL_VAL_4_IND_17 0x00003c00U
#define NVGPU_ZBC_CL_L2_R_17 0x00898000U
#define NVGPU_ZBC_CL_L2_G_17 0x008a8000U
#define NVGPU_ZBC_CL_L2_B_17 0x008b8000U
#define NVGPU_ZBC_CL_L2_A_17 0x008c8000U
#define NVGPU_ZBC_CL_FMT_17 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_18 0x008d8000U #define NVGPU_ZBC_CL_VAL_1_IND_18 0x3c003c00U
#define NVGPU_ZBC_CL_DS_G_18 0x008e8000U #define NVGPU_ZBC_CL_VAL_2_IND_18 0x38003c00U
#define NVGPU_ZBC_CL_DS_B_18 0x008f8000U #define NVGPU_ZBC_CL_VAL_3_IND_18 0x3c003c00U
#define NVGPU_ZBC_CL_DS_A_18 0x00918000U #define NVGPU_ZBC_CL_VAL_4_IND_18 0x38003c00U
#define NVGPU_ZBC_CL_L2_R_18 0x00928000U
#define NVGPU_ZBC_CL_L2_G_18 0x00938000U
#define NVGPU_ZBC_CL_L2_B_18 0x00948000U
#define NVGPU_ZBC_CL_L2_A_18 0x00958000U
#define NVGPU_ZBC_CL_FMT_18 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_19 0x00968000U #define NVGPU_ZBC_CL_VAL_1_IND_19 0x00000000U
#define NVGPU_ZBC_CL_DS_G_19 0x00978000U #define NVGPU_ZBC_CL_VAL_2_IND_19 0x00000000U
#define NVGPU_ZBC_CL_DS_B_19 0x00988000U #define NVGPU_ZBC_CL_VAL_3_IND_19 0x00000000U
#define NVGPU_ZBC_CL_DS_A_19 0x00998000U #define NVGPU_ZBC_CL_VAL_4_IND_19 0x3f800000U
#define NVGPU_ZBC_CL_L2_R_19 0x009a8000U
#define NVGPU_ZBC_CL_L2_G_19 0x009b8000U
#define NVGPU_ZBC_CL_L2_B_19 0x009c8000U
#define NVGPU_ZBC_CL_L2_A_19 0x009d8000U
#define NVGPU_ZBC_CL_FMT_19 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_20 0x009e8000U #define NVGPU_ZBC_CL_VAL_1_IND_20 0x00000000U
#define NVGPU_ZBC_CL_DS_G_20 0x009f8000U #define NVGPU_ZBC_CL_VAL_2_IND_20 0x00000000U
#define NVGPU_ZBC_CL_DS_B_20 0x00a18000U #define NVGPU_ZBC_CL_VAL_3_IND_20 0x00000000U
#define NVGPU_ZBC_CL_DS_A_20 0x00a28000U #define NVGPU_ZBC_CL_VAL_4_IND_20 0x3f000000U
#define NVGPU_ZBC_CL_L2_R_20 0x00a38000U
#define NVGPU_ZBC_CL_L2_G_20 0x00a48000U
#define NVGPU_ZBC_CL_L2_B_20 0x00a58000U
#define NVGPU_ZBC_CL_L2_A_20 0x00a68000U
#define NVGPU_ZBC_CL_FMT_20 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_21 0x00a78000U #define NVGPU_ZBC_CL_VAL_1_IND_21 0x00000000U
#define NVGPU_ZBC_CL_DS_G_21 0x00a88000U #define NVGPU_ZBC_CL_VAL_2_IND_21 0x00000000U
#define NVGPU_ZBC_CL_DS_B_21 0x00a98000U #define NVGPU_ZBC_CL_VAL_3_IND_21 0x00000000U
#define NVGPU_ZBC_CL_DS_A_21 0x00aa8000U #define NVGPU_ZBC_CL_VAL_4_IND_21 0x3e800000U
#define NVGPU_ZBC_CL_L2_R_21 0x00ab8000U
#define NVGPU_ZBC_CL_L2_G_21 0x00ac8000U
#define NVGPU_ZBC_CL_L2_B_21 0x00ad8000U
#define NVGPU_ZBC_CL_L2_A_21 0x00b18000U
#define NVGPU_ZBC_CL_FMT_21 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_22 0x00b28000U #define NVGPU_ZBC_CL_VAL_1_IND_22 0x00000000U
#define NVGPU_ZBC_CL_DS_G_22 0x00b38000U #define NVGPU_ZBC_CL_VAL_2_IND_22 0x00000000U
#define NVGPU_ZBC_CL_DS_B_22 0x00b48000U #define NVGPU_ZBC_CL_VAL_3_IND_22 0x00000000U
#define NVGPU_ZBC_CL_DS_A_22 0x00b58000U #define NVGPU_ZBC_CL_VAL_4_IND_22 0x3f400000U
#define NVGPU_ZBC_CL_L2_R_22 0x00b68000U
#define NVGPU_ZBC_CL_L2_G_22 0x00b78000U
#define NVGPU_ZBC_CL_L2_B_22 0x00b88000U
#define NVGPU_ZBC_CL_L2_A_22 0x00b98000U
#define NVGPU_ZBC_CL_FMT_22 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_23 0x00ba8000U #define NVGPU_ZBC_CL_VAL_1_IND_23 0x00000000U
#define NVGPU_ZBC_CL_DS_G_23 0x00bb8000U #define NVGPU_ZBC_CL_VAL_2_IND_23 0x00000000U
#define NVGPU_ZBC_CL_DS_B_23 0x00bc8000U #define NVGPU_ZBC_CL_VAL_3_IND_23 0x3f800000U
#define NVGPU_ZBC_CL_DS_A_23 0x00bd8000U #define NVGPU_ZBC_CL_VAL_4_IND_23 0x3f800000U
#define NVGPU_ZBC_CL_L2_R_23 0x00be8000U
#define NVGPU_ZBC_CL_L2_G_23 0x00bf8000U
#define NVGPU_ZBC_CL_L2_B_23 0x00c18000U
#define NVGPU_ZBC_CL_L2_A_23 0x00c28000U
#define NVGPU_ZBC_CL_FMT_23 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_24 0x00c38000U #define NVGPU_ZBC_CL_VAL_1_IND_24 0x3f800000U
#define NVGPU_ZBC_CL_DS_G_24 0x00c48000U #define NVGPU_ZBC_CL_VAL_2_IND_24 0x3f800000U
#define NVGPU_ZBC_CL_DS_B_24 0x00c58000U #define NVGPU_ZBC_CL_VAL_3_IND_24 0x3f800000U
#define NVGPU_ZBC_CL_DS_A_24 0x00c68000U #define NVGPU_ZBC_CL_VAL_4_IND_24 0x3f800000U
#define NVGPU_ZBC_CL_L2_R_24 0x00c78000U
#define NVGPU_ZBC_CL_L2_G_24 0x00c88000U
#define NVGPU_ZBC_CL_L2_B_24 0x00c98000U
#define NVGPU_ZBC_CL_L2_A_24 0x00ca8000U
#define NVGPU_ZBC_CL_FMT_24 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_25 0x00cb8000U #define NVGPU_ZBC_CL_VAL_1_IND_25 0x3f800000U
#define NVGPU_ZBC_CL_DS_G_25 0x00cc8000U #define NVGPU_ZBC_CL_VAL_2_IND_25 0x3f800000U
#define NVGPU_ZBC_CL_DS_B_25 0x00cd8000U #define NVGPU_ZBC_CL_VAL_3_IND_25 0x3f800000U
#define NVGPU_ZBC_CL_DS_A_25 0x00d18000U #define NVGPU_ZBC_CL_VAL_4_IND_25 0x00000000U
#define NVGPU_ZBC_CL_L2_R_25 0x00d28000U
#define NVGPU_ZBC_CL_L2_G_25 0x00d18000U
#define NVGPU_ZBC_CL_L2_B_25 0x00d28000U
#define NVGPU_ZBC_CL_L2_A_25 0x00d38000U
#define NVGPU_ZBC_CL_FMT_25 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_26 0x00d48000U #define NVGPU_ZBC_CL_VAL_1_IND_26 0x3f800000U
#define NVGPU_ZBC_CL_DS_G_26 0x00d58000U #define NVGPU_ZBC_CL_VAL_2_IND_26 0x3f800000U
#define NVGPU_ZBC_CL_DS_B_26 0x00d68000U #define NVGPU_ZBC_CL_VAL_3_IND_26 0x3f800000U
#define NVGPU_ZBC_CL_DS_A_26 0x00d78000U #define NVGPU_ZBC_CL_VAL_4_IND_26 0x3f000000U
#define NVGPU_ZBC_CL_L2_R_26 0x00d88000U #endif
#define NVGPU_ZBC_CL_L2_G_26 0x00d98000U
#define NVGPU_ZBC_CL_L2_B_26 0x00da8000U
#define NVGPU_ZBC_CL_L2_A_26 0x00db8000U
#define NVGPU_ZBC_CL_FMT_26 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_27 0x00dc8000U
#define NVGPU_ZBC_CL_DS_G_27 0x00dd8000U
#define NVGPU_ZBC_CL_DS_B_27 0x00de8000U
#define NVGPU_ZBC_CL_DS_A_27 0x00df8000U
#define NVGPU_ZBC_CL_L2_R_27 0x00e18000U
#define NVGPU_ZBC_CL_L2_G_27 0x00e28000U
#define NVGPU_ZBC_CL_L2_B_27 0x00e38000U
#define NVGPU_ZBC_CL_L2_A_27 0x00e48000U
#define NVGPU_ZBC_CL_FMT_27 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_28 0x00e58000U
#define NVGPU_ZBC_CL_DS_G_28 0x00e68000U
#define NVGPU_ZBC_CL_DS_B_28 0x00e78000U
#define NVGPU_ZBC_CL_DS_A_28 0x00e88000U
#define NVGPU_ZBC_CL_L2_R_28 0x00e98000U
#define NVGPU_ZBC_CL_L2_G_28 0x00ea8000U
#define NVGPU_ZBC_CL_L2_B_28 0x00eb8000U
#define NVGPU_ZBC_CL_L2_A_28 0x00ec8000U
#define NVGPU_ZBC_CL_FMT_28 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_29 0x00f18000U
#define NVGPU_ZBC_CL_DS_G_29 0x00f28000U
#define NVGPU_ZBC_CL_DS_B_29 0x00f38000U
#define NVGPU_ZBC_CL_DS_A_29 0x00f48000U
#define NVGPU_ZBC_CL_L2_R_29 0x00f58000U
#define NVGPU_ZBC_CL_L2_G_29 0x00f68000U
#define NVGPU_ZBC_CL_L2_B_29 0x00f78000U
#define NVGPU_ZBC_CL_L2_A_29 0x00f88000U
#define NVGPU_ZBC_CL_FMT_29 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_CL_DS_R_30 0x0ae18000U
#define NVGPU_ZBC_CL_DS_G_30 0x0ae28000U
#define NVGPU_ZBC_CL_DS_B_30 0x0ae38000U
#define NVGPU_ZBC_CL_DS_A_30 0x0ae48000U
#define NVGPU_ZBC_CL_L2_R_30 0xbae18000U
#define NVGPU_ZBC_CL_L2_G_30 0xbae28000U
#define NVGPU_ZBC_CL_L2_B_30 0xbae38000U
#define NVGPU_ZBC_CL_L2_A_30 0xbae48000U
#define NVGPU_ZBC_CL_FMT_30 GR_ZBC_SOLID_BLACK_COLOR_FMT
#define NVGPU_ZBC_SET_DEPTH_ATTR(tbl, i) \ #define NVGPU_ZBC_SET_DEPTH_ATTR(tbl, i) \
{ \ { \
@@ -376,9 +206,4 @@ void ga10b_gr_zbc_load_static_table(struct gk20a *g,
#define NVGPU_ZBC_SCIL_FMT_2 GR_ZBC_STENCIL_CLEAR_FMT_U8 #define NVGPU_ZBC_SCIL_FMT_2 GR_ZBC_STENCIL_CLEAR_FMT_U8
#define NVGPU_ZBC_SCIL_3 0xffU #define NVGPU_ZBC_SCIL_3 0xffU
#define NVGPU_ZBC_SCIL_FMT_3 GR_ZBC_STENCIL_CLEAR_FMT_U8 #define NVGPU_ZBC_SCIL_FMT_3 GR_ZBC_STENCIL_CLEAR_FMT_U8
#define NVGPU_ZBC_SCIL_4 0x3f800000U
#define NVGPU_ZBC_SCIL_FMT_4 GR_ZBC_STENCIL_CLEAR_FMT_U8
#define NVGPU_ZBC_SCIL_5 0x0ae28000U
#define NVGPU_ZBC_SCIL_FMT_5 GR_ZBC_STENCIL_CLEAR_FMT_U8
#endif
#endif /* ZBC_GA10B_H */ #endif /* ZBC_GA10B_H */

4
drivers/gpu/nvgpu/hal/init/hal_ga10b.c
View File

@@ -567,11 +567,7 @@ static const struct gops_gr_setup ga10b_ops_gr_setup = {
#ifdef CONFIG_NVGPU_GRAPHICS #ifdef CONFIG_NVGPU_GRAPHICS
static const struct gops_gr_zbc ga10b_ops_gr_zbc = { static const struct gops_gr_zbc ga10b_ops_gr_zbc = {
.add_color = ga10b_gr_zbc_add_color, .add_color = ga10b_gr_zbc_add_color,
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
.load_default_sw_table = gm20b_gr_zbc_load_default_sw_table,
#else
.load_default_sw_table = ga10b_gr_zbc_load_static_table, .load_default_sw_table = ga10b_gr_zbc_load_static_table,
#endif
.add_depth = gp10b_gr_zbc_add_depth, .add_depth = gp10b_gr_zbc_add_depth,
.set_table = nvgpu_gr_zbc_set_table, .set_table = nvgpu_gr_zbc_set_table,
.query_table = nvgpu_gr_zbc_query_table, .query_table = nvgpu_gr_zbc_query_table,