From 98f27acf083c79bd6146204f783f0ded68ebc47d Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Sun, 9 Jun 2019 08:27:54 -0700 Subject: [PATCH] gpu: nvgpu: fix CERT-C errors in hal ltc driver Fixed CERT-C issues in hal ltc driver by replacing arithmetic operations with nvgpu safe ops. JIRA NVGPU-3623 Change-Id: I0c6840ac1ee174c509e14e18e89cbacb0fdb650b Signed-off-by: Seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/2133290 Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: Alex Waterman Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: Nitin Kumbhar GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c | 45 +++++++++++++++++---------- drivers/gpu/nvgpu/hal/ltc/ltc_gp10b.c | 9 ++++-- drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c | 14 +++++---- 3 files changed, 43 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c b/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c index 21e0c285a..9870b485f 100644 --- a/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include @@ -117,8 +118,9 @@ void gm20b_flush_ltc(struct gk20a *g) } do { - u32 cmgmt1 = (u32)(ltc_ltc0_ltss_tstg_cmgmt1_r() + - (ltc * ltc_stride)); + u32 cmgmt1 = nvgpu_safe_add_u32( + ltc_ltc0_ltss_tstg_cmgmt1_r(), + nvgpu_safe_mult_u32(ltc, ltc_stride)); op_pending = gk20a_readl(g, cmgmt1); is_clean_pending_set = (op_pending & ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f()) != 0U; @@ -149,8 +151,9 @@ void gm20b_flush_ltc(struct gk20a *g) } do { - u32 cmgmt0 = (u32)(ltc_ltc0_ltss_tstg_cmgmt0_r() + - (ltc * ltc_stride)); + u32 cmgmt0 = nvgpu_safe_add_u32( + ltc_ltc0_ltss_tstg_cmgmt0_r(), + nvgpu_safe_mult_u32(ltc, ltc_stride)); op_pending = gk20a_readl(g, cmgmt0); is_invalidate_pending_set = (op_pending & ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f()) != 0U; @@ -197,8 +200,9 @@ u64 gm20b_determine_L2_size_bytes(struct gk20a *g) /* chip-specific values */ lts_per_ltc = 2U; bytes_per_line = 128U; - cache_size = active_ltcs * (u64)lts_per_ltc * ways * - (u64) sets * bytes_per_line; + cache_size = nvgpu_safe_mult_u64(nvgpu_safe_mult_u64( + nvgpu_safe_mult_u64(active_ltcs, lts_per_ltc), ways), + nvgpu_safe_mult_u64(sets, bytes_per_line)); return cache_size; } @@ -270,7 +274,7 @@ bool gm20b_ltc_is_ltcs_ltss_addr(struct gk20a *g, u32 addr) u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); return (addr >= ltc_shared_base) && - (addr < (ltc_shared_base + lts_stride)); + (addr < nvgpu_safe_add_u32(ltc_shared_base, lts_stride)); } bool gm20b_ltc_is_ltcn_ltss_addr(struct gk20a *g, u32 addr) @@ -279,7 +283,7 @@ bool gm20b_ltc_is_ltcn_ltss_addr(struct gk20a *g, u32 addr) u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); u32 addr_mask = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE) - 1U; u32 base_offset = lts_shared_base & addr_mask; - u32 end_offset = base_offset + lts_stride; + u32 end_offset = nvgpu_safe_add_u32(base_offset, lts_stride); return (!gm20b_ltc_is_ltcs_ltss_addr(g, addr)) && ((addr & addr_mask) >= base_offset) && @@ -295,11 +299,17 @@ static void gm20b_ltc_update_ltc_lts_addr(struct gk20a *g, u32 addr, u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE); u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); - for (lts_num = 0; lts_num < num_ltc_slices; lts_num++) { - priv_addr_table[index++] = ltc_ltc0_lts0_v() + - ltc_num * ltc_stride + - lts_num * lts_stride + - (addr & (lts_stride - 1U)); + for (lts_num = 0; lts_num < num_ltc_slices; + lts_num = nvgpu_safe_add_u32(lts_num, 1U)) { + priv_addr_table[index] = nvgpu_safe_add_u32( + ltc_ltc0_lts0_v(), + nvgpu_safe_add_u32( + nvgpu_safe_add_u32( + nvgpu_safe_mult_u32(ltc_num, ltc_stride), + nvgpu_safe_mult_u32(lts_num, lts_stride)), + (addr & nvgpu_safe_sub_u32( + lts_stride, 1U)))); + index = nvgpu_safe_add_u32(index, 1U); } *priv_addr_table_index = index; @@ -315,8 +325,10 @@ void gm20b_ltc_split_lts_broadcast_addr(struct gk20a *g, u32 addr, u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE); for (i = 0; i < num_ltc; i++) { - start = pltcg_base + i * ltc_stride; - if ((addr >= start) && (addr < (start + ltc_stride))) { + start = nvgpu_safe_add_u32(pltcg_base, + nvgpu_safe_mult_u32(i, ltc_stride)); + if ((addr >= start) && (addr < nvgpu_safe_add_u32(start, + ltc_stride))) { ltc_num = i; break; } @@ -332,7 +344,8 @@ void gm20b_ltc_split_ltc_broadcast_addr(struct gk20a *g, u32 addr, u32 num_ltc = g->ltc->ltc_count; u32 ltc_num; - for (ltc_num = 0; ltc_num < num_ltc; ltc_num++) { + for (ltc_num = 0; ltc_num < num_ltc; ltc_num = + nvgpu_safe_add_u32(ltc_num, 1U)) { gm20b_ltc_update_ltc_lts_addr(g, addr, ltc_num, priv_addr_table, priv_addr_table_index); } diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_gp10b.c b/drivers/gpu/nvgpu/hal/ltc/ltc_gp10b.c index 84da27c74..dcd0e4083 100644 --- a/drivers/gpu/nvgpu/hal/ltc/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/hal/ltc/ltc_gp10b.c @@ -26,6 +26,7 @@ #include #include #include +#include #include @@ -41,9 +42,11 @@ u64 gp10b_determine_L2_size_bytes(struct gk20a *g) tmp = gk20a_readl(g, ltc_ltc0_lts0_tstg_info_1_r()); - ret = (u64)g->ltc->ltc_count * - ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(tmp) * 1024U * - (u64)ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(tmp); + ret = nvgpu_safe_mult_u64(g->ltc->ltc_count, + nvgpu_safe_mult_u64( + nvgpu_safe_mult_u64( + ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(tmp), 1024U), + ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(tmp))); nvgpu_log(g, gpu_dbg_info, "L2 size: %llu\n", ret); diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c b/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c index b656bd05c..dc914cdb2 100644 --- a/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "ltc_gv11b.h" @@ -59,12 +60,13 @@ struct nvgpu_hw_err_inject_info_desc * gv11b_ltc_get_err_desc(struct gk20a *g) int gv11b_ltc_inject_ecc_error(struct gk20a *g, struct nvgpu_hw_err_inject_info *err, u32 error_info) { - unsigned int ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE); - unsigned int lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); - unsigned int ltc = (error_info & 0xFF00U) >> 8U; - unsigned int lts = (error_info & 0xFFU); - unsigned int reg_addr = err->get_reg_addr() + ltc * ltc_stride + - lts * lts_stride; + u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE); + u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); + u32 ltc = (error_info & 0xFF00U) >> 8U; + u32 lts = (error_info & 0xFFU); + u32 reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(), + nvgpu_safe_add_u32(nvgpu_safe_mult_u32(ltc, ltc_stride), + nvgpu_safe_mult_u32(lts, lts_stride))); nvgpu_info(g, "Injecting LTC fault %s for ltc: %d, lts: %d", err->name, ltc, lts);