diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h b/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h index a29b8f760..68081a91b 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h +++ b/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h @@ -20,8 +20,8 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef MC_GP10B_H -#define MC_GP10B_H +#ifndef NVGPU_MC_GP10B_H +#define NVGPU_MC_GP10B_H #include @@ -53,4 +53,4 @@ void mc_gp10b_intr_nonstall_resume(struct gk20a *g); void mc_gp10b_ltc_isr(struct gk20a *g); /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ -#endif +#endif /* NVGPU_MC_GP10B_H */ diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gv100.h b/drivers/gpu/nvgpu/hal/mc/mc_gv100.h index b11a65a36..4ffc4ad0c 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gv100.h +++ b/drivers/gpu/nvgpu/hal/mc/mc_gv100.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,8 +20,8 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef MC_GV100_H -#define MC_GV100_H +#ifndef NVGPU_MC_GV100_H +#define NVGPU_MC_GV100_H #include @@ -32,4 +32,4 @@ bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 engine_id, u32 *eng_intr_pending); u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit); -#endif +#endif /* NVGPU_MC_GV100_H */ diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gv11b.h b/drivers/gpu/nvgpu/hal/mc/mc_gv11b.h index 989ff16d6..55ef4f2cc 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gv11b.h +++ b/drivers/gpu/nvgpu/hal/mc/mc_gv11b.h @@ -20,8 +20,8 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef MC_GV11B_H -#define MC_GV11B_H +#ifndef NVGPU_MC_GV11B_H +#define NVGPU_MC_GV11B_H #include @@ -35,4 +35,4 @@ bool gv11b_mc_is_mmu_fault_pending(struct gk20a *g); bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0); /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ -#endif +#endif /* NVGPU_MC_GV11B_H */