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gpu: nvgpu: update pbdma HAL Ops method names

Browse Source 
HAL ops specific to pbdma are now updated to remove the word "pbdma"
from the function names in order to follow the convention
g->ops.pbdma.{function_name}()

Jira NVGPU-2950

Change-Id: I43ddb5c842b31c97da8fe35f4762de0478916702
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075438
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Debarshi Dutta
2019-04-01 12:49:59 +05:30
committed by mobile promotions
parent bd1ae5c9e1
commit 993fbd085e
14 changed files with 52 additions and 52 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -453,14 +453,14 @@ static const struct gpu_ops vgpu_gp10b_ops = {
},
.pbdma = {
.intr_enable = NULL,
.pbdma_acquire_val = gm20b_pbdma_acquire_val,
.get_pbdma_signature = gp10b_pbdma_get_signature,
.dump_pbdma_status = NULL,
.acquire_val = gm20b_pbdma_acquire_val,
.get_signature = gp10b_pbdma_get_signature,
.dump_status = NULL,
.handle_intr_0 = NULL,
.handle_intr_1 = gm20b_pbdma_handle_intr_1,
.handle_intr = gm20b_pbdma_handle_intr,
.read_pbdma_data = NULL,
.reset_pbdma_header = NULL,
.read_data = NULL,
.reset_header = NULL,
.device_fatal_0_intr_descs = NULL,
.channel_fatal_0_intr_descs = NULL,
.restartable_0_intr_descs = NULL,

10
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -540,14 +540,14 @@ static const struct gpu_ops vgpu_gv11b_ops = {
},
.pbdma = {
.intr_enable = NULL,
.pbdma_acquire_val = gm20b_pbdma_acquire_val,
.get_pbdma_signature = gp10b_pbdma_get_signature,
.dump_pbdma_status = NULL,
.acquire_val = gm20b_pbdma_acquire_val,
.get_signature = gp10b_pbdma_get_signature,
.dump_status = NULL,
.handle_intr_0 = NULL,
.handle_intr_1 = gv11b_pbdma_handle_intr_1,
.handle_intr = gm20b_pbdma_handle_intr,
.read_pbdma_data = NULL,
.reset_pbdma_header = NULL,
.read_data = NULL,
.reset_header = NULL,
.device_fatal_0_intr_descs = NULL,
.channel_fatal_0_intr_descs = NULL,
.restartable_0_intr_descs = NULL,

10
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -638,14 +638,14 @@ static const struct gpu_ops gm20b_ops = {
},
.pbdma = {
.intr_enable = gm20b_pbdma_intr_enable,
.pbdma_acquire_val = gm20b_pbdma_acquire_val,
.get_pbdma_signature = gm20b_pbdma_get_signature,
.dump_pbdma_status = gm20b_pbdma_dump_status,
.acquire_val = gm20b_pbdma_acquire_val,
.get_signature = gm20b_pbdma_get_signature,
.dump_status = gm20b_pbdma_dump_status,
.handle_intr_0 = gm20b_pbdma_handle_intr_0,
.handle_intr_1 = gm20b_pbdma_handle_intr_1,
.handle_intr = gm20b_pbdma_handle_intr,
.read_pbdma_data = gm20b_pbdma_read_data,
.reset_pbdma_header = gm20b_pbdma_reset_header,
.read_data = gm20b_pbdma_read_data,
.reset_header = gm20b_pbdma_reset_header,
.device_fatal_0_intr_descs =
gm20b_pbdma_device_fatal_0_intr_descs,
.channel_fatal_0_intr_descs =

10
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -725,14 +725,14 @@ static const struct gpu_ops gp10b_ops = {
},
.pbdma = {
.intr_enable = gm20b_pbdma_intr_enable,
.pbdma_acquire_val = gm20b_pbdma_acquire_val,
.get_pbdma_signature = gp10b_pbdma_get_signature,
.dump_pbdma_status = gm20b_pbdma_dump_status,
.acquire_val = gm20b_pbdma_acquire_val,
.get_signature = gp10b_pbdma_get_signature,
.dump_status = gm20b_pbdma_dump_status,
.handle_intr_0 = gm20b_pbdma_handle_intr_0,
.handle_intr_1 = gm20b_pbdma_handle_intr_1,
.handle_intr = gm20b_pbdma_handle_intr,
.read_pbdma_data = gm20b_pbdma_read_data,
.reset_pbdma_header = gm20b_pbdma_reset_header,
.read_data = gm20b_pbdma_read_data,
.reset_header = gm20b_pbdma_reset_header,
.device_fatal_0_intr_descs =
gm20b_pbdma_device_fatal_0_intr_descs,
.channel_fatal_0_intr_descs =

10
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -910,14 +910,14 @@ static const struct gpu_ops gv100_ops = {
},
.pbdma = {
.intr_enable = gv11b_pbdma_intr_enable,
.pbdma_acquire_val = gm20b_pbdma_acquire_val,
.get_pbdma_signature = gp10b_pbdma_get_signature,
.dump_pbdma_status = gm20b_pbdma_dump_status,
.acquire_val = gm20b_pbdma_acquire_val,
.get_signature = gp10b_pbdma_get_signature,
.dump_status = gm20b_pbdma_dump_status,
.handle_intr_0 = gv11b_pbdma_handle_intr_0,
.handle_intr_1 = gv11b_pbdma_handle_intr_1,
.handle_intr = gm20b_pbdma_handle_intr,
.read_pbdma_data = gm20b_pbdma_read_data,
.reset_pbdma_header = gm20b_pbdma_reset_header,
.read_data = gm20b_pbdma_read_data,
.reset_header = gm20b_pbdma_reset_header,
.device_fatal_0_intr_descs =
gm20b_pbdma_device_fatal_0_intr_descs,
.channel_fatal_0_intr_descs =

10
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -865,14 +865,14 @@ static const struct gpu_ops gv11b_ops = {
},
.pbdma = {
.intr_enable = gv11b_pbdma_intr_enable,
.pbdma_acquire_val = gm20b_pbdma_acquire_val,
.get_pbdma_signature = gp10b_pbdma_get_signature,
.dump_pbdma_status = gm20b_pbdma_dump_status,
.acquire_val = gm20b_pbdma_acquire_val,
.get_signature = gp10b_pbdma_get_signature,
.dump_status = gm20b_pbdma_dump_status,
.handle_intr_0 = gv11b_pbdma_handle_intr_0,
.handle_intr_1 = gv11b_pbdma_handle_intr_1,
.handle_intr = gm20b_pbdma_handle_intr,
.read_pbdma_data = gm20b_pbdma_read_data,
.reset_pbdma_header = gm20b_pbdma_reset_header,
.read_data = gm20b_pbdma_read_data,
.reset_header = gm20b_pbdma_reset_header,
.device_fatal_0_intr_descs =
gm20b_pbdma_device_fatal_0_intr_descs,
.channel_fatal_0_intr_descs =

6
drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.c
View File

@@ -155,7 +155,7 @@ bool gm20b_pbdma_handle_intr_0(struct gk20a *g, u32 pbdma_id,
"M0: %08x %08x %08x %08x ",
pbdma_id, pbdma_intr_0,
nvgpu_readl(g, pbdma_pb_header_r(pbdma_id)),
g->ops.pbdma.read_pbdma_data(g, pbdma_id),
g->ops.pbdma.read_data(g, pbdma_id),
nvgpu_readl(g, pbdma_gp_shadow_0_r(pbdma_id)),
nvgpu_readl(g, pbdma_gp_shadow_1_r(pbdma_id)),
nvgpu_readl(g, pbdma_method0_r(pbdma_id)),
@@ -187,7 +187,7 @@ bool gm20b_pbdma_handle_intr_0(struct gk20a *g, u32 pbdma_id,
}
if ((pbdma_intr_0 & pbdma_intr_0_pbentry_pending_f()) != 0U) {
g->ops.pbdma.reset_pbdma_header(g, pbdma_id);
g->ops.pbdma.reset_header(g, pbdma_id);
gm20b_pbdma_reset_method(g, pbdma_id, 0);
recover = true;
}
@@ -204,7 +204,7 @@ bool gm20b_pbdma_handle_intr_0(struct gk20a *g, u32 pbdma_id,
}
if ((pbdma_intr_0 & pbdma_intr_0_device_pending_f()) != 0U) {
g->ops.pbdma.reset_pbdma_header(g, pbdma_id);
g->ops.pbdma.reset_header(g, pbdma_id);
for (i = 0U; i < 4U; i++) {
if (gm20b_pbdma_is_sw_method_subch(g,

4
drivers/gpu/nvgpu/hal/fifo/ramfc_gk20a.c
View File

@@ -87,7 +87,7 @@ int gk20a_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
pbdma_gp_base_hi_limit2_f((u32)limit2_val));
nvgpu_mem_wr32(g, mem, ram_fc_signature_w(),
ch->g->ops.pbdma.get_pbdma_signature(ch->g));
ch->g->ops.pbdma.get_signature(ch->g));
nvgpu_mem_wr32(g, mem, ram_fc_formats_w(),
pbdma_formats_gp_fermi0_f() |
@@ -110,7 +110,7 @@ int gk20a_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
nvgpu_mem_wr32(g, mem, ram_fc_target_w(), pbdma_target_engine_sw_f());
nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(),
g->ops.pbdma.pbdma_acquire_val(pbdma_acquire_timeout));
g->ops.pbdma.acquire_val(pbdma_acquire_timeout));
nvgpu_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(),
fifo_runlist_timeslice_timeout_128_f() |

4
drivers/gpu/nvgpu/hal/fifo/ramfc_gp10b.c
View File

@@ -83,7 +83,7 @@ int gp10b_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
pbdma_gp_base_hi_limit2_f((u32)ilog2(gpfifo_entries)));
nvgpu_mem_wr32(g, mem, ram_fc_signature_w(),
ch->g->ops.pbdma.get_pbdma_signature(ch->g));
ch->g->ops.pbdma.get_signature(ch->g));
nvgpu_mem_wr32(g, mem, ram_fc_formats_w(),
pbdma_formats_gp_fermi0_f() |
@@ -106,7 +106,7 @@ int gp10b_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
nvgpu_mem_wr32(g, mem, ram_fc_target_w(), pbdma_target_engine_sw_f());
nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(),
g->ops.pbdma.pbdma_acquire_val(pbdma_acquire_timeout));
g->ops.pbdma.acquire_val(pbdma_acquire_timeout));
nvgpu_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(),
pbdma_runlist_timeslice_timeout_128_f() |

4
drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b.c
View File

@@ -61,7 +61,7 @@ int gv11b_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries)));
nvgpu_mem_wr32(g, mem, ram_fc_signature_w(),
ch->g->ops.pbdma.get_pbdma_signature(ch->g));
ch->g->ops.pbdma.get_signature(ch->g));
nvgpu_mem_wr32(g, mem, ram_fc_pb_header_w(),
pbdma_pb_header_method_zero_f() |
@@ -81,7 +81,7 @@ int gv11b_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
pbdma_target_engine_sw_f());
nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(),
g->ops.pbdma.pbdma_acquire_val(pbdma_acquire_timeout));
g->ops.pbdma.acquire_val(pbdma_acquire_timeout));
nvgpu_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(),
pbdma_runlist_timeslice_timeout_128_f() |

4
drivers/gpu/nvgpu/hal/fifo/ramfc_tu104.c
View File

@@ -55,7 +55,7 @@ int tu104_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries)));
nvgpu_mem_wr32(g, mem, ram_fc_signature_w(),
g->ops.pbdma.get_pbdma_signature(g));
g->ops.pbdma.get_signature(g));
nvgpu_mem_wr32(g, mem, ram_fc_pb_header_w(),
pbdma_pb_header_method_zero_f() |
@@ -75,7 +75,7 @@ int tu104_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
pbdma_target_engine_sw_f());
nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(),
g->ops.pbdma.pbdma_acquire_val(pbdma_acquire_timeout));
g->ops.pbdma.acquire_val(pbdma_acquire_timeout));
nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(),
pbdma_set_channel_info_veid_f(ch->subctx_id));

10
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -1050,12 +1050,12 @@ struct gpu_ops {
/* error_notifier can be NULL */
bool (*handle_intr)(struct gk20a *g, u32 pbdma_id,
u32 *error_notifier);
u32 (*get_pbdma_signature)(struct gk20a *g);
void (*dump_pbdma_status)(struct gk20a *g,
u32 (*get_signature)(struct gk20a *g);
void (*dump_status)(struct gk20a *g,
struct gk20a_debug_output *o);
u32 (*pbdma_acquire_val)(u64 timeout);
u32 (*read_pbdma_data)(struct gk20a *g, u32 pbdma_id);
void (*reset_pbdma_header)(struct gk20a *g, u32 pbdma_id);
u32 (*acquire_val)(u64 timeout);
u32 (*read_data)(struct gk20a *g, u32 pbdma_id);
void (*reset_header)(struct gk20a *g, u32 pbdma_id);
u32 (*device_fatal_0_intr_descs)(void);
u32 (*channel_fatal_0_intr_descs)(void);
u32 (*restartable_0_intr_descs)(void);

2
drivers/gpu/nvgpu/os/linux/debug.c
View File

@@ -66,7 +66,7 @@ void gk20a_debug_output(struct gk20a_debug_output *o, const char *fmt, ...)
void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o)
{
gk20a_debug_dump_all_channel_status_ramfc(g, o);
g->ops.pbdma.dump_pbdma_status(g, o);
g->ops.pbdma.dump_status(g, o);
g->ops.engine_status.dump_engine_status(g, o);
}

10
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -948,14 +948,14 @@ static const struct gpu_ops tu104_ops = {
},
.pbdma = {
.intr_enable = gv11b_pbdma_intr_enable,
.pbdma_acquire_val = gm20b_pbdma_acquire_val,
.get_pbdma_signature = gp10b_pbdma_get_signature,
.dump_pbdma_status = gm20b_pbdma_dump_status,
.acquire_val = gm20b_pbdma_acquire_val,
.get_signature = gp10b_pbdma_get_signature,
.dump_status = gm20b_pbdma_dump_status,
.handle_intr = gm20b_pbdma_handle_intr,
.handle_intr_0 = gv11b_pbdma_handle_intr_0,
.handle_intr_1 = gv11b_pbdma_handle_intr_1,
.read_pbdma_data = tu104_pbdma_read_data,
.reset_pbdma_header = tu104_pbdma_reset_header,
.read_data = tu104_pbdma_read_data,
.reset_header = tu104_pbdma_reset_header,
.device_fatal_0_intr_descs =
gm20b_pbdma_device_fatal_0_intr_descs,
.channel_fatal_0_intr_descs =