From 9984b59a00a34cf0f73b6987f40399203fb117fa Mon Sep 17 00:00:00 2001 From: Divya Singhatwaria Date: Sat, 14 Aug 2021 22:39:12 +0530 Subject: [PATCH] gpu: nvgpu: Add ELPG protected call for GR and CE intr - Accessing any PGRAPH registers in GR intr retrigger ISR routine when ELPG is engaged causes idle snap. - This idle snap is caught when nvgpu_submit_illegal_class test is run. - To avoid access to PGRAPH registers when ELPG is engaged add elpg protected call for GR intr retrigger and CE ISR and retrigger HALs Bug 200777033 Change-Id: Ieef4a423faf79f09476d696c3078b113750548bb Signed-off-by: Divya Singhatwaria Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2586449 Reviewed-by: Mahantesh Kumbar Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b.h | 4 +-- .../nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c | 4 ++- drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c | 25 ++++++++++++++++++- drivers/gpu/nvgpu/include/nvgpu/gops/gr.h | 2 +- 4 files changed, 30 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b.h b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b.h index d374cc602..76d26ae94 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b.h +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -64,7 +64,7 @@ void ga10b_gr_intr_handle_tpc_sm_ecc_exception(struct gk20a *g, u32 gpc, bool ga10b_gr_intr_sm_ecc_status_errors(struct gk20a *g, u32 ecc_status_reg, enum nvgpu_gr_sm_ecc_error_types err_type, struct nvgpu_gr_sm_ecc_status *ecc_status); -void ga10b_gr_intr_retrigger(struct gk20a *g); +int ga10b_gr_intr_retrigger(struct gk20a *g); void ga10b_gr_intr_enable_gpc_crop_hww(struct gk20a *g); void ga10b_gr_intr_enable_gpc_zrop_hww(struct gk20a *g); void ga10b_gr_intr_handle_gpc_crop_hww(struct gk20a *g, u32 gpc, u32 exception); diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c index 8e2572dee..176870f86 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c @@ -1028,10 +1028,12 @@ void ga10b_gr_intr_enable_interrupts(struct gk20a *g, bool enable) } } -void ga10b_gr_intr_retrigger(struct gk20a *g) +int ga10b_gr_intr_retrigger(struct gk20a *g) { nvgpu_writel(g, gr_intr_retrigger_r(), gr_intr_retrigger_trigger_true_f()); + + return 0; } u32 ga10b_gr_intr_read_pending_interrupts(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c index 3d959ef5e..bda032108 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c @@ -714,7 +714,16 @@ static int ga10b_intr_gr_stall_isr(struct gk20a *g) int err; err = nvgpu_pg_elpg_protected_call(g, g->ops.gr.intr.stall_isr(g)); - g->ops.gr.intr.retrigger(g); + if (err != 0) { + nvgpu_err(g, "GR intr stall_isr failed"); + return err; + } + + err = nvgpu_pg_elpg_protected_call(g, g->ops.gr.intr.retrigger(g)); + if (err != 0) { + nvgpu_err(g, "GR intr retrigger failed"); + return err; + } return err; } @@ -807,6 +816,7 @@ static void ga10b_intr_isr_stall_host2soc_3(struct gk20a *g) u64 engine_intr_mask; u32 vectorid; const struct nvgpu_device *dev; + int err; vectorid = g->mc.intr_unit_info[NVGPU_CIC_INTR_UNIT_CE_STALL].vectorid[0]; @@ -814,6 +824,15 @@ static void ga10b_intr_isr_stall_host2soc_3(struct gk20a *g) handled_subtree_mask |= unit_subtree_mask; ga10b_intr_subtree_clear(g, subtree, unit_subtree_mask); + /* disable elpg before accessing CE registers */ + err = nvgpu_pg_elpg_disable(g); + if (err != 0) { + nvgpu_err(g, "ELPG disable failed"); + /* enable ELPG again so that PG SM is in known state*/ + (void) nvgpu_pg_elpg_enable(g); + goto exit; + } + for (i = 0U; i < g->fifo.num_engines; i++) { dev = g->fifo.active_engines[i]; @@ -832,7 +851,11 @@ static void ga10b_intr_isr_stall_host2soc_3(struct gk20a *g) g->ops.ce.intr_retrigger(g, dev->inst_id); } + + /* enable elpg again */ + (void) nvgpu_pg_elpg_enable(g); } +exit: ga10b_intr_subtree_clear_unhandled(g, subtree, intr_leaf0, intr_leaf1, handled_subtree_mask); } diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h index 5428690eb..eff5fdbd0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h @@ -475,7 +475,7 @@ struct gops_gr_intr { /** @cond DOXYGEN_SHOULD_SKIP_THIS */ #if defined(CONFIG_NVGPU_HAL_NON_FUSA) - void (*retrigger)(struct gk20a *g); + int (*retrigger)(struct gk20a *g); u32 (*enable_mask)(struct gk20a *g); #endif int (*handle_fecs_error)(struct gk20a *g,