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gpu: nvgpu: enable stencil zbc
The implementation already exists. This change adds NVGPU_GR_ZBC_TYPE_STENCIL and plumbs through the stencil value from NvRmGpuDeviceZbcAddStencil through NVGPU_GPU_IOCTL_ZBC_SET_TABLE. Adds cases for querying the stencil values, enabling NvRmGpuDeviceZbcGetStencilTableEntry. Bug 3403523 Bug 3395601 Change-Id: I42c9a2967d0433e0bb08343aabeff0fe465f231e Signed-off-by: Pyarelal Knowles <pknowles@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2554963 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -538,6 +538,9 @@ int vgpu_gr_add_zbc(struct gk20a *g, struct nvgpu_gr_zbc *zbc,
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case NVGPU_GR_ZBC_TYPE_DEPTH:
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case NVGPU_GR_ZBC_TYPE_DEPTH:
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p->depth = zbc_val->depth;
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p->depth = zbc_val->depth;
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break;
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break;
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case NVGPU_GR_ZBC_TYPE_STENCIL:
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p->stencil = zbc_val->stencil;
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break;
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default:
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default:
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return -EINVAL;
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return -EINVAL;
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}
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}
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@@ -578,6 +581,9 @@ int vgpu_gr_query_zbc(struct gk20a *g, struct nvgpu_gr_zbc *zbc,
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case NVGPU_GR_ZBC_TYPE_DEPTH:
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case NVGPU_GR_ZBC_TYPE_DEPTH:
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query_params->depth = p->depth;
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query_params->depth = p->depth;
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break;
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break;
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case NVGPU_GR_ZBC_TYPE_STENCIL:
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query_params->stencil = p->stencil;
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break;
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case NVGPU_GR_ZBC_TYPE_INVALID:
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case NVGPU_GR_ZBC_TYPE_INVALID:
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query_params->index_size = p->index_size;
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query_params->index_size = p->index_size;
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break;
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break;
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@@ -254,22 +254,25 @@ struct tegra_vgpu_zcull_info_params {
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#define TEGRA_VGPU_ZBC_TYPE_INVALID 0
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#define TEGRA_VGPU_ZBC_TYPE_INVALID 0
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#define TEGRA_VGPU_ZBC_TYPE_COLOR 1
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#define TEGRA_VGPU_ZBC_TYPE_COLOR 1
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#define TEGRA_VGPU_ZBC_TYPE_DEPTH 2
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#define TEGRA_VGPU_ZBC_TYPE_DEPTH 2
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#define TEGRA_VGPU_ZBC_TYPE_STENCIL 3
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struct tegra_vgpu_zbc_set_table_params {
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struct tegra_vgpu_zbc_set_table_params {
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u32 color_ds[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE];
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u32 color_ds[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE];
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u32 color_l2[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE];
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u32 color_l2[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE];
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u32 depth;
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u32 depth;
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u32 stencil;
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u32 format;
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u32 format;
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u32 type; /* color or depth */
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u32 type; /* color, depth or stencil */
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};
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};
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struct tegra_vgpu_zbc_query_table_params {
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struct tegra_vgpu_zbc_query_table_params {
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u32 color_ds[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE];
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u32 color_ds[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE];
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u32 color_l2[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE];
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u32 color_l2[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE];
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u32 depth;
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u32 depth;
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u32 stencil;
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u32 ref_cnt;
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u32 ref_cnt;
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u32 format;
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u32 format;
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u32 type; /* color or depth */
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u32 type; /* color, depth or stencil */
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u32 index_size; /* [out] size, [in] index */
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u32 index_size; /* [out] size, [in] index */
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};
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};
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#endif
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#endif
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@@ -2307,6 +2307,10 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
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nvgpu_gr_zbc_set_entry_depth(zbc_val,
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nvgpu_gr_zbc_set_entry_depth(zbc_val,
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set_table_args->depth);
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set_table_args->depth);
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break;
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break;
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case NVGPU_GR_ZBC_TYPE_STENCIL:
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nvgpu_gr_zbc_set_entry_stencil(zbc_val,
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set_table_args->stencil);
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break;
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default:
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default:
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err = -EINVAL;
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err = -EINVAL;
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}
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}
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@@ -2349,6 +2353,9 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
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case NVGPU_GR_ZBC_TYPE_DEPTH:
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case NVGPU_GR_ZBC_TYPE_DEPTH:
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query_table_args->depth = zbc_tbl->depth;
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query_table_args->depth = zbc_tbl->depth;
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break;
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break;
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case NVGPU_GR_ZBC_TYPE_STENCIL:
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query_table_args->stencil = zbc_tbl->stencil;
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break;
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case NVGPU_GR_ZBC_TYPE_INVALID:
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case NVGPU_GR_ZBC_TYPE_INVALID:
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query_table_args->index_size = zbc_tbl->index_size;
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query_table_args->index_size = zbc_tbl->index_size;
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break;
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break;
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@@ -49,22 +49,25 @@ struct nvgpu_gpu_zcull_get_info_args {
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#define NVGPU_ZBC_TYPE_INVALID 0
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#define NVGPU_ZBC_TYPE_INVALID 0
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#define NVGPU_ZBC_TYPE_COLOR 1
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#define NVGPU_ZBC_TYPE_COLOR 1
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#define NVGPU_ZBC_TYPE_DEPTH 2
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#define NVGPU_ZBC_TYPE_DEPTH 2
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#define NVGPU_ZBC_TYPE_STENCIL 3
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struct nvgpu_gpu_zbc_set_table_args {
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struct nvgpu_gpu_zbc_set_table_args {
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__u32 color_ds[NVGPU_ZBC_COLOR_VALUE_SIZE];
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__u32 color_ds[NVGPU_ZBC_COLOR_VALUE_SIZE];
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__u32 color_l2[NVGPU_ZBC_COLOR_VALUE_SIZE];
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__u32 color_l2[NVGPU_ZBC_COLOR_VALUE_SIZE];
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__u32 depth;
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__u32 depth;
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__u32 stencil;
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__u32 format;
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__u32 format;
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__u32 type; /* color or depth */
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__u32 type; /* color, depth or stencil */
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};
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};
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struct nvgpu_gpu_zbc_query_table_args {
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struct nvgpu_gpu_zbc_query_table_args {
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__u32 color_ds[NVGPU_ZBC_COLOR_VALUE_SIZE];
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__u32 color_ds[NVGPU_ZBC_COLOR_VALUE_SIZE];
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__u32 color_l2[NVGPU_ZBC_COLOR_VALUE_SIZE];
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__u32 color_l2[NVGPU_ZBC_COLOR_VALUE_SIZE];
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__u32 depth;
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__u32 depth;
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__u32 stencil;
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__u32 ref_cnt;
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__u32 ref_cnt;
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__u32 format;
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__u32 format;
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__u32 type; /* color or depth */
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__u32 type; /* color, depth or stencil */
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__u32 index_size; /* [out] size, [in] index */
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__u32 index_size; /* [out] size, [in] index */
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};
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};
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