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gpu: nvgpu: support usermode submit buffers

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Import userd and gpfifo buffers from userspace if provided via
NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX. Also supply the work submit token
(i.e., the hw channel id) to userspace.

To keep the buffers alive, store their dmabuf and attachment/sgt handles
in nvgpu_channel_linux. Our nvgpu_mem doesn't provide such data for
buffers that are mainly in kernel use. The buffers are freed via a new
API in the os_channel interface.

Fix a bug in gk20a_channel_free_usermode_buffers: also unmap the
usermode gpfifo buffer.

Bug 200145225

Change-Id: I8416af7085c91b044ac8ccd9faa38e2a6d0c3946
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795821
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Konsta Holtta
2018-09-11 14:47:51 +03:00
committed by mobile promotions
parent 9de6d20abb
commit 99b1c6dcdf
7 changed files with 204 additions and 3 deletions
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18
include/uapi/linux/nvgpu.h
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@@ -1514,8 +1514,24 @@ struct nvgpu_channel_setup_bind_args {
#define NVGPU_CHANNEL_SETUP_BIND_FLAGS_DETERMINISTIC (1 << 1)
/* enable replayable gmmu faults for this channel */
#define NVGPU_CHANNEL_SETUP_BIND_FLAGS_REPLAYABLE_FAULTS_ENABLE (1 << 2)
/*
* Enable usermode submits on this channel.
*
* Submits in usermode are supported in some environments. If supported and
* this flag is set + USERD and GPFIFO buffers are provided here, a submit
* token is passed back to be written in the doorbell register in the usermode
* region to notify the GPU for new work on this channel. Usermode and
* kernelmode submit modes are mutually exclusive; by passing this flag, the
* SUBMIT_GPFIFO IOCTL cannot be used.
*/
#define NVGPU_CHANNEL_SETUP_BIND_FLAGS_USERMODE_SUPPORT (1 << 3)
__u32 flags;
__u32 reserved[16];
__s32 userd_dmabuf_fd; /* in */
__s32 gpfifo_dmabuf_fd; /* in */
__u32 work_submit_token; /* out */
__u64 userd_dmabuf_offset; /* in */
__u64 gpfifo_dmabuf_offset; /* in */
__u32 reserved[9];
};
struct nvgpu_fence {