From 99bdda584603414cd3d45516962b6fa34bf4c4c6 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Wed, 15 May 2019 09:48:13 -0700 Subject: [PATCH] gpu: nvgpu: fix MISRA 21.2 violations in nvgpu.hal.mm.gmmu Renamed the following functions to fix MISRA 21.2 violations: - __update_pte -> update_pte - __update_pte_sparse -> update_pte_sparse Jira NVGPU-3284 Change-Id: Ic2281254f362ca261ab66562a4160acd3bf7ebc2 Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/2119617 GVS: Gerrit_Virtual_Submit Reviewed-by: Philip Elcan Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gk20a.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gk20a.c b/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gk20a.c index 24155a80d..e19878eb1 100644 --- a/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gk20a.c +++ b/drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gk20a.c @@ -100,13 +100,13 @@ static void update_gmmu_pde_locked(struct vm_gk20a *vm, nvgpu_pd_write(g, &vm->pdb, (size_t)pd_offset + (size_t)1, pde_v[1]); } -static void __update_pte_sparse(u32 *pte_w) +static void update_pte_sparse(u32 *pte_w) { pte_w[0] = gmmu_pte_valid_false_f(); pte_w[1] |= gmmu_pte_vol_true_f(); } -static void __update_pte(struct vm_gk20a *vm, +static void update_pte(struct vm_gk20a *vm, u32 *pte_w, u64 phys_addr, struct nvgpu_gmmu_attrs *attrs) @@ -189,10 +189,10 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm, } if (phys_addr != 0ULL) { - __update_pte(vm, pte_w, phys_addr, attrs); + update_pte(vm, pte_w, phys_addr, attrs); } else { if (attrs->sparse) { - __update_pte_sparse(pte_w); + update_pte_sparse(pte_w); } }