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gpu: nvgpu: gv11b: Use internal nvgpu_warpstate

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Replace use of ioctl structure warpstate with internal
nvgpu_warptate.

JIRA NVGPU-259

Change-Id: I003c15152042e566124c04d6124e515e36157c88
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1578683
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
2017-10-13 08:12:58 -07:00
committed by mobile promotions
parent e78cd6c42a
commit 99cae3dff7
2 changed files with 3 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -2504,7 +2504,7 @@ int gv11b_gr_sm_trigger_suspend(struct gk20a *g)
return 0; return 0;
} }
void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state)
{ {
/* Check if we have at least one valid warp /* Check if we have at least one valid warp
* get paused state on maxwell * get paused state on maxwell

3
drivers/gpu/nvgpu/gv11b/gr_gv11b.h
View File

@@ -44,6 +44,7 @@ struct gk20a;
struct zbc_entry; struct zbc_entry;
struct zbc_query_params; struct zbc_query_params;
struct channel_ctx_gk20a; struct channel_ctx_gk20a;
struct nvgpu_warpstate;
enum { enum {
VOLTA_CHANNEL_GPFIFO_A = 0xC36F, VOLTA_CHANNEL_GPFIFO_A = 0xC36F,
@@ -158,7 +159,7 @@ int gr_gv11b_init_fs_state(struct gk20a *g);
void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc,
u32 *esr_sm_sel); u32 *esr_sm_sel);
int gv11b_gr_sm_trigger_suspend(struct gk20a *g); int gv11b_gr_sm_trigger_suspend(struct gk20a *g);
void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state); void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state);
int gv11b_gr_update_sm_error_state(struct gk20a *g, int gv11b_gr_update_sm_error_state(struct gk20a *g,
struct channel_gk20a *ch, u32 sm_id, struct channel_gk20a *ch, u32 sm_id,
struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state); struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state);