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gpu: nvgpu: read gobs_per_comptagline_per_slice

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Add code to read NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE
during t18x ltc init and store it for use in CDE code.

Change-Id: I4d4a3a6c7e3ad369d8359ff838e7040a0521b441
Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com>
Reviewed-on: http://git-master/r/673150
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Jussi Rasanen
2015-01-16 12:55:28 +02:00
committed by Deepak Nibade
parent c0fcbdf2fc
commit 99d41c05f5
2 changed files with 18 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -174,6 +174,14 @@ static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
{
return (r >> 28) & 0xf;
}
static inline u32 ltc_ltcs_ltss_cbc_param2_r(void)
{
return 0x0017e3f4;
}
static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r)
{
return (r >> 0) & 0xffff;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
{
return 0x0017e2ac;

10
drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
View File

@@ -1,7 +1,7 @@
/*
* GP10B L2
*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -59,6 +59,10 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
512 << ltc_ltcs_ltss_cbc_param_cache_line_size_v(cbc_param);
u32 slices_per_ltc =
ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(cbc_param);
u32 cbc_param2 =
gk20a_readl(g, ltc_ltcs_ltss_cbc_param2_r());
u32 gobs_per_comptagline_per_slice =
ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(cbc_param2);
u32 compbit_backing_size;
@@ -96,6 +100,8 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
compbit_backing_size);
gk20a_dbg_info("max comptag lines : %d",
max_comptag_lines);
gk20a_dbg_info("gobs_per_comptagline_per_slice: %d",
gobs_per_comptagline_per_slice);
if (tegra_platform_is_linsim())
err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size);
@@ -112,6 +118,7 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
gr->comptags_per_cacheline = comptags_per_cacheline;
gr->slices_per_ltc = slices_per_ltc;
gr->cacheline_size = cacheline_size;
gr->gobs_per_comptagline_per_slice = gobs_per_comptagline_per_slice;
return 0;
}
@@ -136,3 +143,4 @@ void gp10b_init_ltc(struct gpu_ops *gops)
gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs;
#endif
}