gpu: nvgpu: init: take out the litter

Move the get_litter() functions out of the main hal init to its own
source file for each device. This allows removal of the hw_proj_*.h
files in the main hal init file. This reduces the number of hw header
includes per file creating better code isolation.

JIRA NVGPU-3274

Change-Id: I9e04294434acf274ccc2236646f0f15f710a6976
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107751
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -207,10 +207,15 @@ nvgpu-y += \
 	hal/gr/gr/gr_tu104.o \
 	hal/fbpa/fbpa_tu104.o \
 	hal/init/hal_gm20b.o \
+	hal/init/hal_gm20b_litter.o \
 	hal/init/hal_gp10b.o \
+	hal/init/hal_gp10b_litter.o \
 	hal/init/hal_gv100.o \
+	hal/init/hal_gv100_litter.o \
 	hal/init/hal_gv11b.o \
+	hal/init/hal_gv11b_litter.o \
 	hal/init/hal_tu104.o \
+	hal/init/hal_tu104_litter.o \
 	hal/init/hal_init.o \
 	hal/perf/perf_gm20b.o \
 	hal/perf/perf_gv11b.o \

drivers/gpu/nvgpu/Makefile.sources

@@ -308,10 +308,15 @@ srcs += common/sim/sim.c \
 	hal/gr/gr/gr_tu104.c \
 	hal/fbpa/fbpa_tu104.c \
 	hal/init/hal_gm20b.c \
+	hal/init/hal_gm20b_litter.c \
 	hal/init/hal_gp10b.c \
+	hal/init/hal_gp10b_litter.c \
 	hal/init/hal_gv100.c \
+	hal/init/hal_gv100_litter.c \
 	hal/init/hal_gv11b.c \
+	hal/init/hal_gv11b_litter.c \
 	hal/init/hal_tu104.c \
+	hal/init/hal_tu104_litter.c \
 	hal/init/hal_init.c \
 	hal/perf/perf_gm20b.c \
 	hal/perf/perf_gv11b.c \

drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -73,6 +73,7 @@
 #include "hal/sync/syncpt_cmdbuf_gk20a.h"
 #include "hal/sync/sema_cmdbuf_gk20a.h"
 #include "hal/init/hal_gp10b.h"
+#include "hal/init/hal_gp10b_litter.h"
 
 #include "common/fifo/channel_gm20b.h"
 #include "common/clk_arb/clk_arb_gp10b.h"

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -80,6 +80,7 @@
 #include "hal/sync/syncpt_cmdbuf_gv11b.h"
 #include "hal/sync/sema_cmdbuf_gv11b.h"
 #include "hal/init/hal_gv11b.h"
+#include "hal/init/hal_gv11b_litter.h"
 
 #include "common/fifo/channel_gv11b.h"
 #include "common/clk_arb/clk_arb_gp10b.h"

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -21,7 +21,6 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#include <nvgpu/class.h>
 #include <nvgpu/ptimer.h>
 #include <nvgpu/error_notifier.h>
 #include <nvgpu/gk20a.h>
@@ -103,125 +102,12 @@
 #include "common/pmu/pg/pg_sw_gm20b.h"
 
 #include "hal_gm20b.h"
+#include "hal_gm20b_litter.h"
 
-#include <nvgpu/hw/gm20b/hw_proj_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_pwr_gm20b.h>
 
 #define PRIV_SECURITY_DISABLE 0x01
 
-u32 gm20b_get_litter_value(struct gk20a *g, int value)
-{
-	u32 ret = 0;
-	switch (value) {
-	case GPU_LIT_NUM_GPCS:
-		ret = proj_scal_litter_num_gpcs_v();
-		break;
-	case GPU_LIT_NUM_PES_PER_GPC:
-		ret = proj_scal_litter_num_pes_per_gpc_v();
-		break;
-	case GPU_LIT_NUM_ZCULL_BANKS:
-		ret = proj_scal_litter_num_zcull_banks_v();
-		break;
-	case GPU_LIT_NUM_TPC_PER_GPC:
-		ret = proj_scal_litter_num_tpc_per_gpc_v();
-		break;
-	case GPU_LIT_NUM_SM_PER_TPC:
-		ret = proj_scal_litter_num_sm_per_tpc_v();
-		break;
-	case GPU_LIT_NUM_FBPS:
-		ret = proj_scal_litter_num_fbps_v();
-		break;
-	case GPU_LIT_GPC_BASE:
-		ret = proj_gpc_base_v();
-		break;
-	case GPU_LIT_GPC_STRIDE:
-		ret = proj_gpc_stride_v();
-		break;
-	case GPU_LIT_GPC_SHARED_BASE:
-		ret = proj_gpc_shared_base_v();
-		break;
-	case GPU_LIT_TPC_IN_GPC_BASE:
-		ret = proj_tpc_in_gpc_base_v();
-		break;
-	case GPU_LIT_TPC_IN_GPC_STRIDE:
-		ret = proj_tpc_in_gpc_stride_v();
-		break;
-	case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
-		ret = proj_tpc_in_gpc_shared_base_v();
-		break;
-	case GPU_LIT_PPC_IN_GPC_BASE:
-		ret = proj_ppc_in_gpc_base_v();
-		break;
-	case GPU_LIT_PPC_IN_GPC_STRIDE:
-		ret = proj_ppc_in_gpc_stride_v();
-		break;
-	case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
-		ret = proj_ppc_in_gpc_shared_base_v();
-		break;
-	case GPU_LIT_ROP_BASE:
-		ret = proj_rop_base_v();
-		break;
-	case GPU_LIT_ROP_STRIDE:
-		ret = proj_rop_stride_v();
-		break;
-	case GPU_LIT_ROP_SHARED_BASE:
-		ret = proj_rop_shared_base_v();
-		break;
-	case GPU_LIT_HOST_NUM_ENGINES:
-		ret = proj_host_num_engines_v();
-		break;
-	case GPU_LIT_HOST_NUM_PBDMA:
-		ret = proj_host_num_pbdma_v();
-		break;
-	case GPU_LIT_LTC_STRIDE:
-		ret = proj_ltc_stride_v();
-		break;
-	case GPU_LIT_LTS_STRIDE:
-		ret = proj_lts_stride_v();
-		break;
-	/* Even though GM20B doesn't have an FBPA unit, the HW reports one,
-	 * and the microcode as a result leaves space in the context buffer
-	 * for one, so make sure SW accounts for this also.
-	 */
-	case GPU_LIT_NUM_FBPAS:
-		ret = proj_scal_litter_num_fbpas_v();
-		break;
-	/* Hardcode FBPA values other than NUM_FBPAS to 0. */
-	case GPU_LIT_FBPA_STRIDE:
-	case GPU_LIT_FBPA_BASE:
-	case GPU_LIT_FBPA_SHARED_BASE:
-		ret = 0;
-		break;
-	case GPU_LIT_TWOD_CLASS:
-		ret = FERMI_TWOD_A;
-		break;
-	case GPU_LIT_THREED_CLASS:
-		ret = MAXWELL_B;
-		break;
-	case GPU_LIT_COMPUTE_CLASS:
-		ret = MAXWELL_COMPUTE_B;
-		break;
-	case GPU_LIT_GPFIFO_CLASS:
-		ret = MAXWELL_CHANNEL_GPFIFO_A;
-		break;
-	case GPU_LIT_I2M_CLASS:
-		ret = KEPLER_INLINE_TO_MEMORY_B;
-		break;
-	case GPU_LIT_DMA_COPY_CLASS:
-		ret = MAXWELL_DMA_COPY_A;
-		break;
-	case GPU_LIT_GPC_PRIV_STRIDE:
-		ret = proj_gpc_priv_stride_v();
-		break;
-	default:
-		nvgpu_err(g, "Missing definition %d", value);
-		BUG();
-		break;
-	}
-
-	return ret;
-}
-
 static const struct gpu_ops gm20b_ops = {
 	.ltc = {
 		.determine_L2_size_bytes = gm20b_determine_L2_size_bytes,

drivers/gpu/nvgpu/hal/init/hal_gm20b.h

@@ -1,7 +1,7 @@
 /*
  * GM20B Graphics
  *
- * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -27,5 +27,4 @@
 struct gk20a;
 
 int gm20b_init_hal(struct gk20a *g);
-u32 gm20b_get_litter_value(struct gk20a *g, int value);
 #endif /* NVGPU_GM20B_HAL_GM20B_H */

drivers/gpu/nvgpu/hal/init/hal_gm20b_litter.c

@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/class.h>
+
+#include <nvgpu/hw/gm20b/hw_proj_gm20b.h>
+
+#include "hal_gm20b_litter.h"
+
+u32 gm20b_get_litter_value(struct gk20a *g, int value)
+{
+	u32 ret = 0;
+
+	switch (value) {
+	case GPU_LIT_NUM_GPCS:
+		ret = proj_scal_litter_num_gpcs_v();
+		break;
+	case GPU_LIT_NUM_PES_PER_GPC:
+		ret = proj_scal_litter_num_pes_per_gpc_v();
+		break;
+	case GPU_LIT_NUM_ZCULL_BANKS:
+		ret = proj_scal_litter_num_zcull_banks_v();
+		break;
+	case GPU_LIT_NUM_TPC_PER_GPC:
+		ret = proj_scal_litter_num_tpc_per_gpc_v();
+		break;
+	case GPU_LIT_NUM_SM_PER_TPC:
+		ret = proj_scal_litter_num_sm_per_tpc_v();
+		break;
+	case GPU_LIT_NUM_FBPS:
+		ret = proj_scal_litter_num_fbps_v();
+		break;
+	case GPU_LIT_GPC_BASE:
+		ret = proj_gpc_base_v();
+		break;
+	case GPU_LIT_GPC_STRIDE:
+		ret = proj_gpc_stride_v();
+		break;
+	case GPU_LIT_GPC_SHARED_BASE:
+		ret = proj_gpc_shared_base_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_BASE:
+		ret = proj_tpc_in_gpc_base_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_STRIDE:
+		ret = proj_tpc_in_gpc_stride_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
+		ret = proj_tpc_in_gpc_shared_base_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_BASE:
+		ret = proj_ppc_in_gpc_base_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_STRIDE:
+		ret = proj_ppc_in_gpc_stride_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
+		ret = proj_ppc_in_gpc_shared_base_v();
+		break;
+	case GPU_LIT_ROP_BASE:
+		ret = proj_rop_base_v();
+		break;
+	case GPU_LIT_ROP_STRIDE:
+		ret = proj_rop_stride_v();
+		break;
+	case GPU_LIT_ROP_SHARED_BASE:
+		ret = proj_rop_shared_base_v();
+		break;
+	case GPU_LIT_HOST_NUM_ENGINES:
+		ret = proj_host_num_engines_v();
+		break;
+	case GPU_LIT_HOST_NUM_PBDMA:
+		ret = proj_host_num_pbdma_v();
+		break;
+	case GPU_LIT_LTC_STRIDE:
+		ret = proj_ltc_stride_v();
+		break;
+	case GPU_LIT_LTS_STRIDE:
+		ret = proj_lts_stride_v();
+		break;
+	/* Even though GM20B doesn't have an FBPA unit, the HW reports one,
+	 * and the microcode as a result leaves space in the context buffer
+	 * for one, so make sure SW accounts for this also.
+	 */
+	case GPU_LIT_NUM_FBPAS:
+		ret = proj_scal_litter_num_fbpas_v();
+		break;
+	/* Hardcode FBPA values other than NUM_FBPAS to 0. */
+	case GPU_LIT_FBPA_STRIDE:
+	case GPU_LIT_FBPA_BASE:
+	case GPU_LIT_FBPA_SHARED_BASE:
+		ret = 0;
+		break;
+	case GPU_LIT_TWOD_CLASS:
+		ret = FERMI_TWOD_A;
+		break;
+	case GPU_LIT_THREED_CLASS:
+		ret = MAXWELL_B;
+		break;
+	case GPU_LIT_COMPUTE_CLASS:
+		ret = MAXWELL_COMPUTE_B;
+		break;
+	case GPU_LIT_GPFIFO_CLASS:
+		ret = MAXWELL_CHANNEL_GPFIFO_A;
+		break;
+	case GPU_LIT_I2M_CLASS:
+		ret = KEPLER_INLINE_TO_MEMORY_B;
+		break;
+	case GPU_LIT_DMA_COPY_CLASS:
+		ret = MAXWELL_DMA_COPY_A;
+		break;
+	case GPU_LIT_GPC_PRIV_STRIDE:
+		ret = proj_gpc_priv_stride_v();
+		break;
+	default:
+		nvgpu_err(g, "Missing definition %d", value);
+		BUG();
+		break;
+	}
+
+	return ret;
+}
+

drivers/gpu/nvgpu/hal/init/hal_gm20b_litter.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_HAL_GM20B_LITTER_H
+#define NVGPU_HAL_GM20B_LITTER_H
+
+u32 gm20b_get_litter_value(struct gk20a *g, int value);
+
+#endif /* NVGPU_HAL_GM20B_LITTER_H */

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -21,7 +21,6 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#include <nvgpu/class.h>
 #include <nvgpu/ptimer.h>
 #include <nvgpu/error_notifier.h>
 #include <nvgpu/gk20a.h>
@@ -125,8 +124,8 @@
 #include "common/clk_arb/clk_arb_gp10b.h"
 
 #include "hal_gp10b.h"
+#include "hal_gp10b_litter.h"
 
-#include <nvgpu/hw/gp10b/hw_proj_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_pram_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_pwr_gp10b.h>
 
@@ -137,119 +136,6 @@ static void gp10b_init_gpu_characteristics(struct gk20a *g)
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, true);
 }
 
-u32 gp10b_get_litter_value(struct gk20a *g, int value)
-{
-	u32 ret = 0;
-	switch (value) {
-	case GPU_LIT_NUM_GPCS:
-		ret = proj_scal_litter_num_gpcs_v();
-		break;
-	case GPU_LIT_NUM_PES_PER_GPC:
-		ret = proj_scal_litter_num_pes_per_gpc_v();
-		break;
-	case GPU_LIT_NUM_ZCULL_BANKS:
-		ret = proj_scal_litter_num_zcull_banks_v();
-		break;
-	case GPU_LIT_NUM_TPC_PER_GPC:
-		ret = proj_scal_litter_num_tpc_per_gpc_v();
-		break;
-	case GPU_LIT_NUM_SM_PER_TPC:
-		ret = proj_scal_litter_num_sm_per_tpc_v();
-		break;
-	case GPU_LIT_NUM_FBPS:
-		ret = proj_scal_litter_num_fbps_v();
-		break;
-	case GPU_LIT_GPC_BASE:
-		ret = proj_gpc_base_v();
-		break;
-	case GPU_LIT_GPC_STRIDE:
-		ret = proj_gpc_stride_v();
-		break;
-	case GPU_LIT_GPC_SHARED_BASE:
-		ret = proj_gpc_shared_base_v();
-		break;
-	case GPU_LIT_TPC_IN_GPC_BASE:
-		ret = proj_tpc_in_gpc_base_v();
-		break;
-	case GPU_LIT_TPC_IN_GPC_STRIDE:
-		ret = proj_tpc_in_gpc_stride_v();
-		break;
-	case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
-		ret = proj_tpc_in_gpc_shared_base_v();
-		break;
-	case GPU_LIT_PPC_IN_GPC_BASE:
-		ret = proj_ppc_in_gpc_base_v();
-		break;
-	case GPU_LIT_PPC_IN_GPC_STRIDE:
-		ret = proj_ppc_in_gpc_stride_v();
-		break;
-	case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
-		ret = proj_ppc_in_gpc_shared_base_v();
-		break;
-	case GPU_LIT_ROP_BASE:
-		ret = proj_rop_base_v();
-		break;
-	case GPU_LIT_ROP_STRIDE:
-		ret = proj_rop_stride_v();
-		break;
-	case GPU_LIT_ROP_SHARED_BASE:
-		ret = proj_rop_shared_base_v();
-		break;
-	case GPU_LIT_HOST_NUM_ENGINES:
-		ret = proj_host_num_engines_v();
-		break;
-	case GPU_LIT_HOST_NUM_PBDMA:
-		ret = proj_host_num_pbdma_v();
-		break;
-	case GPU_LIT_LTC_STRIDE:
-		ret = proj_ltc_stride_v();
-		break;
-	case GPU_LIT_LTS_STRIDE:
-		ret = proj_lts_stride_v();
-		break;
-	/* Even though GP10B doesn't have an FBPA unit, the HW reports one,
-	 * and the microcode as a result leaves space in the context buffer
-	 * for one, so make sure SW accounts for this also.
-	 */
-	case GPU_LIT_NUM_FBPAS:
-		ret = proj_scal_litter_num_fbpas_v();
-		break;
-	/* Hardcode FBPA values other than NUM_FBPAS to 0. */
-	case GPU_LIT_FBPA_STRIDE:
-	case GPU_LIT_FBPA_BASE:
-	case GPU_LIT_FBPA_SHARED_BASE:
-		ret = 0;
-		break;
-	case GPU_LIT_TWOD_CLASS:
-		ret = FERMI_TWOD_A;
-		break;
-	case GPU_LIT_THREED_CLASS:
-		ret = PASCAL_A;
-		break;
-	case GPU_LIT_COMPUTE_CLASS:
-		ret = PASCAL_COMPUTE_A;
-		break;
-	case GPU_LIT_GPFIFO_CLASS:
-		ret = PASCAL_CHANNEL_GPFIFO_A;
-		break;
-	case GPU_LIT_I2M_CLASS:
-		ret = KEPLER_INLINE_TO_MEMORY_B;
-		break;
-	case GPU_LIT_DMA_COPY_CLASS:
-		ret = PASCAL_DMA_COPY_A;
-		break;
-	case GPU_LIT_GPC_PRIV_STRIDE:
-		ret = proj_gpc_priv_stride_v();
-		break;
-	default:
-		nvgpu_err(g, "Missing definition %d", value);
-		BUG();
-		break;
-	}
-
-	return ret;
-}
-
 static const struct gpu_ops gp10b_ops = {
 	.ltc = {
 		.determine_L2_size_bytes = gp10b_determine_L2_size_bytes,

drivers/gpu/nvgpu/hal/init/hal_gp10b.h

@@ -1,7 +1,7 @@
 /*
  * GP10B Tegra HAL interface
  *
- * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -27,5 +27,4 @@
 struct gk20a;
 
 int gp10b_init_hal(struct gk20a *g);
-u32 gp10b_get_litter_value(struct gk20a *g, int value);
 #endif /* NVGPU_HAL_GP10B_H */

drivers/gpu/nvgpu/hal/init/hal_gp10b_litter.c

@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/class.h>
+#include <nvgpu/gk20a.h>
+
+#include <nvgpu/hw/gp10b/hw_proj_gp10b.h>
+
+#include "hal_gp10b_litter.h"
+
+u32 gp10b_get_litter_value(struct gk20a *g, int value)
+{
+	u32 ret = 0;
+
+	switch (value) {
+	case GPU_LIT_NUM_GPCS:
+		ret = proj_scal_litter_num_gpcs_v();
+		break;
+	case GPU_LIT_NUM_PES_PER_GPC:
+		ret = proj_scal_litter_num_pes_per_gpc_v();
+		break;
+	case GPU_LIT_NUM_ZCULL_BANKS:
+		ret = proj_scal_litter_num_zcull_banks_v();
+		break;
+	case GPU_LIT_NUM_TPC_PER_GPC:
+		ret = proj_scal_litter_num_tpc_per_gpc_v();
+		break;
+	case GPU_LIT_NUM_SM_PER_TPC:
+		ret = proj_scal_litter_num_sm_per_tpc_v();
+		break;
+	case GPU_LIT_NUM_FBPS:
+		ret = proj_scal_litter_num_fbps_v();
+		break;
+	case GPU_LIT_GPC_BASE:
+		ret = proj_gpc_base_v();
+		break;
+	case GPU_LIT_GPC_STRIDE:
+		ret = proj_gpc_stride_v();
+		break;
+	case GPU_LIT_GPC_SHARED_BASE:
+		ret = proj_gpc_shared_base_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_BASE:
+		ret = proj_tpc_in_gpc_base_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_STRIDE:
+		ret = proj_tpc_in_gpc_stride_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
+		ret = proj_tpc_in_gpc_shared_base_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_BASE:
+		ret = proj_ppc_in_gpc_base_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_STRIDE:
+		ret = proj_ppc_in_gpc_stride_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
+		ret = proj_ppc_in_gpc_shared_base_v();
+		break;
+	case GPU_LIT_ROP_BASE:
+		ret = proj_rop_base_v();
+		break;
+	case GPU_LIT_ROP_STRIDE:
+		ret = proj_rop_stride_v();
+		break;
+	case GPU_LIT_ROP_SHARED_BASE:
+		ret = proj_rop_shared_base_v();
+		break;
+	case GPU_LIT_HOST_NUM_ENGINES:
+		ret = proj_host_num_engines_v();
+		break;
+	case GPU_LIT_HOST_NUM_PBDMA:
+		ret = proj_host_num_pbdma_v();
+		break;
+	case GPU_LIT_LTC_STRIDE:
+		ret = proj_ltc_stride_v();
+		break;
+	case GPU_LIT_LTS_STRIDE:
+		ret = proj_lts_stride_v();
+		break;
+	/* Even though GP10B doesn't have an FBPA unit, the HW reports one,
+	 * and the microcode as a result leaves space in the context buffer
+	 * for one, so make sure SW accounts for this also.
+	 */
+	case GPU_LIT_NUM_FBPAS:
+		ret = proj_scal_litter_num_fbpas_v();
+		break;
+	/* Hardcode FBPA values other than NUM_FBPAS to 0. */
+	case GPU_LIT_FBPA_STRIDE:
+	case GPU_LIT_FBPA_BASE:
+	case GPU_LIT_FBPA_SHARED_BASE:
+		ret = 0;
+		break;
+	case GPU_LIT_TWOD_CLASS:
+		ret = FERMI_TWOD_A;
+		break;
+	case GPU_LIT_THREED_CLASS:
+		ret = PASCAL_A;
+		break;
+	case GPU_LIT_COMPUTE_CLASS:
+		ret = PASCAL_COMPUTE_A;
+		break;
+	case GPU_LIT_GPFIFO_CLASS:
+		ret = PASCAL_CHANNEL_GPFIFO_A;
+		break;
+	case GPU_LIT_I2M_CLASS:
+		ret = KEPLER_INLINE_TO_MEMORY_B;
+		break;
+	case GPU_LIT_DMA_COPY_CLASS:
+		ret = PASCAL_DMA_COPY_A;
+		break;
+	case GPU_LIT_GPC_PRIV_STRIDE:
+		ret = proj_gpc_priv_stride_v();
+		break;
+	default:
+		nvgpu_err(g, "Missing definition %d", value);
+		BUG();
+		break;
+	}
+
+	return ret;
+}
+

drivers/gpu/nvgpu/hal/init/hal_gp10b_litter.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_HAL_GP10B_LITTER_H
+#define NVGPU_HAL_GP10B_LITTER_H
+
+u32 gp10b_get_litter_value(struct gk20a *g, int value);
+
+#endif /* NVGPU_HAL_GP10B_LITTER_H */

drivers/gpu/nvgpu/hal/init/hal_gv100.c

@@ -154,13 +154,13 @@
 #include "gv11b/mm_gv11b.h"
 
 #include "hal_gv100.h"
+#include "hal_gv100_litter.h"
 
 #include "gv100/mm_gv100.h"
 #include "hal/clk/clk_gv100.h"
 
 #include <nvgpu/gk20a.h>
 #include <nvgpu/ptimer.h>
-#include <nvgpu/class.h>
 #include <nvgpu/error_notifier.h>
 #include <nvgpu/debugger.h>
 #include <nvgpu/pbdma.h>
@@ -178,158 +178,9 @@
 #include <nvgpu/gr/gr_intr.h>
 #include <nvgpu/pmu/lpwr.h>
 
-#include <nvgpu/hw/gv100/hw_proj_gv100.h>
 #include <nvgpu/hw/gv100/hw_pram_gv100.h>
 #include <nvgpu/hw/gv100/hw_pwr_gv100.h>
 
-static u32 gv100_get_litter_value(struct gk20a *g, int value)
-{
-	u32 ret = 0;
-	switch (value) {
-	case GPU_LIT_NUM_GPCS:
-		ret = proj_scal_litter_num_gpcs_v();
-		break;
-	case GPU_LIT_NUM_PES_PER_GPC:
-		ret = proj_scal_litter_num_pes_per_gpc_v();
-		break;
-	case GPU_LIT_NUM_ZCULL_BANKS:
-		ret = proj_scal_litter_num_zcull_banks_v();
-		break;
-	case GPU_LIT_NUM_TPC_PER_GPC:
-		ret = proj_scal_litter_num_tpc_per_gpc_v();
-		break;
-	case GPU_LIT_NUM_SM_PER_TPC:
-		ret = proj_scal_litter_num_sm_per_tpc_v();
-		break;
-	case GPU_LIT_NUM_FBPS:
-		ret = proj_scal_litter_num_fbps_v();
-		break;
-	case GPU_LIT_GPC_BASE:
-		ret = proj_gpc_base_v();
-		break;
-	case GPU_LIT_GPC_STRIDE:
-		ret = proj_gpc_stride_v();
-		break;
-	case GPU_LIT_GPC_SHARED_BASE:
-		ret = proj_gpc_shared_base_v();
-		break;
-	case GPU_LIT_TPC_IN_GPC_BASE:
-		ret = proj_tpc_in_gpc_base_v();
-		break;
-	case GPU_LIT_TPC_IN_GPC_STRIDE:
-		ret = proj_tpc_in_gpc_stride_v();
-		break;
-	case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
-		ret = proj_tpc_in_gpc_shared_base_v();
-		break;
-	case GPU_LIT_PPC_IN_GPC_BASE:
-		ret = proj_ppc_in_gpc_base_v();
-		break;
-	case GPU_LIT_PPC_IN_GPC_STRIDE:
-		ret = proj_ppc_in_gpc_stride_v();
-		break;
-	case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
-		ret = proj_ppc_in_gpc_shared_base_v();
-		break;
-	case GPU_LIT_ROP_BASE:
-		ret = proj_rop_base_v();
-		break;
-	case GPU_LIT_ROP_STRIDE:
-		ret = proj_rop_stride_v();
-		break;
-	case GPU_LIT_ROP_SHARED_BASE:
-		ret = proj_rop_shared_base_v();
-		break;
-	case GPU_LIT_HOST_NUM_ENGINES:
-		ret = proj_host_num_engines_v();
-		break;
-	case GPU_LIT_HOST_NUM_PBDMA:
-		ret = proj_host_num_pbdma_v();
-		break;
-	case GPU_LIT_LTC_STRIDE:
-		ret = proj_ltc_stride_v();
-		break;
-	case GPU_LIT_LTS_STRIDE:
-		ret = proj_lts_stride_v();
-		break;
-	case GPU_LIT_NUM_FBPAS:
-		ret = proj_scal_litter_num_fbpas_v();
-		break;
-	case GPU_LIT_FBPA_SHARED_BASE:
-		ret = proj_fbpa_shared_base_v();
-		break;
-	case GPU_LIT_FBPA_BASE:
-		ret = proj_fbpa_base_v();
-		break;
-	case GPU_LIT_FBPA_STRIDE:
-		ret = proj_fbpa_stride_v();
-		break;
-	case GPU_LIT_SM_PRI_STRIDE:
-		ret = proj_sm_stride_v();
-		break;
-	case GPU_LIT_SMPC_PRI_BASE:
-		ret = proj_smpc_base_v();
-		break;
-	case GPU_LIT_SMPC_PRI_SHARED_BASE:
-		ret = proj_smpc_shared_base_v();
-		break;
-	case GPU_LIT_SMPC_PRI_UNIQUE_BASE:
-		ret = proj_smpc_unique_base_v();
-		break;
-	case GPU_LIT_SMPC_PRI_STRIDE:
-		ret = proj_smpc_stride_v();
-		break;
-	case GPU_LIT_TWOD_CLASS:
-		ret = FERMI_TWOD_A;
-		break;
-	case GPU_LIT_THREED_CLASS:
-		ret = VOLTA_A;
-		break;
-	case GPU_LIT_COMPUTE_CLASS:
-		ret = VOLTA_COMPUTE_A;
-		break;
-	case GPU_LIT_GPFIFO_CLASS:
-		ret = VOLTA_CHANNEL_GPFIFO_A;
-		break;
-	case GPU_LIT_I2M_CLASS:
-		ret = KEPLER_INLINE_TO_MEMORY_B;
-		break;
-	case GPU_LIT_DMA_COPY_CLASS:
-		ret = VOLTA_DMA_COPY_A;
-		break;
-	case GPU_LIT_GPC_PRIV_STRIDE:
-		ret = proj_gpc_priv_stride_v();
-		break;
-	case GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START:
-		ret = 2;
-		break;
-	case GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START:
-		ret = 9;
-		break;
-	case GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT:
-		ret = 7;
-		break;
-	case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START:
-		ret = 2;
-		break;
-	case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT:
-		ret = 4;
-		break;
-	case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START:
-		ret = 6;
-		break;
-	case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT:
-		ret = 2;
-		break;
-	default:
-		nvgpu_err(g, "Missing definition %d", value);
-		BUG();
-		break;
-	}
-
-	return ret;
-}
-
 static void gv100_init_gpu_characteristics(struct gk20a *g)
 {
 	gk20a_init_gpu_characteristics(g);

drivers/gpu/nvgpu/hal/init/hal_gv100_litter.c

@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/class.h>
+
+#include <nvgpu/hw/gv100/hw_proj_gv100.h>
+
+#include "hal_gv100_litter.h"
+
+u32 gv100_get_litter_value(struct gk20a *g, int value)
+{
+	u32 ret = 0;
+
+	switch (value) {
+	case GPU_LIT_NUM_GPCS:
+		ret = proj_scal_litter_num_gpcs_v();
+		break;
+	case GPU_LIT_NUM_PES_PER_GPC:
+		ret = proj_scal_litter_num_pes_per_gpc_v();
+		break;
+	case GPU_LIT_NUM_ZCULL_BANKS:
+		ret = proj_scal_litter_num_zcull_banks_v();
+		break;
+	case GPU_LIT_NUM_TPC_PER_GPC:
+		ret = proj_scal_litter_num_tpc_per_gpc_v();
+		break;
+	case GPU_LIT_NUM_SM_PER_TPC:
+		ret = proj_scal_litter_num_sm_per_tpc_v();
+		break;
+	case GPU_LIT_NUM_FBPS:
+		ret = proj_scal_litter_num_fbps_v();
+		break;
+	case GPU_LIT_GPC_BASE:
+		ret = proj_gpc_base_v();
+		break;
+	case GPU_LIT_GPC_STRIDE:
+		ret = proj_gpc_stride_v();
+		break;
+	case GPU_LIT_GPC_SHARED_BASE:
+		ret = proj_gpc_shared_base_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_BASE:
+		ret = proj_tpc_in_gpc_base_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_STRIDE:
+		ret = proj_tpc_in_gpc_stride_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
+		ret = proj_tpc_in_gpc_shared_base_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_BASE:
+		ret = proj_ppc_in_gpc_base_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_STRIDE:
+		ret = proj_ppc_in_gpc_stride_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
+		ret = proj_ppc_in_gpc_shared_base_v();
+		break;
+	case GPU_LIT_ROP_BASE:
+		ret = proj_rop_base_v();
+		break;
+	case GPU_LIT_ROP_STRIDE:
+		ret = proj_rop_stride_v();
+		break;
+	case GPU_LIT_ROP_SHARED_BASE:
+		ret = proj_rop_shared_base_v();
+		break;
+	case GPU_LIT_HOST_NUM_ENGINES:
+		ret = proj_host_num_engines_v();
+		break;
+	case GPU_LIT_HOST_NUM_PBDMA:
+		ret = proj_host_num_pbdma_v();
+		break;
+	case GPU_LIT_LTC_STRIDE:
+		ret = proj_ltc_stride_v();
+		break;
+	case GPU_LIT_LTS_STRIDE:
+		ret = proj_lts_stride_v();
+		break;
+	case GPU_LIT_NUM_FBPAS:
+		ret = proj_scal_litter_num_fbpas_v();
+		break;
+	case GPU_LIT_FBPA_SHARED_BASE:
+		ret = proj_fbpa_shared_base_v();
+		break;
+	case GPU_LIT_FBPA_BASE:
+		ret = proj_fbpa_base_v();
+		break;
+	case GPU_LIT_FBPA_STRIDE:
+		ret = proj_fbpa_stride_v();
+		break;
+	case GPU_LIT_SM_PRI_STRIDE:
+		ret = proj_sm_stride_v();
+		break;
+	case GPU_LIT_SMPC_PRI_BASE:
+		ret = proj_smpc_base_v();
+		break;
+	case GPU_LIT_SMPC_PRI_SHARED_BASE:
+		ret = proj_smpc_shared_base_v();
+		break;
+	case GPU_LIT_SMPC_PRI_UNIQUE_BASE:
+		ret = proj_smpc_unique_base_v();
+		break;
+	case GPU_LIT_SMPC_PRI_STRIDE:
+		ret = proj_smpc_stride_v();
+		break;
+	case GPU_LIT_TWOD_CLASS:
+		ret = FERMI_TWOD_A;
+		break;
+	case GPU_LIT_THREED_CLASS:
+		ret = VOLTA_A;
+		break;
+	case GPU_LIT_COMPUTE_CLASS:
+		ret = VOLTA_COMPUTE_A;
+		break;
+	case GPU_LIT_GPFIFO_CLASS:
+		ret = VOLTA_CHANNEL_GPFIFO_A;
+		break;
+	case GPU_LIT_I2M_CLASS:
+		ret = KEPLER_INLINE_TO_MEMORY_B;
+		break;
+	case GPU_LIT_DMA_COPY_CLASS:
+		ret = VOLTA_DMA_COPY_A;
+		break;
+	case GPU_LIT_GPC_PRIV_STRIDE:
+		ret = proj_gpc_priv_stride_v();
+		break;
+	case GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START:
+		ret = 2;
+		break;
+	case GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START:
+		ret = 9;
+		break;
+	case GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT:
+		ret = 7;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START:
+		ret = 2;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT:
+		ret = 4;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START:
+		ret = 6;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT:
+		ret = 2;
+		break;
+	default:
+		nvgpu_err(g, "Missing definition %d", value);
+		BUG();
+		break;
+	}
+
+	return ret;
+}
+

drivers/gpu/nvgpu/hal/init/hal_gv100_litter.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_HAL_GV100_LITTER_H
+#define NVGPU_HAL_GV100_LITTER_H
+
+u32 gv100_get_litter_value(struct gk20a *g, int value);
+
+#endif /* NVGPU_HAL_GV100_LITTER_H */

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -22,7 +22,6 @@
  * DEALINGS IN THE SOFTWARE.
  */
 #include <nvgpu/gk20a.h>
-#include <nvgpu/class.h>
 #include <nvgpu/fuse.h>
 #include <nvgpu/pbdma.h>
 #include <nvgpu/regops.h>
@@ -143,6 +142,7 @@
 #include "common/clk_arb/clk_arb_gp10b.h"
 
 #include "hal_gv11b.h"
+#include "hal_gv11b_litter.h"
 #include "gv11b/mm_gv11b.h"
 
 #include <nvgpu/ptimer.h>
@@ -157,7 +157,6 @@
 #include <nvgpu/gr/fecs_trace.h>
 #include <nvgpu/gr/gr_intr.h>
 
-#include <nvgpu/hw/gv11b/hw_proj_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
 
 static void gv11b_init_gpu_characteristics(struct gk20a *g)
@@ -172,155 +171,6 @@ static void gv11b_init_gpu_characteristics(struct gk20a *g)
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_USERMODE_SUBMIT, true);
 }
 
-u32 gv11b_get_litter_value(struct gk20a *g, int value)
-{
-	u32 ret = 0;
-	switch (value) {
-	case GPU_LIT_NUM_GPCS:
-		ret = proj_scal_litter_num_gpcs_v();
-		break;
-	case GPU_LIT_NUM_PES_PER_GPC:
-		ret = proj_scal_litter_num_pes_per_gpc_v();
-		break;
-	case GPU_LIT_NUM_ZCULL_BANKS:
-		ret = proj_scal_litter_num_zcull_banks_v();
-		break;
-	case GPU_LIT_NUM_TPC_PER_GPC:
-		ret = proj_scal_litter_num_tpc_per_gpc_v();
-		break;
-	case GPU_LIT_NUM_SM_PER_TPC:
-		ret = proj_scal_litter_num_sm_per_tpc_v();
-		break;
-	case GPU_LIT_NUM_FBPS:
-		ret = proj_scal_litter_num_fbps_v();
-		break;
-	case GPU_LIT_GPC_BASE:
-		ret = proj_gpc_base_v();
-		break;
-	case GPU_LIT_GPC_STRIDE:
-		ret = proj_gpc_stride_v();
-		break;
-	case GPU_LIT_GPC_SHARED_BASE:
-		ret = proj_gpc_shared_base_v();
-		break;
-	case GPU_LIT_TPC_IN_GPC_BASE:
-		ret = proj_tpc_in_gpc_base_v();
-		break;
-	case GPU_LIT_TPC_IN_GPC_STRIDE:
-		ret = proj_tpc_in_gpc_stride_v();
-		break;
-	case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
-		ret = proj_tpc_in_gpc_shared_base_v();
-		break;
-	case GPU_LIT_PPC_IN_GPC_BASE:
-		ret = proj_ppc_in_gpc_base_v();
-		break;
-	case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
-		ret = proj_ppc_in_gpc_shared_base_v();
-		break;
-	case GPU_LIT_PPC_IN_GPC_STRIDE:
-		ret = proj_ppc_in_gpc_stride_v();
-		break;
-	case GPU_LIT_ROP_BASE:
-		ret = proj_rop_base_v();
-		break;
-	case GPU_LIT_ROP_STRIDE:
-		ret = proj_rop_stride_v();
-		break;
-	case GPU_LIT_ROP_SHARED_BASE:
-		ret = proj_rop_shared_base_v();
-		break;
-	case GPU_LIT_HOST_NUM_ENGINES:
-		ret = proj_host_num_engines_v();
-		break;
-	case GPU_LIT_HOST_NUM_PBDMA:
-		ret = proj_host_num_pbdma_v();
-		break;
-	case GPU_LIT_LTC_STRIDE:
-		ret = proj_ltc_stride_v();
-		break;
-	case GPU_LIT_LTS_STRIDE:
-		ret = proj_lts_stride_v();
-		break;
-	case GPU_LIT_SM_PRI_STRIDE:
-		ret = proj_sm_stride_v();
-		break;
-	case GPU_LIT_SMPC_PRI_BASE:
-		ret = proj_smpc_base_v();
-		break;
-	case GPU_LIT_SMPC_PRI_SHARED_BASE:
-		ret = proj_smpc_shared_base_v();
-		break;
-	case GPU_LIT_SMPC_PRI_UNIQUE_BASE:
-		ret = proj_smpc_unique_base_v();
-		break;
-	case GPU_LIT_SMPC_PRI_STRIDE:
-		ret = proj_smpc_stride_v();
-		break;
-	/* Even though GV11B doesn't have an FBPA unit, the HW reports one,
-	 * and the microcode as a result leaves space in the context buffer
-	 * for one, so make sure SW accounts for this also.
-	 */
-	case GPU_LIT_NUM_FBPAS:
-		ret = proj_scal_litter_num_fbpas_v();
-		break;
-	/* Hardcode FBPA values other than NUM_FBPAS to 0. */
-	case GPU_LIT_FBPA_STRIDE:
-	case GPU_LIT_FBPA_BASE:
-	case GPU_LIT_FBPA_SHARED_BASE:
-		ret = 0;
-		break;
-	case GPU_LIT_TWOD_CLASS:
-		ret = FERMI_TWOD_A;
-		break;
-	case GPU_LIT_THREED_CLASS:
-		ret = VOLTA_A;
-		break;
-	case GPU_LIT_COMPUTE_CLASS:
-		ret = VOLTA_COMPUTE_A;
-		break;
-	case GPU_LIT_GPFIFO_CLASS:
-		ret = VOLTA_CHANNEL_GPFIFO_A;
-		break;
-	case GPU_LIT_I2M_CLASS:
-		ret = KEPLER_INLINE_TO_MEMORY_B;
-		break;
-	case GPU_LIT_DMA_COPY_CLASS:
-		ret = VOLTA_DMA_COPY_A;
-		break;
-	case GPU_LIT_GPC_PRIV_STRIDE:
-		ret = proj_gpc_priv_stride_v();
-		break;
-	case GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START:
-		ret = 2;
-		break;
-	case GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START:
-		ret = 6;
-		break;
-	case GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT:
-		ret = 4;
-		break;
-	case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START:
-		ret = 1;
-		break;
-	case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT:
-		ret = 2;
-		break;
-	case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START:
-		ret = 3;
-		break;
-	case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT:
-		ret = 2;
-		break;
-	default:
-		nvgpu_err(g, "Missing definition %d", value);
-		BUG();
-		break;
-	}
-
-	return ret;
-}
-
 static const struct gpu_ops gv11b_ops = {
 	.ltc = {
 		.determine_L2_size_bytes = gp10b_determine_L2_size_bytes,

drivers/gpu/nvgpu/hal/init/hal_gv11b.h

@@ -1,7 +1,7 @@
 /*
  * GV11B Tegra HAL interface
  *
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -27,5 +27,4 @@
 struct gk20a;
 
 int gv11b_init_hal(struct gk20a *g);
-u32 gv11b_get_litter_value(struct gk20a *g, int value);
 #endif /* NVGPU_HAL_GV11B_H */

drivers/gpu/nvgpu/hal/init/hal_gv11b_litter.c

@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/class.h>
+
+#include <nvgpu/hw/gv11b/hw_proj_gv11b.h>
+
+#include "hal_gv11b_litter.h"
+
+u32 gv11b_get_litter_value(struct gk20a *g, int value)
+{
+	u32 ret = 0;
+
+	switch (value) {
+	case GPU_LIT_NUM_GPCS:
+		ret = proj_scal_litter_num_gpcs_v();
+		break;
+	case GPU_LIT_NUM_PES_PER_GPC:
+		ret = proj_scal_litter_num_pes_per_gpc_v();
+		break;
+	case GPU_LIT_NUM_ZCULL_BANKS:
+		ret = proj_scal_litter_num_zcull_banks_v();
+		break;
+	case GPU_LIT_NUM_TPC_PER_GPC:
+		ret = proj_scal_litter_num_tpc_per_gpc_v();
+		break;
+	case GPU_LIT_NUM_SM_PER_TPC:
+		ret = proj_scal_litter_num_sm_per_tpc_v();
+		break;
+	case GPU_LIT_NUM_FBPS:
+		ret = proj_scal_litter_num_fbps_v();
+		break;
+	case GPU_LIT_GPC_BASE:
+		ret = proj_gpc_base_v();
+		break;
+	case GPU_LIT_GPC_STRIDE:
+		ret = proj_gpc_stride_v();
+		break;
+	case GPU_LIT_GPC_SHARED_BASE:
+		ret = proj_gpc_shared_base_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_BASE:
+		ret = proj_tpc_in_gpc_base_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_STRIDE:
+		ret = proj_tpc_in_gpc_stride_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
+		ret = proj_tpc_in_gpc_shared_base_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_BASE:
+		ret = proj_ppc_in_gpc_base_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
+		ret = proj_ppc_in_gpc_shared_base_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_STRIDE:
+		ret = proj_ppc_in_gpc_stride_v();
+		break;
+	case GPU_LIT_ROP_BASE:
+		ret = proj_rop_base_v();
+		break;
+	case GPU_LIT_ROP_STRIDE:
+		ret = proj_rop_stride_v();
+		break;
+	case GPU_LIT_ROP_SHARED_BASE:
+		ret = proj_rop_shared_base_v();
+		break;
+	case GPU_LIT_HOST_NUM_ENGINES:
+		ret = proj_host_num_engines_v();
+		break;
+	case GPU_LIT_HOST_NUM_PBDMA:
+		ret = proj_host_num_pbdma_v();
+		break;
+	case GPU_LIT_LTC_STRIDE:
+		ret = proj_ltc_stride_v();
+		break;
+	case GPU_LIT_LTS_STRIDE:
+		ret = proj_lts_stride_v();
+		break;
+	case GPU_LIT_SM_PRI_STRIDE:
+		ret = proj_sm_stride_v();
+		break;
+	case GPU_LIT_SMPC_PRI_BASE:
+		ret = proj_smpc_base_v();
+		break;
+	case GPU_LIT_SMPC_PRI_SHARED_BASE:
+		ret = proj_smpc_shared_base_v();
+		break;
+	case GPU_LIT_SMPC_PRI_UNIQUE_BASE:
+		ret = proj_smpc_unique_base_v();
+		break;
+	case GPU_LIT_SMPC_PRI_STRIDE:
+		ret = proj_smpc_stride_v();
+		break;
+	/* Even though GV11B doesn't have an FBPA unit, the HW reports one,
+	 * and the microcode as a result leaves space in the context buffer
+	 * for one, so make sure SW accounts for this also.
+	 */
+	case GPU_LIT_NUM_FBPAS:
+		ret = proj_scal_litter_num_fbpas_v();
+		break;
+	/* Hardcode FBPA values other than NUM_FBPAS to 0. */
+	case GPU_LIT_FBPA_STRIDE:
+	case GPU_LIT_FBPA_BASE:
+	case GPU_LIT_FBPA_SHARED_BASE:
+		ret = 0;
+		break;
+	case GPU_LIT_TWOD_CLASS:
+		ret = FERMI_TWOD_A;
+		break;
+	case GPU_LIT_THREED_CLASS:
+		ret = VOLTA_A;
+		break;
+	case GPU_LIT_COMPUTE_CLASS:
+		ret = VOLTA_COMPUTE_A;
+		break;
+	case GPU_LIT_GPFIFO_CLASS:
+		ret = VOLTA_CHANNEL_GPFIFO_A;
+		break;
+	case GPU_LIT_I2M_CLASS:
+		ret = KEPLER_INLINE_TO_MEMORY_B;
+		break;
+	case GPU_LIT_DMA_COPY_CLASS:
+		ret = VOLTA_DMA_COPY_A;
+		break;
+	case GPU_LIT_GPC_PRIV_STRIDE:
+		ret = proj_gpc_priv_stride_v();
+		break;
+	case GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START:
+		ret = 2;
+		break;
+	case GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START:
+		ret = 6;
+		break;
+	case GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT:
+		ret = 4;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START:
+		ret = 1;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT:
+		ret = 2;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START:
+		ret = 3;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT:
+		ret = 2;
+		break;
+	default:
+		nvgpu_err(g, "Missing definition %d", value);
+		BUG();
+		break;
+	}
+
+	return ret;
+}
+

drivers/gpu/nvgpu/hal/init/hal_gv11b_litter.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_HAL_GV11B_LITTER_H
+#define NVGPU_HAL_GV11B_LITTER_H
+
+u32 gv11b_get_litter_value(struct gk20a *g, int value);
+
+#endif /* NVGPU_HAL_GV11B_LITTER_H */

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -178,6 +178,7 @@
 #include "tu104/mm_tu104.h"
 #include "hal/fbpa/fbpa_tu104.h"
 #include "hal_tu104.h"
+#include "hal_tu104_litter.h"
 
 #include <nvgpu/ptimer.h>
 #include <nvgpu/error_notifier.h>
@@ -199,158 +200,9 @@
 #include <nvgpu/gr/gr_intr.h>
 #include <nvgpu/pmu/pmu_perfmon.h>
 
-#include <nvgpu/hw/tu104/hw_proj_tu104.h>
 #include <nvgpu/hw/tu104/hw_pram_tu104.h>
 #include <nvgpu/hw/tu104/hw_pwr_tu104.h>
 
-static u32 tu104_get_litter_value(struct gk20a *g, int value)
-{
-	u32 ret = 0;
-	switch (value) {
-	case GPU_LIT_NUM_GPCS:
-		ret = proj_scal_litter_num_gpcs_v();
-		break;
-	case GPU_LIT_NUM_PES_PER_GPC:
-		ret = proj_scal_litter_num_pes_per_gpc_v();
-		break;
-	case GPU_LIT_NUM_ZCULL_BANKS:
-		ret = proj_scal_litter_num_zcull_banks_v();
-		break;
-	case GPU_LIT_NUM_TPC_PER_GPC:
-		ret = proj_scal_litter_num_tpc_per_gpc_v();
-		break;
-	case GPU_LIT_NUM_SM_PER_TPC:
-		ret = proj_scal_litter_num_sm_per_tpc_v();
-		break;
-	case GPU_LIT_NUM_FBPS:
-		ret = proj_scal_litter_num_fbps_v();
-		break;
-	case GPU_LIT_GPC_BASE:
-		ret = proj_gpc_base_v();
-		break;
-	case GPU_LIT_GPC_STRIDE:
-		ret = proj_gpc_stride_v();
-		break;
-	case GPU_LIT_GPC_SHARED_BASE:
-		ret = proj_gpc_shared_base_v();
-		break;
-	case GPU_LIT_TPC_IN_GPC_BASE:
-		ret = proj_tpc_in_gpc_base_v();
-		break;
-	case GPU_LIT_TPC_IN_GPC_STRIDE:
-		ret = proj_tpc_in_gpc_stride_v();
-		break;
-	case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
-		ret = proj_tpc_in_gpc_shared_base_v();
-		break;
-	case GPU_LIT_PPC_IN_GPC_BASE:
-		ret = proj_ppc_in_gpc_base_v();
-		break;
-	case GPU_LIT_PPC_IN_GPC_STRIDE:
-		ret = proj_ppc_in_gpc_stride_v();
-		break;
-	case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
-		ret = proj_ppc_in_gpc_shared_base_v();
-		break;
-	case GPU_LIT_ROP_BASE:
-		ret = proj_rop_base_v();
-		break;
-	case GPU_LIT_ROP_STRIDE:
-		ret = proj_rop_stride_v();
-		break;
-	case GPU_LIT_ROP_SHARED_BASE:
-		ret = proj_rop_shared_base_v();
-		break;
-	case GPU_LIT_HOST_NUM_ENGINES:
-		ret = proj_host_num_engines_v();
-		break;
-	case GPU_LIT_HOST_NUM_PBDMA:
-		ret = proj_host_num_pbdma_v();
-		break;
-	case GPU_LIT_LTC_STRIDE:
-		ret = proj_ltc_stride_v();
-		break;
-	case GPU_LIT_LTS_STRIDE:
-		ret = proj_lts_stride_v();
-		break;
-	case GPU_LIT_NUM_FBPAS:
-		ret = proj_scal_litter_num_fbpas_v();
-		break;
-	case GPU_LIT_FBPA_SHARED_BASE:
-		ret = proj_fbpa_shared_base_v();
-		break;
-	case GPU_LIT_FBPA_BASE:
-		ret = proj_fbpa_base_v();
-		break;
-	case GPU_LIT_FBPA_STRIDE:
-		ret = proj_fbpa_stride_v();
-		break;
-	case GPU_LIT_SM_PRI_STRIDE:
-		ret = proj_sm_stride_v();
-		break;
-	case GPU_LIT_SMPC_PRI_BASE:
-		ret = proj_smpc_base_v();
-		break;
-	case GPU_LIT_SMPC_PRI_SHARED_BASE:
-		ret = proj_smpc_shared_base_v();
-		break;
-	case GPU_LIT_SMPC_PRI_UNIQUE_BASE:
-		ret = proj_smpc_unique_base_v();
-		break;
-	case GPU_LIT_SMPC_PRI_STRIDE:
-		ret = proj_smpc_stride_v();
-		break;
-	case GPU_LIT_TWOD_CLASS:
-		ret = FERMI_TWOD_A;
-		break;
-	case GPU_LIT_THREED_CLASS:
-		ret = TURING_A;
-		break;
-	case GPU_LIT_COMPUTE_CLASS:
-		ret = TURING_COMPUTE_A;
-		break;
-	case GPU_LIT_GPFIFO_CLASS:
-		ret = TURING_CHANNEL_GPFIFO_A;
-		break;
-	case GPU_LIT_I2M_CLASS:
-		ret = KEPLER_INLINE_TO_MEMORY_B;
-		break;
-	case GPU_LIT_DMA_COPY_CLASS:
-		ret = TURING_DMA_COPY_A;
-		break;
-	case GPU_LIT_GPC_PRIV_STRIDE:
-		ret = proj_gpc_priv_stride_v();
-		break;
-	case GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START:
-		ret = 2;
-		break;
-	case GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START:
-		ret = 8;
-		break;
-	case GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT:
-		ret = 6;
-		break;
-	case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START:
-		ret = 2;
-		break;
-	case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT:
-		ret = 8;
-		break;
-	case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START:
-		ret = 10;
-		break;
-	case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT:
-		ret = 2;
-		break;
-	default:
-		nvgpu_err(g, "Missing definition %d", value);
-		BUG();
-		break;
-	}
-
-	return ret;
-}
-
 static void tu104_init_gpu_characteristics(struct gk20a *g)
 {
 	gk20a_init_gpu_characteristics(g);

drivers/gpu/nvgpu/hal/init/hal_tu104_litter.c

@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/class.h>
+
+#include <nvgpu/hw/tu104/hw_proj_tu104.h>
+
+#include "hal_tu104_litter.h"
+
+u32 tu104_get_litter_value(struct gk20a *g, int value)
+{
+	u32 ret = 0;
+
+	switch (value) {
+	case GPU_LIT_NUM_GPCS:
+		ret = proj_scal_litter_num_gpcs_v();
+		break;
+	case GPU_LIT_NUM_PES_PER_GPC:
+		ret = proj_scal_litter_num_pes_per_gpc_v();
+		break;
+	case GPU_LIT_NUM_ZCULL_BANKS:
+		ret = proj_scal_litter_num_zcull_banks_v();
+		break;
+	case GPU_LIT_NUM_TPC_PER_GPC:
+		ret = proj_scal_litter_num_tpc_per_gpc_v();
+		break;
+	case GPU_LIT_NUM_SM_PER_TPC:
+		ret = proj_scal_litter_num_sm_per_tpc_v();
+		break;
+	case GPU_LIT_NUM_FBPS:
+		ret = proj_scal_litter_num_fbps_v();
+		break;
+	case GPU_LIT_GPC_BASE:
+		ret = proj_gpc_base_v();
+		break;
+	case GPU_LIT_GPC_STRIDE:
+		ret = proj_gpc_stride_v();
+		break;
+	case GPU_LIT_GPC_SHARED_BASE:
+		ret = proj_gpc_shared_base_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_BASE:
+		ret = proj_tpc_in_gpc_base_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_STRIDE:
+		ret = proj_tpc_in_gpc_stride_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
+		ret = proj_tpc_in_gpc_shared_base_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_BASE:
+		ret = proj_ppc_in_gpc_base_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_STRIDE:
+		ret = proj_ppc_in_gpc_stride_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
+		ret = proj_ppc_in_gpc_shared_base_v();
+		break;
+	case GPU_LIT_ROP_BASE:
+		ret = proj_rop_base_v();
+		break;
+	case GPU_LIT_ROP_STRIDE:
+		ret = proj_rop_stride_v();
+		break;
+	case GPU_LIT_ROP_SHARED_BASE:
+		ret = proj_rop_shared_base_v();
+		break;
+	case GPU_LIT_HOST_NUM_ENGINES:
+		ret = proj_host_num_engines_v();
+		break;
+	case GPU_LIT_HOST_NUM_PBDMA:
+		ret = proj_host_num_pbdma_v();
+		break;
+	case GPU_LIT_LTC_STRIDE:
+		ret = proj_ltc_stride_v();
+		break;
+	case GPU_LIT_LTS_STRIDE:
+		ret = proj_lts_stride_v();
+		break;
+	case GPU_LIT_NUM_FBPAS:
+		ret = proj_scal_litter_num_fbpas_v();
+		break;
+	case GPU_LIT_FBPA_SHARED_BASE:
+		ret = proj_fbpa_shared_base_v();
+		break;
+	case GPU_LIT_FBPA_BASE:
+		ret = proj_fbpa_base_v();
+		break;
+	case GPU_LIT_FBPA_STRIDE:
+		ret = proj_fbpa_stride_v();
+		break;
+	case GPU_LIT_SM_PRI_STRIDE:
+		ret = proj_sm_stride_v();
+		break;
+	case GPU_LIT_SMPC_PRI_BASE:
+		ret = proj_smpc_base_v();
+		break;
+	case GPU_LIT_SMPC_PRI_SHARED_BASE:
+		ret = proj_smpc_shared_base_v();
+		break;
+	case GPU_LIT_SMPC_PRI_UNIQUE_BASE:
+		ret = proj_smpc_unique_base_v();
+		break;
+	case GPU_LIT_SMPC_PRI_STRIDE:
+		ret = proj_smpc_stride_v();
+		break;
+	case GPU_LIT_TWOD_CLASS:
+		ret = FERMI_TWOD_A;
+		break;
+	case GPU_LIT_THREED_CLASS:
+		ret = TURING_A;
+		break;
+	case GPU_LIT_COMPUTE_CLASS:
+		ret = TURING_COMPUTE_A;
+		break;
+	case GPU_LIT_GPFIFO_CLASS:
+		ret = TURING_CHANNEL_GPFIFO_A;
+		break;
+	case GPU_LIT_I2M_CLASS:
+		ret = KEPLER_INLINE_TO_MEMORY_B;
+		break;
+	case GPU_LIT_DMA_COPY_CLASS:
+		ret = TURING_DMA_COPY_A;
+		break;
+	case GPU_LIT_GPC_PRIV_STRIDE:
+		ret = proj_gpc_priv_stride_v();
+		break;
+	case GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START:
+		ret = 2;
+		break;
+	case GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START:
+		ret = 8;
+		break;
+	case GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT:
+		ret = 6;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START:
+		ret = 2;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT:
+		ret = 8;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START:
+		ret = 10;
+		break;
+	case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT:
+		ret = 2;
+		break;
+	default:
+		nvgpu_err(g, "Missing definition %d", value);
+		BUG();
+		break;
+	}
+
+	return ret;
+}
+

drivers/gpu/nvgpu/hal/init/hal_tu104_litter.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_HAL_TU104_LITTER_H
+#define NVGPU_HAL_TU104_LITTER_H
+
+u32 tu104_get_litter_value(struct gk20a *g, int value);
+
+#endif /* NVGPU_HAL_TU104_LITTER_H */