gpu: nvgpu: hal: split MM-related HALs based on FUSA

This patch moves MM HALs that are guaranteed to be functionaly safe
into _fusa.c files. HALs that are not part of FUSA are not compiled
anymore when the safety profile is enabled.

Given a HAL source file:
- it may contain only FUSA code, in that case the source file is
  simply renamed with the _fusa postfix.
- it may contain only non-FUSA code, in that case the file is left
  as-is
- it may contain a mix, in that case the original file will now only
  contain non-FUSA code, and all FUSA code will be moved into a new
  source file with the _fusa postfix.

JIRA NVGPU-3690

Change-Id: I44c604aef2d72252abb7da1c0ef1210d71a0efa7
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2140895
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile.sources

@@ -148,17 +148,6 @@ srcs += common/utils/enabled.c \
 	common/clk_arb/clk_arb.c \
 	common/clk_arb/clk_arb_gp10b.c \
 	common/fence/fence.c \
-	hal/mm/mm_gk20a.c \
-	hal/mm/mm_gm20b.c \
-	hal/mm/mm_gp10b.c \
-	hal/mm/mm_gv11b.c \
-	hal/mm/cache/flush_gk20a.c \
-	hal/mm/cache/flush_gv11b.c \
-	hal/mm/mmu_fault/mmu_fault_gv11b.c \
-	hal/mm/gmmu/gmmu_gk20a.c \
-	hal/mm/gmmu/gmmu_gm20b.c \
-	hal/mm/gmmu/gmmu_gp10b.c \
-	hal/mm/gmmu/gmmu_gv11b.c \
 	hal/mc/mc_gm20b.c  \
 	hal/mc/mc_gp10b.c  \
 	hal/mc/mc_gv11b.c  \
@@ -270,13 +259,28 @@ srcs += common/utils/enabled.c \
 	hal/top/top_gp106.c \
 	hal/top/top_gv11b.c
 
+# Source files below are functionaly safe (FuSa) and must always be included.
+srcs += hal/mm/mm_gv11b_fusa.c \
+	hal/mm/mm_gp10b_fusa.c \
+	hal/mm/gmmu/gmmu_gv11b_fusa.c \
+	hal/mm/gmmu/gmmu_gp10b_fusa.c \
+	hal/mm/gmmu/gmmu_gk20a_fusa.c \
+	hal/mm/gmmu/gmmu_gm20b_fusa.c \
+	hal/mm/cache/flush_gk20a_fusa.c \
+	hal/mm/cache/flush_gv11b_fusa.c \
+	hal/mm/mmu_fault/mmu_fault_gv11b_fusa.c
+
 # Source files below are not guaranteed to be functionaly safe (FuSa) and are
 # only included in the normal build.
 ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1)
 srcs += hal/init/hal_gp10b.c \
 	hal/init/hal_gp10b_litter.c \
 	hal/init/hal_gm20b.c \
-	hal/init/hal_gm20b_litter.c
+	hal/init/hal_gm20b_litter.c \
+	hal/mm/mm_gm20b.c \
+	hal/mm/mm_gk20a.c \
+	hal/mm/gmmu/gmmu_gk20a.c \
+	hal/mm/gmmu/gmmu_gm20b.c
 endif
 
 ifeq ($(CONFIG_NVGPU_ACR_LEGACY),1)

drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gk20a.c

@@ -235,24 +235,6 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm,
 	nvgpu_pd_write(g, pd, (size_t)pd_offset + (size_t)1, pte_w[1]);
 }
 
-u32 gk20a_get_pde_pgsz(struct gk20a *g, const struct gk20a_mmu_level *l,
-				struct nvgpu_gmmu_pd *pd, u32 pd_idx)
-{
-	/*
-	 * big and small page sizes are the same
-	 */
-	return GMMU_PAGE_SIZE_SMALL;
-}
-
-u32 gk20a_get_pte_pgsz(struct gk20a *g, const struct gk20a_mmu_level *l,
-				struct nvgpu_gmmu_pd *pd, u32 pd_idx)
-{
-	/*
-	 * return invalid
-	 */
-	return GMMU_NR_PAGE_SIZES;
-}
-
 const struct gk20a_mmu_level gk20a_mm_levels_64k[] = {
 	{.hi_bit = {NV_GMMU_VA_RANGE-1, NV_GMMU_VA_RANGE-1},
 	 .lo_bit = {26, 26},

drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gk20a_fusa.c

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/gmmu.h>
+
+#include "gmmu_gk20a.h"
+
+u32 gk20a_get_pde_pgsz(struct gk20a *g, const struct gk20a_mmu_level *l,
+				struct nvgpu_gmmu_pd *pd, u32 pd_idx)
+{
+	/*
+	 * big and small page sizes are the same
+	 */
+	return GMMU_PAGE_SIZE_SMALL;
+}
+
+u32 gk20a_get_pte_pgsz(struct gk20a *g, const struct gk20a_mmu_level *l,
+				struct nvgpu_gmmu_pd *pd, u32 pd_idx)
+{
+	/*
+	 * return invalid
+	 */
+	return GMMU_NR_PAGE_SIZES;
+}

drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gm20b.c

@@ -27,11 +27,6 @@
 
 #include "gmmu_gm20b.h"
 
-u32 gm20b_mm_get_big_page_sizes(void)
-{
-	return U32(SZ_64K | SZ_128K);
-}
-
 u32 gm20b_mm_get_default_big_page_size(void)
 {
 	return U32(SZ_64K);

drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gm20b_fusa.c

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/gmmu.h>
+
+#include "gmmu_gm20b.h"
+
+u32 gm20b_mm_get_big_page_sizes(void)
+{
+	return U32(SZ_64K | SZ_128K);
+}
+