From 9adc7a6542cc19fcc9fff2ac8da6b357aeb96eec Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Tue, 30 Oct 2018 17:29:05 +0200 Subject: [PATCH] gpu: nvgpu: fix MISRA errors in runlist Fix some mistakes from commit 0fbc1a265240 (gpu: nvgpu: avoid recursion in runlist construction) and commit 998bf379df11 (gpu: nvgpu: add runlist_append_tsg) for MISRA rules 10.3 and 10.4. - cast a sizeof to u32 in a calculation to match in size, - make the NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_* constants unsigned to make comparisons match in signedness. Jira NVGPU-1174 Change-Id: I00aa9758ca4352d8eb53a0e8ded42a1ba3b14561 Signed-off-by: Konsta Holtta Reviewed-on: https://git-master.nvidia.com/r/1938069 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 2 +- drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 10 ++++------ 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index cfc3490b7..53841fc76 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -3330,7 +3330,7 @@ static u32 nvgpu_runlist_append_tsg(struct gk20a *g, struct tsg_gk20a *tsg) { struct fifo_gk20a *f = &g->fifo; - u32 runlist_entry_words = f->runlist_entry_size / sizeof(u32); + u32 runlist_entry_words = f->runlist_entry_size / (u32)sizeof(u32); struct channel_gk20a *ch; u32 count = 0; diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index f9408eb95..69d757ead 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h @@ -32,12 +32,10 @@ struct nvgpu_semaphore; struct channel_gk20a; struct tsg_gk20a; -enum { - NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW = 0U, - NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM = 1U, - NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH = 2U, - NVGPU_FIFO_RUNLIST_INTERLEAVE_NUM_LEVELS = 3U, -}; +#define NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW 0U +#define NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM 1U +#define NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH 2U +#define NVGPU_FIFO_RUNLIST_INTERLEAVE_NUM_LEVELS 3U #define MAX_RUNLIST_BUFFERS 2