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gpu: nvgpu: gv11b: chip revision check for invalidates

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Only for T194 A01 version following invalidates are disabled:
-CBM alpha and beta invalidations for L2
-SCC pagepool invalidates
-SWDX spill buffer invalidates

Bug 2053668

Change-Id: I7122b223946a1bfa4b11ed8ee782572215313dc1
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1680500
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
seshendra Gadagottu
2018-03-26 18:23:52 -07:00
committed by mobile promotions
parent 67c4571d95
commit 9ae69536b9
3 changed files with 15 additions and 6 deletions
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8
drivers/gpu/nvgpu/common/linux/soc.c
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@@ -12,6 +12,7 @@
*/
#include <soc/tegra/chip-id.h>
#include <soc/tegra/fuse.h>
#include <soc/tegra/tegra_bpmp.h>
#ifdef CONFIG_TEGRA_HV_MANAGER
#include <soc/tegra/virt/syscalls.h>
@@ -46,6 +47,13 @@ bool nvgpu_is_bpmp_running(struct gk20a *g)
return tegra_bpmp_running();
}
bool nvgpu_is_soc_t194_a01(struct gk20a *g)
{
return ((tegra_get_chip_id() == TEGRA194 &&
tegra_chip_get_revision() == TEGRA194_REVISION_A01) ?
true : false);
}
#ifdef CONFIG_TEGRA_HV_MANAGER
/* When nvlink is enabled on dGPU, we need to use physical memory addresses.
* There is no SMMU translation. However, the device initially enumerates as a