diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
index b2a21a7ce..1f1e603bd 100644
--- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -46,6 +46,7 @@
 #include "hal/gr/init/gr_init_gm20b.h"
 #include "hal/gr/init/gr_init_gp10b.h"
 #include "hal/gr/init/gr_init_gv11b.h"
+#include "hal/gr/intr/gr_intr_gv11b.h"
 #include "hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h"
 #include "hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h"
 #include "hal/gr/ctxsw_prog/ctxsw_prog_gv11b.h"
@@ -207,7 +208,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.set_ctxsw_preemption_mode = vgpu_gr_set_ctxsw_preemption_mode,
 		.is_etpc_addr = gv11b_gr_pri_is_etpc_addr,
 		.egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table,
-		.handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception,
 		.handle_gpc_gpcmmu_exception =
 			gr_gv11b_handle_gpc_gpcmmu_exception,
 		.get_egpc_base = gv11b_gr_get_egpc_base,
@@ -412,6 +412,11 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 			.gfxp_wfi_timeout =
 				gv11b_gr_init_commit_gfxp_wfi_timeout,
 		},
+		.intr = {
+			.handle_tpc_mpc_exception =
+					gv11b_gr_intr_handle_tpc_mpc_exception,
+			.handle_tex_exception = NULL,
+		},
 	},
 	.perf = {
 		.get_pmm_per_chiplet_offset =
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 284811e77..5e0ef6974 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -2623,10 +2623,8 @@ static int gk20a_gr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc,
 		}
 	}
 
-	if (g->ops.gr.handle_tpc_mpc_exception != NULL) {
-		tmp_ret = g->ops.gr.handle_tpc_mpc_exception(g,
-					gpc, tpc, post_event);
-		ret = (ret != 0) ? ret : tmp_ret;
+	if (g->ops.gr.intr.handle_tpc_mpc_exception != NULL) {
+		g->ops.gr.intr.handle_tpc_mpc_exception(g, gpc, tpc);
 	}
 
 	return ret;
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index b36115dd1..a15ca5f10 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -452,7 +452,6 @@ static const struct gpu_ops gv100_ops = {
 		.set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode,
 		.is_etpc_addr = gv11b_gr_pri_is_etpc_addr,
 		.egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table,
-		.handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception,
 		.handle_gpc_gpcmmu_exception =
 			gr_gv11b_handle_gpc_gpcmmu_exception,
 		.get_egpc_base = gv11b_gr_get_egpc_base,
@@ -702,6 +701,8 @@ static const struct gpu_ops gv100_ops = {
 				gv11b_gr_init_commit_gfxp_wfi_timeout,
 		},
 		.intr = {
+			.handle_tpc_mpc_exception =
+					gv11b_gr_intr_handle_tpc_mpc_exception,
 			.handle_tex_exception = NULL,
 			.enable_hww_exceptions =
 					gv11b_gr_intr_enable_hww_exceptions,
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index b85f2de36..2ec2a51df 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -2877,39 +2877,6 @@ void gv11b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
 						offset));
 }
 
-int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g,
-		u32 gpc, u32 tpc, bool *post_event)
-{
-	u32 esr;
-	u32 offset = nvgpu_gr_gpc_offset(g, gpc) + nvgpu_gr_tpc_offset(g, tpc);
-	u32 tpc_exception = gk20a_readl(g, gr_gpc0_tpc0_tpccs_tpc_exception_r()
-			+ offset);
-
-	if ((tpc_exception & gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m()) == 0U) {
-		return 0;
-	}
-
-	nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg,
-			"GPC%d TPC%d MPC exception", gpc, tpc);
-
-	esr = gk20a_readl(g, gr_gpc0_tpc0_mpc_hww_esr_r() + offset);
-	nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, "mpc hww esr 0x%08x", esr);
-
-	nvgpu_report_gr_exception(g, ((gpc << 8U) | tpc),
-			GPU_PGRAPH_MPC_EXCEPTION,
-			esr);
-
-	esr = gk20a_readl(g, gr_gpc0_tpc0_mpc_hww_esr_info_r() + offset);
-	nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg,
-			"mpc hww esr info: veid 0x%08x",
-			gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(esr));
-
-	gk20a_writel(g, gr_gpc0_tpc0_mpc_hww_esr_r() + offset,
-		     gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f());
-
-	return 0;
-}
-
 static const u32 _num_ovr_perf_regs = 20;
 static u32 _ovr_perf_regs[20] = { 0, };
 
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index b937f70b2..00dd81314 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -405,7 +405,6 @@ static const struct gpu_ops gv11b_ops = {
 		.set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode,
 		.is_etpc_addr = gv11b_gr_pri_is_etpc_addr,
 		.egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table,
-		.handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception,
 		.handle_gpc_gpcmmu_exception =
 			gr_gv11b_handle_gpc_gpcmmu_exception,
 		.get_egpc_base = gv11b_gr_get_egpc_base,
@@ -661,6 +660,8 @@ static const struct gpu_ops gv11b_ops = {
 				gv11b_gr_init_commit_gfxp_wfi_timeout,
 		},
 		.intr = {
+			.handle_tpc_mpc_exception =
+					gv11b_gr_intr_handle_tpc_mpc_exception,
 			.handle_tex_exception = NULL,
 			.enable_hww_exceptions =
 					gv11b_gr_intr_enable_hww_exceptions,
diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c
index 9555da6e2..e5c3769aa 100644
--- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c
@@ -22,13 +22,45 @@
 
 #include <nvgpu/gk20a.h>
 #include <nvgpu/io.h>
+#include <nvgpu/nvgpu_err.h>
 
 #include <nvgpu/gr/config.h>
+#include <nvgpu/gr/gr.h>
 
 #include "gr_intr_gv11b.h"
 
 #include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
 
+void gv11b_gr_intr_handle_tpc_mpc_exception(struct gk20a *g, u32 gpc, u32 tpc)
+{
+	u32 esr;
+	u32 offset = nvgpu_gr_gpc_offset(g, gpc) + nvgpu_gr_tpc_offset(g, tpc);
+	u32 tpc_exception = gk20a_readl(g, gr_gpc0_tpc0_tpccs_tpc_exception_r()
+			+ offset);
+
+	if ((tpc_exception & gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m()) == 0U) {
+		return;
+	}
+
+	nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg,
+			"GPC%d TPC%d MPC exception", gpc, tpc);
+
+	esr = nvgpu_readl(g, gr_gpc0_tpc0_mpc_hww_esr_r() + offset);
+	nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, "mpc hww esr 0x%08x", esr);
+
+	nvgpu_report_gr_exception(g, ((gpc << 8U) | tpc),
+			GPU_PGRAPH_MPC_EXCEPTION,
+			esr);
+
+	esr = nvgpu_readl(g, gr_gpc0_tpc0_mpc_hww_esr_info_r() + offset);
+	nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg,
+			"mpc hww esr info: veid 0x%08x",
+			gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(esr));
+
+	nvgpu_writel(g, gr_gpc0_tpc0_mpc_hww_esr_r() + offset,
+		     gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f());
+}
+
 void gv11b_gr_intr_enable_hww_exceptions(struct gk20a *g)
 {
 	/* enable exceptions */
diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h
index e13837dfc..5b7c4cf3c 100644
--- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h
+++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h
@@ -28,6 +28,7 @@
 struct gk20a;
 struct nvgpu_gr_config;
 
+void gv11b_gr_intr_handle_tpc_mpc_exception(struct gk20a *g, u32 gpc, u32 tpc);
 void gv11b_gr_intr_enable_hww_exceptions(struct gk20a *g);
 void gv11b_gr_intr_enable_exceptions(struct gk20a *g,
 				     struct nvgpu_gr_config *gr_config,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 82b244003..b98c4dae7 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -370,8 +370,6 @@ struct gpu_ops {
 		int (*handle_gcc_exception)(struct gk20a *g, u32 gpc, u32 tpc,
 				bool *post_event, struct channel_gk20a *fault_ch,
 				u32 *hww_global_esr);
-		int (*handle_tpc_mpc_exception)(struct gk20a *g,
-					u32 gpc, u32 tpc, bool *post_event);
 		int (*handle_gpc_gpccs_exception)(struct gk20a *g, u32 gpc,
 						u32 gpc_exception);
 		int (*handle_gpc_gpcmmu_exception)(struct gk20a *g, u32 gpc,
@@ -769,6 +767,8 @@ struct gpu_ops {
 		} init;
 
 		struct {
+			void (*handle_tpc_mpc_exception)(struct gk20a *g,
+							u32 gpc, u32 tpc);
 			void (*handle_tex_exception)(struct gk20a *g,
 						     u32 gpc, u32 tpc);
 			void (*enable_hww_exceptions)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c
index c26c6bea7..1f38fbded 100644
--- a/drivers/gpu/nvgpu/tu104/hal_tu104.c
+++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c
@@ -474,7 +474,6 @@ static const struct gpu_ops tu104_ops = {
 		.set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode,
 		.is_etpc_addr = gv11b_gr_pri_is_etpc_addr,
 		.egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table,
-		.handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception,
 		.handle_gpc_gpcmmu_exception =
 			gr_gv11b_handle_gpc_gpcmmu_exception,
 		.get_egpc_base = gv11b_gr_get_egpc_base,
@@ -735,6 +734,8 @@ static const struct gpu_ops tu104_ops = {
 				gv11b_gr_init_commit_gfxp_wfi_timeout,
 		},
 		.intr = {
+			.handle_tpc_mpc_exception =
+					gv11b_gr_intr_handle_tpc_mpc_exception,
 			.handle_tex_exception = NULL,
 			.enable_hww_exceptions =
 					gv11b_gr_intr_enable_hww_exceptions,