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gpu: nvgpu: gr_gk20a header cleanup

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Move GK20A_TIMEOUT_FPGA definition from gr_gk20a.h to
defaults.h as NVGPU_DEFAULT_FPGA_TIMEOUT_MS

Remove unused function definitions in gr_gk20a.h

JIRA NVGPU-3132

Change-Id: I29b973f04fb5a1725177e18903a8494481c43d95
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098995
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-04-16 14:40:55 -07:00
committed by mobile promotions
parent 7a440fb721
commit 9b12f99534
3 changed files with 4 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
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@@ -29,8 +29,6 @@
#include "mm_gk20a.h" #include "mm_gk20a.h"
#define GK20A_TIMEOUT_FPGA 100000U /* 100 sec */
struct nvgpu_gr_ctx; struct nvgpu_gr_ctx;
struct channel_gk20a; struct channel_gk20a;
struct nvgpu_warpstate; struct nvgpu_warpstate;
@@ -42,6 +40,7 @@ struct nvgpu_gr_hwpm_map;
struct nvgpu_gr_isr_data; struct nvgpu_gr_isr_data;
struct nvgpu_gr_ctx_desc; struct nvgpu_gr_ctx_desc;
struct dbg_session_gk20a; struct dbg_session_gk20a;
struct nvgpu_dbg_reg_op;
enum ctxsw_addr_type; enum ctxsw_addr_type;
@@ -148,20 +147,12 @@ struct nvgpu_warpstate {
u64 paused_warps[2]; u64 paused_warps[2];
}; };
struct gpu_ops;
int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
struct channel_gk20a *c,
struct nvgpu_gr_ctx *gr_ctx);
int gk20a_gr_isr(struct gk20a *g); int gk20a_gr_isr(struct gk20a *g);
void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config);
/* sm */ /* sm */
bool gk20a_gr_sm_debugger_attached(struct gk20a *g); bool gk20a_gr_sm_debugger_attached(struct gk20a *g);
u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g); u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g);
struct nvgpu_dbg_reg_op;
int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops, struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
u32 num_ctx_wr_ops, u32 num_ctx_rd_ops, u32 num_ctx_wr_ops, u32 num_ctx_rd_ops,
@@ -257,7 +248,6 @@ void gk20a_gr_init_ovr_sm_dsm_perf(void);
void gk20a_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs, void gk20a_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs,
u32 **ovr_perf_regs); u32 **ovr_perf_regs);
int gk20a_init_sw_bundle(struct gk20a *g);
int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr, int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr,
enum ctxsw_addr_type *addr_type, enum ctxsw_addr_type *addr_type,
u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num,

2
drivers/gpu/nvgpu/include/nvgpu/defaults.h
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@@ -30,4 +30,6 @@
#define NVGPU_DEFAULT_RAILGATE_IDLE_TIMEOUT 500 #define NVGPU_DEFAULT_RAILGATE_IDLE_TIMEOUT 500
#define NVGPU_DEFAULT_FPGA_TIMEOUT_MS 100000U /* 100 sec */
#endif #endif

2
drivers/gpu/nvgpu/os/linux/driver_common.c
View File

@@ -118,7 +118,7 @@ static void nvgpu_init_timeout(struct gk20a *g)
if (nvgpu_platform_is_silicon(g)) { if (nvgpu_platform_is_silicon(g)) {
g->poll_timeout_default = NVGPU_DEFAULT_POLL_TIMEOUT_MS; g->poll_timeout_default = NVGPU_DEFAULT_POLL_TIMEOUT_MS;
} else if (nvgpu_platform_is_fpga(g)) { } else if (nvgpu_platform_is_fpga(g)) {
g->poll_timeout_default = GK20A_TIMEOUT_FPGA; g->poll_timeout_default = NVGPU_DEFAULT_FPGA_TIMEOUT_MS;
} else { } else {
g->poll_timeout_default = (u32)ULONG_MAX; g->poll_timeout_default = (u32)ULONG_MAX;
} }