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gpu: nvgpu: move .exec_regops to only execute regops

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HAL .exec_regops used to first validate regops then execute it, now
moving it to only execute the regops.

- It helps B0CC on HV. On server side it does not track profiler object,
but regops validation uses the profiler, so moving validation to client
side.
- The change also remove ctx_buffer_offset checking in
validate_reg_op_offset. The offset already checked again whitelists
which have be verified when update whitelist. Also vgpu does not have
information of ctx and golden image.
- Added function nvgpu_regops_exec to cover both regops validation and
execution.

Jira GVSCI-10351

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I434e027290e263a8a64a25a55500f7294038c9c4
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2534252
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Richard Zhao
2021-05-24 18:21:57 -07:00
committed by mobile promotions
parent 08cd42093d
commit 9b66fca165
7 changed files with 58 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

72
drivers/gpu/nvgpu/common/regops/regops.c
View File

@@ -1,7 +1,7 @@
/*
* Tegra GK20A GPU Debugger Driver Register Ops
*
* Copyright (c) 2013-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2013-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -88,29 +88,19 @@ static bool validate_reg_ops(struct gk20a *g,
int exec_regops_gk20a(struct gk20a *g,
struct nvgpu_tsg *tsg,
struct nvgpu_profiler_object *prof,
struct nvgpu_dbg_reg_op *ops,
u32 num_ops,
u32 ctx_wr_count,
u32 ctx_rd_count,
u32 *flags)
{
int err = 0;
unsigned int i;
u32 data32_lo = 0, data32_hi = 0;
u32 ctx_rd_count = 0, ctx_wr_count = 0;
bool skip_read_lo, skip_read_hi;
bool ok;
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, " ");
ok = validate_reg_ops(g, prof, &ctx_rd_count, &ctx_wr_count,
ops, num_ops, tsg != NULL, flags);
if (!ok) {
nvgpu_err(g, "invalid op(s)");
err = -EINVAL;
/* each op has its own err/status */
goto clean_up;
}
/* be sure that ctx info is in place if there are ctx ops */
if ((ctx_wr_count | ctx_rd_count) != 0U) {
if (!gr_context_info_available(g)) {
@@ -226,6 +216,34 @@ int exec_regops_gk20a(struct gk20a *g,
}
int nvgpu_regops_exec(struct gk20a *g,
struct nvgpu_tsg *tsg,
struct nvgpu_profiler_object *prof,
struct nvgpu_dbg_reg_op *ops,
u32 num_ops,
u32 *flags)
{
u32 ctx_rd_count = 0, ctx_wr_count = 0;
int err = 0;
bool ok;
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, " ");
ok = validate_reg_ops(g, prof, &ctx_rd_count, &ctx_wr_count,
ops, num_ops, tsg != NULL, flags);
if (!ok) {
nvgpu_err(g, "invalid op(s)");
return -EINVAL;
}
err = g->ops.regops.exec_regops(g, tsg, ops, num_ops, ctx_wr_count,
ctx_rd_count, flags);
if (err != 0) {
nvgpu_warn(g, "failed to perform regops, err=%d", err);
}
return err;
}
static int validate_reg_op_info(struct nvgpu_dbg_reg_op *op)
{
@@ -360,8 +378,7 @@ static int validate_reg_op_offset(struct gk20a *g,
struct nvgpu_dbg_reg_op *op,
bool valid_ctx)
{
int err;
u32 buf_offset_lo, buf_offset_addr, num_offsets, offset;
u32 offset;
bool valid = false;
offset = op->offset;
@@ -378,31 +395,6 @@ static int validate_reg_op_offset(struct gk20a *g,
valid = check_whitelists(g, op, offset + 4U, valid_ctx);
}
if (valid && (op->type != REGOP(TYPE_GLOBAL))) {
err = g->ops.gr.get_ctx_buffer_offsets(g,
op->offset,
1,
&buf_offset_lo,
&buf_offset_addr,
&num_offsets);
if (err != 0) {
err = gr_gk20a_get_pm_ctx_buffer_offsets(g,
op->offset,
1,
&buf_offset_lo,
&buf_offset_addr,
&num_offsets);
if (err != 0) {
op->status |= REGOP(STATUS_INVALID_OFFSET);
return -EINVAL;
}
}
if (num_offsets == 0U) {
op->status |= REGOP(STATUS_INVALID_OFFSET);
return -EINVAL;
}
}
if (!valid) {
nvgpu_err(g, "invalid regop offset: 0x%x", offset);
op->status |= REGOP(STATUS_INVALID_OFFSET);