gpu: nvgpu: Add support for loading ctxsw encrypted binaries

Add checks to load encrypted CTXSW binaries for T234,
when executing in silicon; else load the non encrypted
binaries.

Jira NVGPU-9303

Change-Id: Icf55ed76b1a7340006b00d1c24472d26462a880c
Signed-off-by: mpoojary <mpoojary@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2819642
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Dinesh Kamalakannan <dineshka@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>

drivers/gpu/nvgpu/common/acr/acr_blob_construct.c

@@ -27,6 +27,7 @@
 #include <nvgpu/bug.h>
 #include <nvgpu/gr/gr_falcon.h>
 #include <nvgpu/gr/gr_utils.h>
+#include <nvgpu/soc.h>
 
 #include "nvgpu_acr_interface.h"
 #include "acr_blob_construct.h"
@@ -190,9 +191,15 @@ int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
 					GM20B_FECS_UCODE_SIG,
 					g->acr->fw_load_flag);
 			} else {
-				fecs_sig = nvgpu_request_firmware(g,
+				if (nvgpu_platform_is_simulation(g)) {
-					GA10B_FECS_UCODE_PKC_SIG,
+					fecs_sig = nvgpu_request_firmware(g,
-					g->acr->fw_load_flag);
+						GA10B_FECS_UCODE_PKC_SIG,
+						g->acr->fw_load_flag);
+				} else {
+					fecs_sig = nvgpu_request_firmware(g,
+						GA10B_FECS_UCODE_ENCRYPT_PKC_SIG,
+						g->acr->fw_load_flag);
+				}
 			}
 			break;
 #ifdef CONFIG_NVGPU_DGPU
@@ -333,9 +340,15 @@ int nvgpu_acr_lsf_gpccs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
 					T18x_GPCCS_UCODE_SIG,
 					g->acr->fw_load_flag);
 			} else {
-				gpccs_sig = nvgpu_request_firmware(g,
+				if (nvgpu_platform_is_simulation(g)) {
-					GA10B_GPCCS_UCODE_PKC_SIG,
+					gpccs_sig = nvgpu_request_firmware(g,
-					g->acr->fw_load_flag);
+						GA10B_GPCCS_UCODE_PKC_SIG,
+						g->acr->fw_load_flag);
+				} else {
+					gpccs_sig = nvgpu_request_firmware(g,
+						GA10B_GPCCS_UCODE_ENCRYPT_PKC_SIG,
+						g->acr->fw_load_flag);
+				}
 			}
 			break;
 #ifdef CONFIG_NVGPU_DGPU

drivers/gpu/nvgpu/common/acr/acr_priv.h

@@ -92,6 +92,9 @@ struct wpr_carveout_info;
 #define GA10B_FECS_UCODE_PKC_SIG "fecs_pkc_sig.bin"
 #define GA10B_GPCCS_UCODE_PKC_SIG "gpccs_pkc_sig.bin"
 
+#define GA10B_FECS_UCODE_ENCRYPT_PKC_SIG "fecs_pkc_sig_encrypt.bin"
+#define GA10B_GPCCS_UCODE_ENCRYPT_PKC_SIG "gpccs_pkc_sig_encrypt.bin"
+
 #define TU104_FECS_UCODE_SIG "tu104/fecs_sig.bin"
 #define TU104_GPCCS_UCODE_SIG "tu104/gpccs_sig.bin"
 

drivers/gpu/nvgpu/common/gr/gr_falcon.c

@@ -43,9 +43,6 @@
 
 #include "gr_falcon_priv.h"
 
-#define NVGPU_FECS_UCODE_IMAGE	"fecs.bin"
-#define NVGPU_GPCCS_UCODE_IMAGE	"gpccs.bin"
-
 struct nvgpu_gr_falcon *nvgpu_gr_falcon_init_support(struct gk20a *g)
 {
 	struct nvgpu_gr_falcon *falcon;
@@ -311,11 +308,13 @@ int nvgpu_gr_falcon_init_ctxsw_ucode(struct gk20a *g,
 	u32 *gpccs_boot_image;
 	struct nvgpu_ctxsw_ucode_info *ucode_info = &falcon->ctxsw_ucode_info;
 	u32 ucode_size;
+	const char *fw_name = NULL;
 	int err = 0;
 
 	nvgpu_log(g, gpu_dbg_gr, "Requst and copy FECS/GPCCS firmwares");
 
-	fecs_fw = nvgpu_request_firmware(g, NVGPU_FECS_UCODE_IMAGE, 0);
+	g->ops.gr.falcon.get_fw_name(g, &fw_name, FALCON_ID_FECS);
+	fecs_fw = nvgpu_request_firmware(g, fw_name, 0);
 	if (fecs_fw == NULL) {
 		nvgpu_err(g, "failed to load fecs ucode!!");
 		return -ENOENT;
@@ -325,7 +324,8 @@ int nvgpu_gr_falcon_init_ctxsw_ucode(struct gk20a *g,
 	fecs_boot_image = (void *)(fecs_fw->data +
 				sizeof(struct nvgpu_ctxsw_bootloader_desc));
 
-	gpccs_fw = nvgpu_request_firmware(g, NVGPU_GPCCS_UCODE_IMAGE, 0);
+	g->ops.gr.falcon.get_fw_name(g, &fw_name, FALCON_ID_GPCCS);
+	gpccs_fw = nvgpu_request_firmware(g, fw_name, 0);
 	if (gpccs_fw == NULL) {
 		nvgpu_release_firmware(g, fecs_fw);
 		nvgpu_err(g, "failed to load gpccs ucode!!");

drivers/gpu/nvgpu/common/netlist/netlist.c

@@ -45,7 +45,7 @@
  * to get complete path like gm204/NETC_img.bin
  */
 
-#define MAX_NETLIST_NAME (sizeof("GAxxx/") + sizeof("NET?_img.bin"))
+#define MAX_NETLIST_NAME (sizeof("GAxxx/") + sizeof("NET?_img_xxxxx_encrypted.bin"))
 
 struct netlist_av *nvgpu_netlist_alloc_av_list(struct gk20a *g,
 						struct netlist_av_list *avl)

drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga10b.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -27,6 +27,7 @@
 
 struct gk20a;
 
+void ga10b_gr_falcon_get_fw_name(struct gk20a *g, const char **ucode_name, u32 falcon_id);
 u32 ga10b_gr_falcon_get_fecs_ctxsw_mailbox_size(void);
 void ga10b_gr_falcon_fecs_ctxsw_clear_mailbox(struct gk20a *g,
 						u32 reg_index, u32 clear_val);

drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_ga10b_fusa.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -25,11 +25,47 @@
 #include <nvgpu/static_analysis.h>
 #include <nvgpu/gr/gr_utils.h>
 #include <nvgpu/gr/config.h>
+#include <nvgpu/falcon.h>
+#include <nvgpu/soc.h>
 
 #include "gr_falcon_ga10b.h"
 
 #include <nvgpu/hw/ga10b/hw_gr_ga10b.h>
 
+#define NVGPU_FECS_UCODE_IMAGE	                "fecs.bin"
+#define NVGPU_GPCCS_UCODE_IMAGE	                "gpccs.bin"
+#define NVGPU_FECS_ENCRYPT_DBG_UCODE_IMAGE	    "fecs_encrypt_dbg.bin"
+#define NVGPU_FECS_ENCRYPT_PROD_UCODE_IMAGE	    "fecs_encrypt_prod.bin"
+#define NVGPU_GPCCS_ENCRYPT_DBG_UCODE_IMAGE	    "gpccs_encrypt_dbg.bin"
+#define NVGPU_GPCCS_ENCRYPT_PROD_UCODE_IMAGE	"gpccs_encrypt_prod.bin"
+
+void ga10b_gr_falcon_get_fw_name(struct gk20a *g, const char **ucode_name, u32 falcon_id)
+{
+	nvgpu_log_fn(g, " ");
+
+	if (falcon_id == FALCON_ID_FECS) {
+		if (nvgpu_platform_is_simulation(g)) {
+			*ucode_name = NVGPU_FECS_UCODE_IMAGE;
+		} else {
+			if (g->ops.pmu.is_debug_mode_enabled(g)) {
+				*ucode_name = NVGPU_FECS_ENCRYPT_DBG_UCODE_IMAGE;
+			} else {
+				*ucode_name = NVGPU_FECS_ENCRYPT_PROD_UCODE_IMAGE;
+			}
+		}
+	} else if (falcon_id == FALCON_ID_GPCCS) {
+		if (nvgpu_platform_is_simulation(g)) {
+			*ucode_name = NVGPU_GPCCS_UCODE_IMAGE;
+		} else {
+			if (g->ops.pmu.is_debug_mode_enabled(g)) {
+				*ucode_name = NVGPU_GPCCS_ENCRYPT_DBG_UCODE_IMAGE;
+			} else {
+				*ucode_name = NVGPU_GPCCS_ENCRYPT_PROD_UCODE_IMAGE;
+			}
+		}
+	}
+}
+
 u32 ga10b_gr_falcon_get_fecs_ctxsw_mailbox_size(void)
 {
 	return gr_fecs_ctxsw_mailbox__size_1_v();

drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.h

@@ -30,6 +30,7 @@ struct nvgpu_fecs_method_op;
 struct nvgpu_fecs_host_intr_status;
 struct nvgpu_gr_falcon_query_sizes;
 
+void gm20b_gr_falcon_get_fw_name(struct gk20a *g, const char **ucode_name, u32 falcon_id);
 void gm20b_gr_falcon_fecs_ctxsw_clear_mailbox(struct gk20a *g,
 					u32 reg_index, u32 clear_val);
 u32 gm20b_gr_falcon_read_mailbox_fecs_ctxsw(struct gk20a *g, u32 reg_index);

drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c

@@ -52,6 +52,21 @@
 #define CTXSW_INTR0 BIT32(0)
 #define CTXSW_INTR1 BIT32(1)
 
+#define NVGPU_FECS_UCODE_IMAGE	"fecs.bin"
+#define NVGPU_GPCCS_UCODE_IMAGE	"gpccs.bin"
+
+void gm20b_gr_falcon_get_fw_name(struct gk20a *g, const char **ucode_name, u32 falcon_id)
+{
+	nvgpu_log_fn(g, " ");
+
+	if (falcon_id == FALCON_ID_FECS) {
+		*ucode_name = NVGPU_FECS_UCODE_IMAGE;
+	} else if (falcon_id == FALCON_ID_GPCCS) {
+		*ucode_name = NVGPU_GPCCS_UCODE_IMAGE;
+	}
+}
+
+
 void gm20b_gr_falcon_fecs_ctxsw_clear_mailbox(struct gk20a *g,
 			u32 reg_index, u32 clear_val)
 {

drivers/gpu/nvgpu/hal/init/hal_ga100.c

@@ -796,6 +796,7 @@ static const struct gops_gr_falcon ga100_ops_gr_falcon = {
 #ifdef CONFIG_NVGPU_SIM
 	.configure_fmodel = gm20b_gr_falcon_configure_fmodel,
 #endif
+	.get_fw_name = gm20b_gr_falcon_get_fw_name,
 };
 
 static const struct gops_gr ga100_ops_gr = {

drivers/gpu/nvgpu/hal/init/hal_ga10b.c

@@ -800,6 +800,7 @@ static const struct gops_gr_falcon ga10b_ops_gr_falcon = {
 #ifdef CONFIG_NVGPU_SIM
 	.configure_fmodel = gm20b_gr_falcon_configure_fmodel,
 #endif
+	.get_fw_name = ga10b_gr_falcon_get_fw_name,
 };
 
 static const struct gops_gr ga10b_ops_gr = {

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -459,6 +459,7 @@ static const struct gops_gr_falcon gm20b_ops_gr_falcon = {
 #ifdef CONFIG_NVGPU_SIM
 	.configure_fmodel = gm20b_gr_falcon_configure_fmodel,
 #endif
+	.get_fw_name = gm20b_gr_falcon_get_fw_name,
 };
 
 static const struct gops_gr gm20b_ops_gr = {

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -671,6 +671,7 @@ static const struct gops_gr_falcon gv11b_ops_gr_falcon = {
 #ifdef CONFIG_NVGPU_SIM
 	.configure_fmodel = gm20b_gr_falcon_configure_fmodel,
 #endif
+	.get_fw_name = gm20b_gr_falcon_get_fw_name,
 };
 
 static const struct gops_gr gv11b_ops_gr = {

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -706,6 +706,7 @@ static const struct gops_gr_falcon tu104_ops_gr_falcon = {
 #ifdef CONFIG_NVGPU_SIM
 	.configure_fmodel = gm20b_gr_falcon_configure_fmodel,
 #endif
+	.get_fw_name = gm20b_gr_falcon_get_fw_name,
 };
 
 static const struct gops_gr tu104_ops_gr = {

drivers/gpu/nvgpu/hal/netlist/netlist_ga10b.h

@@ -30,6 +30,20 @@ struct gk20a;
 /* NVGPU_NETLIST_IMAGE_C is FNL for ga10b */
 #define GA10B_NETLIST_IMAGE_FW_NAME NVGPU_NETLIST_IMAGE_C
 
+#define NVGPU_NETLIST_DBG_IMAGE_A	"NETA_img_debug_encrypted.bin"
+#define NVGPU_NETLIST_DBG_IMAGE_B	"NETB_img_debug_encrypted.bin"
+#define NVGPU_NETLIST_DBG_IMAGE_C	"NETC_img_debug_encrypted.bin"
+#define NVGPU_NETLIST_DBG_IMAGE_D	"NETD_img_debug_encrypted.bin"
+
+#define NVGPU_NETLIST_PROD_IMAGE_A	"NETA_img_prod_encrypted.bin"
+#define NVGPU_NETLIST_PROD_IMAGE_B	"NETB_img_prod_encrypted.bin"
+#define NVGPU_NETLIST_PROD_IMAGE_C	"NETC_img_prod_encrypted.bin"
+#define NVGPU_NETLIST_PROD_IMAGE_D	"NETD_img_prod_encrypted.bin"
+
+/* NVGPU_NETLIST_IMAGE_C is FNL for ga10b */
+#define GA10B_NETLIST_DBG_IMAGE_FW_NAME NVGPU_NETLIST_DBG_IMAGE_C
+#define GA10B_NETLIST_PROD_IMAGE_FW_NAME NVGPU_NETLIST_PROD_IMAGE_C
+
 int ga10b_netlist_get_name(struct gk20a *g, int index, char *name);
 bool ga10b_netlist_is_firmware_defined(void);
 

drivers/gpu/nvgpu/hal/netlist/netlist_ga10b_fusa.c

@@ -22,10 +22,75 @@
 
 #include <nvgpu/gk20a.h>
 #include <nvgpu/string.h>
+#include <nvgpu/soc.h>
 
 #include "netlist_ga10b.h"
 
-int ga10b_netlist_get_name(struct gk20a *g, int index, char *name)
+static int ga10b_netlist_silicon_get_name(struct gk20a *g, int index, char *name)
+{
+	int ret = 0;
+
+	(void)g;
+
+	switch (index) {
+#if defined(GA10B_NETLIST_DBG_IMAGE_FW_NAME) || defined(GA10B_NETLIST_PROD_IMAGE_FW_NAME)
+	case NETLIST_FINAL:
+		if (g->ops.pmu.is_debug_mode_enabled(g)) {
+			(void) strcpy(name, GA10B_NETLIST_DBG_IMAGE_FW_NAME);
+		} else {
+			(void) strcpy(name, GA10B_NETLIST_PROD_IMAGE_FW_NAME);
+		}
+		break;
+#else
+#ifdef CONFIG_NVGPU_NON_FUSA
+#if defined(NVGPU_NETLIST_DBG_IMAGE_A) || defined(NVGPU_NETLIST_PROD_IMAGE_A)
+	case NETLIST_SLOT_A:
+		if (g->ops.pmu.is_debug_mode_enabled(g)) {
+			(void) strcpy(name, NVGPU_NETLIST_DBG_IMAGE_A);
+		} else {
+			(void) strcpy(name, NVGPU_NETLIST_PROD_IMAGE_A);
+		}
+		break;
+#endif
+#if defined(NVGPU_NETLIST_DBG_IMAGE_B) || defined(NVGPU_NETLIST_PROD_IMAGE_B)
+	case NETLIST_SLOT_B:
+		if (g->ops.pmu.is_debug_mode_enabled(g)) {
+			(void) strcpy(name, NVGPU_NETLIST_DBG_IMAGE_B);
+		} else {
+			(void) strcpy(name, NVGPU_NETLIST_PROD_IMAGE_B);
+		}
+		break;
+#endif
+#if defined(NVGPU_NETLIST_DBG_IMAGE_C) || defined(NVGPU_NETLIST_PROD_IMAGE_C)
+	case NETLIST_SLOT_C:
+		if (g->ops.pmu.is_debug_mode_enabled(g)) {
+			(void) strcpy(name, NVGPU_NETLIST_DBG_IMAGE_C);
+		} else {
+			(void) strcpy(name, NVGPU_NETLIST_PROD_IMAGE_C);
+		}
+		break;
+#endif
+#if defined(NVGPU_NETLIST_DBG_IMAGE_D) || defined(NVGPU_NETLIST_PROD_IMAGE_D)
+	case NETLIST_SLOT_D:
+		if (g->ops.pmu.is_debug_mode_enabled(g)) {
+			(void) strcpy(name, NVGPU_NETLIST_DBG_IMAGE_D);
+		} else {
+			(void) strcpy(name, NVGPU_NETLIST_PROD_IMAGE_D);
+		}
+		break;
+#endif
+#endif
+#endif
+	default:
+		ret = -ENOENT;
+		break;
+
+	}
+
+	return ret;
+}
+
+static int ga10b_netlist_sim_get_name(struct gk20a *g, int index, char *name)
 {
 	int ret = 0;
 
@@ -69,9 +134,22 @@ int ga10b_netlist_get_name(struct gk20a *g, int index, char *name)
 	return ret;
 }
 
+int ga10b_netlist_get_name(struct gk20a *g, int index, char *name)
+{
+	int ret = 0;
+
+	if (nvgpu_platform_is_simulation(g)) {
+		ret = ga10b_netlist_sim_get_name(g, index, name);
+	} else {
+		ret = ga10b_netlist_silicon_get_name(g, index, name);
+	}
+
+	return ret;
+}
+
 bool ga10b_netlist_is_firmware_defined(void)
 {
-#ifdef GA10B_NETLIST_IMAGE_FW_NAME
+#if defined(GA10B_NETLIST_DBG_IMAGE_FW_NAME) || defined(GA10B_NETLIST_PROD_IMAGE_FW_NAME) || defined(GA10B_NETLIST_IMAGE_FW_NAME)
 	return true;
 #else
 	return false;

drivers/gpu/nvgpu/include/nvgpu/gops/gr.h

@@ -416,6 +416,7 @@ struct gops_gr_falcon {
 #ifdef CONFIG_NVGPU_SIM
 	void (*configure_fmodel)(struct gk20a *g);
 #endif
+	void (*get_fw_name)(struct gk20a *g, const char **ucode_name, u32 falcon_id);
 	/** @endcond */
 
 };