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gpu: nvgpu: prealloc priv cmdbuf metadata

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Move preallocation of priv cmdbuf metadata structs to the priv cmdbuf
level and do it always, not only on deterministic channels. This makes
job tracking simpler and loosens dependencies from jobs to cmdbuf
internals. The underlying dma memory for the cmdbuf data has always been
preallocated.

Rename the priv cmdbuf functions to have a consistent prefix.

Refactor the channel sync wait and incr ops to free any priv cmdbufs
they allocate. They have been depending on the caller to free their
resources even on error conditions, requiring the caller to know how
they work.

The error paths that could occur after a priv cmdbuf has been allocated
have likely been wrong for a long time. Usually the cmdbuf queue allows
allocating only from one end and freeing from only the other end, as
that's natural with the hardware job queue. However, in error conditions
the just recently allocated entries need to be put back. Improve the
interface for this.

[not part of the cherry-pick:] Delete the error prints about not enough
priv cmd buffer space. That is not an error. When obeying the
user-provided job sizes more strictly, momentarily running out of job
tracking resources is possible when the job cleanup thread does not
catch up quickly enough. In such a case the number of inflight jobs on
the hardware could be less than the maximum, but the inflight job count
that nvgpu sees via the consumed resources could reach the maximum.
Also remove the wrong translation to -EINVAL from err from one call to
nvgpu_priv_cmdbuf_alloc() - the -EAGAIN from the failed allocation is
important.

[not part of the cherry-pick: a bunch of MISRA mitigations.]

Jira NVGPU-4548

Change-Id: I09d02bd44d50a5451500d09605f906d74009a8a4
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329657
(cherry picked from commit 25412412f31436688c6b45684886f7552075da83)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2332506
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Konsta Hölttä
2020-04-06 13:44:54 +03:00
committed by Alex Waterman
parent bc4f74d854
commit 9bee2fe660
11 changed files with 190 additions and 192 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c
View File

@@ -67,7 +67,7 @@ static void channel_sync_syncpt_gen_wait_cmd(struct nvgpu_channel *c,
}
static int channel_sync_syncpt_wait_raw(struct nvgpu_channel_sync_syncpt *s,
u32 id, u32 thresh, struct priv_cmd_entry *wait_cmd)
u32 id, u32 thresh, struct priv_cmd_entry **wait_cmd)
{
struct nvgpu_channel *c = s->c;
int err = 0;
@@ -77,22 +77,21 @@ static int channel_sync_syncpt_wait_raw(struct nvgpu_channel_sync_syncpt *s,
return -EINVAL;
}
err = nvgpu_channel_alloc_priv_cmdbuf(c,
err = nvgpu_priv_cmdbuf_alloc(c,
c->g->ops.sync.syncpt.get_wait_cmd_size(),
wait_cmd);
if (err != 0) {
nvgpu_err(c->g, "not enough priv cmd buffer space");
return err;
}
channel_sync_syncpt_gen_wait_cmd(c, id, thresh,
wait_cmd, wait_cmd_size);
*wait_cmd, wait_cmd_size);
return 0;
}
static int channel_sync_syncpt_wait_fd(struct nvgpu_channel_sync *s, int fd,
struct priv_cmd_entry *wait_cmd, u32 max_wait_cmds)
struct priv_cmd_entry **wait_cmd, u32 max_wait_cmds)
{
struct nvgpu_os_fence os_fence = {0};
struct nvgpu_os_fence_syncpt os_fence_syncpt = {0};
@@ -136,11 +135,9 @@ static int channel_sync_syncpt_wait_fd(struct nvgpu_channel_sync *s, int fd,
}
wait_cmd_size = c->g->ops.sync.syncpt.get_wait_cmd_size();
err = nvgpu_channel_alloc_priv_cmdbuf(c,
err = nvgpu_priv_cmdbuf_alloc(c,
wait_cmd_size * num_fences, wait_cmd);
if (err != 0) {
nvgpu_err(c->g, "not enough priv cmd buffer space");
err = -EINVAL;
goto cleanup;
}
@@ -148,7 +145,7 @@ static int channel_sync_syncpt_wait_fd(struct nvgpu_channel_sync *s, int fd,
nvgpu_os_fence_syncpt_extract_nth_syncpt(
&os_fence_syncpt, i, &syncpt_id, &syncpt_thresh);
channel_sync_syncpt_gen_wait_cmd(c, syncpt_id,
syncpt_thresh, wait_cmd, wait_cmd_size);
syncpt_thresh, *wait_cmd, wait_cmd_size);
}
cleanup:
@@ -169,7 +166,7 @@ static void channel_sync_syncpt_update(void *priv, int nr_completed)
static int channel_sync_syncpt_incr_common(struct nvgpu_channel_sync *s,
bool wfi_cmd,
bool register_irq,
struct priv_cmd_entry *incr_cmd,
struct priv_cmd_entry **incr_cmd,
struct nvgpu_fence_type *fence,
bool need_sync_fence)
{
@@ -180,7 +177,7 @@ static int channel_sync_syncpt_incr_common(struct nvgpu_channel_sync *s,
struct nvgpu_channel *c = sp->c;
struct nvgpu_os_fence os_fence = {0};
err = nvgpu_channel_alloc_priv_cmdbuf(c,
err = nvgpu_priv_cmdbuf_alloc(c,
c->g->ops.sync.syncpt.get_incr_cmd_size(wfi_cmd),
incr_cmd);
if (err != 0) {
@@ -189,7 +186,7 @@ static int channel_sync_syncpt_incr_common(struct nvgpu_channel_sync *s,
nvgpu_log(c->g, gpu_dbg_info, "sp->id %d gpu va %llx",
sp->id, sp->syncpt_buf.gpu_va);
c->g->ops.sync.syncpt.add_incr_cmd(c->g, incr_cmd,
c->g->ops.sync.syncpt.add_incr_cmd(c->g, *incr_cmd,
sp->id, sp->syncpt_buf.gpu_va, wfi_cmd);
thresh = nvgpu_nvhost_syncpt_incr_max_ext(sp->nvhost, sp->id,
@@ -244,12 +241,12 @@ static int channel_sync_syncpt_incr_common(struct nvgpu_channel_sync *s,
return 0;
clean_up_priv_cmd:
nvgpu_channel_update_priv_cmd_q_and_free_entry(c, incr_cmd);
nvgpu_priv_cmdbuf_rollback(c, *incr_cmd);
return err;
}
static int channel_sync_syncpt_incr(struct nvgpu_channel_sync *s,
struct priv_cmd_entry *entry,
struct priv_cmd_entry **entry,
struct nvgpu_fence_type *fence,
bool need_sync_fence,
bool register_irq)
@@ -263,7 +260,7 @@ static int channel_sync_syncpt_incr(struct nvgpu_channel_sync *s,
}
static int channel_sync_syncpt_incr_user(struct nvgpu_channel_sync *s,
struct priv_cmd_entry *entry,
struct priv_cmd_entry **entry,
struct nvgpu_fence_type *fence,
bool wfi,
bool need_sync_fence,
@@ -278,7 +275,7 @@ static int channel_sync_syncpt_incr_user(struct nvgpu_channel_sync *s,
}
int nvgpu_channel_sync_wait_syncpt(struct nvgpu_channel_sync_syncpt *s,
u32 id, u32 thresh, struct priv_cmd_entry *entry)
u32 id, u32 thresh, struct priv_cmd_entry **entry)
{
return channel_sync_syncpt_wait_raw(s, id, thresh, entry);
}