diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index 476afdafd..6b249a676 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -231,6 +231,10 @@ nvgpu-y += \
 	hal/fb/fb_gv11b.o \
 	hal/fb/fb_gv100.o \
 	hal/fb/fb_tu104.o \
+	hal/fb/intr/fb_intr_gv100.o \
+	hal/fb/intr/fb_intr_gv11b.o \
+	hal/fb/intr/fb_intr_tu104.o \
+	hal/fb/intr/fb_intr_ecc_gv11b.o \
 	hal/fuse/fuse_gm20b.o \
 	hal/fuse/fuse_gp10b.o \
 	hal/fuse/fuse_gp106.o \
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources
index d44880915..bbe94dd1f 100644
--- a/drivers/gpu/nvgpu/Makefile.sources
+++ b/drivers/gpu/nvgpu/Makefile.sources
@@ -361,6 +361,10 @@ srcs += common/sim.c \
 	hal/fb/fb_gv100.c \
 	hal/fb/fb_gv11b.c \
 	hal/fb/fb_tu104.c	\
+	hal/fb/intr/fb_intr_gv100.c	\
+	hal/fb/intr/fb_intr_gv11b.c	\
+	hal/fb/intr/fb_intr_tu104.c	\
+	hal/fb/intr/fb_intr_ecc_gv11b.c	\
 	hal/fuse/fuse_gm20b.c \
 	hal/fuse/fuse_gp10b.c \
 	hal/fuse/fuse_gp106.c \
diff --git a/drivers/gpu/nvgpu/common/mm/mm.c b/drivers/gpu/nvgpu/common/mm/mm.c
index 94a9b4222..39e65d1b8 100644
--- a/drivers/gpu/nvgpu/common/mm/mm.c
+++ b/drivers/gpu/nvgpu/common/mm/mm.c
@@ -130,8 +130,8 @@ int nvgpu_mm_suspend(struct gk20a *g)
 		return err;
 	}
 
-	if (g->ops.fb.disable_hub_intr != NULL) {
-		g->ops.fb.disable_hub_intr(g);
+	if (g->ops.fb.intr.disable != NULL) {
+		g->ops.fb.intr.disable(g);
 	}
 
 	if (g->ops.mm.mmu_fault_disable_hw != NULL) {
diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
index 3c2d96e03..ad0247d75 100644
--- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -47,6 +47,7 @@
 #include "hal/fb/fb_gm20b.h"
 #include "hal/fb/fb_gp10b.h"
 #include "hal/fb/fb_gv11b.h"
+#include "hal/fb/intr/fb_intr_gv11b.h"
 #include "hal/gr/init/gr_init_gm20b.h"
 #include "hal/gr/init/gr_init_gp10b.h"
 #include "hal/gr/init/gr_init_gv11b.h"
@@ -444,9 +445,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.is_debug_mode_enabled = NULL,
 		.set_debug_mode = vgpu_mm_mmu_set_debug_mode,
 		.tlb_invalidate = vgpu_mm_tlb_invalidate,
-		.hub_isr = gv11b_fb_hub_isr,
-		.enable_hub_intr = gv11b_fb_enable_hub_intr,
-		.disable_hub_intr = gv11b_fb_disable_hub_intr,
 		.write_mmu_fault_buffer_lo_hi =
 				fb_gv11b_write_mmu_fault_buffer_lo_hi,
 		.write_mmu_fault_buffer_get =
@@ -464,6 +462,11 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.read_mmu_fault_inst_lo_hi = fb_gv11b_read_mmu_fault_inst_lo_hi,
 		.read_mmu_fault_info = fb_gv11b_read_mmu_fault_info,
 		.read_mmu_fault_status = fb_gv11b_read_mmu_fault_status,
+		.intr = {
+			.enable = gv11b_fb_intr_enable,
+			.disable = gv11b_fb_intr_disable,
+			.isr = gv11b_fb_intr_isr,
+		},
 	},
 	.cg = {
 		.slcg_bus_load_gating_prod = NULL,
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 24a4de326..2a297f1ce 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -47,6 +47,8 @@
 #include "hal/fb/fb_gp106.h"
 #include "hal/fb/fb_gv11b.h"
 #include "hal/fb/fb_gv100.h"
+#include "hal/fb/intr/fb_intr_gv100.h"
+#include "hal/fb/intr/fb_intr_gv11b.h"
 #include "hal/fuse/fuse_gm20b.h"
 #include "hal/fuse/fuse_gp10b.h"
 #include "hal/fuse/fuse_gp106.h"
@@ -800,12 +802,9 @@ static const struct gpu_ops gv100_ops = {
 		.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
 		.set_debug_mode = gm20b_fb_set_debug_mode,
 		.tlb_invalidate = gm20b_fb_tlb_invalidate,
-		.hub_isr = gv11b_fb_hub_isr,
 		.mem_unlock = gv100_fb_memory_unlock,
 		.init_nvlink = gv100_fb_init_nvlink,
 		.enable_nvlink = gv100_fb_enable_nvlink,
-		.enable_hub_intr = gv100_fb_enable_hub_intr,
-		.disable_hub_intr = gv100_fb_disable_hub_intr,
 		.write_mmu_fault_buffer_lo_hi =
 				fb_gv11b_write_mmu_fault_buffer_lo_hi,
 		.write_mmu_fault_buffer_get =
@@ -829,6 +828,11 @@ static const struct gpu_ops gv100_ops = {
 		.fault_buf_set_state_hw = gv11b_fb_fault_buf_set_state_hw,
 		.fault_buf_configure_hw = gv11b_fb_fault_buf_configure_hw,
 		.get_vidmem_size = gv100_fb_get_vidmem_size,
+		.intr = {
+			.enable = gv100_fb_intr_enable,
+			.disable = gv100_fb_intr_disable,
+			.isr = gv11b_fb_intr_isr,
+		},
 	},
 	.nvdec = {
 		.falcon_base_addr = gp106_nvdec_falcon_base_addr,
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 21ee31913..01965f85b 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -50,6 +50,7 @@
 #include "hal/fb/fb_gm20b.h"
 #include "hal/fb/fb_gp10b.h"
 #include "hal/fb/fb_gv11b.h"
+#include "hal/fb/intr/fb_intr_gv11b.h"
 #include "hal/fuse/fuse_gm20b.h"
 #include "hal/fuse/fuse_gp10b.h"
 #include "hal/fifo/pbdma_gm20b.h"
@@ -762,11 +763,8 @@ static const struct gpu_ops gv11b_ops = {
 		.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
 		.set_debug_mode = gm20b_fb_set_debug_mode,
 		.tlb_invalidate = gm20b_fb_tlb_invalidate,
-		.hub_isr = gv11b_fb_hub_isr,
 		.handle_replayable_fault = gv11b_fb_handle_replayable_mmu_fault,
 		.mem_unlock = NULL,
-		.enable_hub_intr = gv11b_fb_enable_hub_intr,
-		.disable_hub_intr = gv11b_fb_disable_hub_intr,
 		.write_mmu_fault_buffer_lo_hi =
 				fb_gv11b_write_mmu_fault_buffer_lo_hi,
 		.write_mmu_fault_buffer_get =
@@ -789,6 +787,11 @@ static const struct gpu_ops gv11b_ops = {
 		.is_fault_buf_enabled = gv11b_fb_is_fault_buf_enabled,
 		.fault_buf_set_state_hw = gv11b_fb_fault_buf_set_state_hw,
 		.fault_buf_configure_hw = gv11b_fb_fault_buf_configure_hw,
+		.intr = {
+			.enable = gv11b_fb_intr_enable,
+			.disable = gv11b_fb_intr_disable,
+			.isr = gv11b_fb_intr_isr,
+		},
 	},
 	.cg = {
 		.slcg_bus_load_gating_prod =
diff --git a/drivers/gpu/nvgpu/hal/fb/fb_gv11b.c b/drivers/gpu/nvgpu/hal/fb/fb_gv11b.c
index 40f64cdf3..a1c6adee5 100644
--- a/drivers/gpu/nvgpu/hal/fb/fb_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/fb/fb_gv11b.c
@@ -97,7 +97,7 @@ void gv11b_fb_init_hw(struct gk20a *g)
 {
 	gm20b_fb_init_hw(g);
 
-	g->ops.fb.enable_hub_intr(g);
+	g->ops.fb.intr.enable(g);
 }
 
 void gv11b_fb_init_fs_state(struct gk20a *g)
@@ -413,278 +413,6 @@ void gv11b_fb_fault_buf_configure_hw(struct gk20a *g, u32 index)
 	gv11b_fb_fault_buf_set_state_hw(g, index, NVGPU_FB_MMU_FAULT_BUF_ENABLED);
 }
 
-void gv11b_fb_enable_hub_intr(struct gk20a *g)
-{
-	u32 mask = 0;
-
-	mask = fb_niso_intr_en_set_mmu_other_fault_notify_m() |
-			fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m() |
-			fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m() |
-			fb_niso_intr_en_set_mmu_replayable_fault_notify_m() |
-			fb_niso_intr_en_set_mmu_replayable_fault_overflow_m() |
-			fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_m();
-
-	gk20a_writel(g, fb_niso_intr_en_set_r(0),
-			mask);
-}
-
-void gv11b_fb_disable_hub_intr(struct gk20a *g)
-{
-	u32 mask = 0;
-
-	mask = fb_niso_intr_en_set_mmu_other_fault_notify_m() |
-			fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m() |
-			fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m() |
-			fb_niso_intr_en_set_mmu_replayable_fault_notify_m() |
-			fb_niso_intr_en_set_mmu_replayable_fault_overflow_m() |
-			fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_m();
-
-	gk20a_writel(g, fb_niso_intr_en_clr_r(0),
-			mask);
-}
-
-void gv11b_handle_l2tlb_ecc_isr(struct gk20a *g, u32 ecc_status)
-{
-	u32 ecc_addr, corrected_cnt, uncorrected_cnt;
-	u32 corrected_delta, uncorrected_delta;
-	u32 corrected_overflow, uncorrected_overflow;
-
-	ecc_addr = gk20a_readl(g, fb_mmu_l2tlb_ecc_address_r());
-	corrected_cnt = gk20a_readl(g,
-		fb_mmu_l2tlb_ecc_corrected_err_count_r());
-	uncorrected_cnt = gk20a_readl(g,
-		fb_mmu_l2tlb_ecc_uncorrected_err_count_r());
-
-	corrected_delta = fb_mmu_l2tlb_ecc_corrected_err_count_total_v(
-							corrected_cnt);
-	uncorrected_delta = fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(
-							uncorrected_cnt);
-	corrected_overflow = ecc_status &
-		fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m();
-
-	uncorrected_overflow = ecc_status &
-		fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m();
-
-	/* clear the interrupt */
-	if ((corrected_delta > 0U) || (corrected_overflow != 0U)) {
-		gk20a_writel(g, fb_mmu_l2tlb_ecc_corrected_err_count_r(), 0);
-	}
-	if ((uncorrected_delta > 0U) || (uncorrected_overflow != 0U)) {
-		gk20a_writel(g, fb_mmu_l2tlb_ecc_uncorrected_err_count_r(), 0);
-	}
-
-	gk20a_writel(g, fb_mmu_l2tlb_ecc_status_r(),
-				fb_mmu_l2tlb_ecc_status_reset_clear_f());
-
-	/* Handle overflow */
-	if (corrected_overflow != 0U) {
-		corrected_delta += BIT32(fb_mmu_l2tlb_ecc_corrected_err_count_total_s());
-	}
-	if (uncorrected_overflow != 0U) {
-		uncorrected_delta += BIT32(fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s());
-	}
-
-
-	g->ecc.fb.mmu_l2tlb_ecc_corrected_err_count[0].counter +=
-							corrected_delta;
-	g->ecc.fb.mmu_l2tlb_ecc_uncorrected_err_count[0].counter +=
-							uncorrected_delta;
-
-	if ((ecc_status &
-             fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m()) != 0U) {
-		nvgpu_hubmmu_report_ecc_error(g, 0,
-				GPU_HUBMMU_L2TLB_SA_DATA_ECC_CORRECTED,
-				ecc_addr,
-				g->ecc.fb.mmu_l2tlb_ecc_corrected_err_count[0].counter);
-		nvgpu_log(g, gpu_dbg_intr, "corrected ecc sa data error");
-	}
-	if ((ecc_status &
-             fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m()) != 0U) {
-		nvgpu_hubmmu_report_ecc_error(g, 0,
-				GPU_HUBMMU_L2TLB_SA_DATA_ECC_UNCORRECTED,
-				ecc_addr,
-				g->ecc.fb.mmu_l2tlb_ecc_uncorrected_err_count[0].counter);
-		nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc sa data error");
-	}
-	if ((corrected_overflow != 0U) || (uncorrected_overflow != 0U)) {
-		nvgpu_info(g, "mmu l2tlb ecc counter overflow!");
-	}
-
-	nvgpu_log(g, gpu_dbg_intr,
-		"ecc error address: 0x%x", ecc_addr);
-	nvgpu_log(g, gpu_dbg_intr,
-		"ecc error count corrected: %d, uncorrected %d",
-		g->ecc.fb.mmu_l2tlb_ecc_corrected_err_count[0].counter,
-		g->ecc.fb.mmu_l2tlb_ecc_uncorrected_err_count[0].counter);
-}
-
-void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status)
-{
-	u32 ecc_addr, corrected_cnt, uncorrected_cnt;
-	u32 corrected_delta, uncorrected_delta;
-	u32 corrected_overflow, uncorrected_overflow;
-
-	ecc_addr = gk20a_readl(g, fb_mmu_hubtlb_ecc_address_r());
-	corrected_cnt = gk20a_readl(g,
-		fb_mmu_hubtlb_ecc_corrected_err_count_r());
-	uncorrected_cnt = gk20a_readl(g,
-		fb_mmu_hubtlb_ecc_uncorrected_err_count_r());
-
-	corrected_delta = fb_mmu_hubtlb_ecc_corrected_err_count_total_v(
-							corrected_cnt);
-	uncorrected_delta = fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(
-							uncorrected_cnt);
-	corrected_overflow = ecc_status &
-		fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m();
-
-	uncorrected_overflow = ecc_status &
-		fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m();
-
-	/* clear the interrupt */
-	if ((corrected_delta > 0U) || (corrected_overflow != 0U)) {
-		gk20a_writel(g, fb_mmu_hubtlb_ecc_corrected_err_count_r(), 0);
-	}
-	if ((uncorrected_delta > 0U) || (uncorrected_overflow != 0U)) {
-		gk20a_writel(g, fb_mmu_hubtlb_ecc_uncorrected_err_count_r(), 0);
-	}
-
-	gk20a_writel(g, fb_mmu_hubtlb_ecc_status_r(),
-				fb_mmu_hubtlb_ecc_status_reset_clear_f());
-
-	/* Handle overflow */
-	if (corrected_overflow != 0U) {
-		corrected_delta += BIT32(fb_mmu_hubtlb_ecc_corrected_err_count_total_s());
-	}
-	if (uncorrected_overflow != 0U) {
-		uncorrected_delta += BIT32(fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s());
-	}
-
-
-	g->ecc.fb.mmu_hubtlb_ecc_corrected_err_count[0].counter +=
-							corrected_delta;
-	g->ecc.fb.mmu_hubtlb_ecc_uncorrected_err_count[0].counter +=
-							uncorrected_delta;
-
-	if ((ecc_status &
-	     fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m()) != 0U) {
-		nvgpu_hubmmu_report_ecc_error(g, 0,
-				GPU_HUBMMU_TLB_SA_DATA_ECC_CORRECTED,
-				ecc_addr,
-				g->ecc.fb.mmu_hubtlb_ecc_corrected_err_count[0].counter);
-		nvgpu_log(g, gpu_dbg_intr, "corrected ecc sa data error");
-	}
-	if ((ecc_status &
-	     fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m()) != 0U) {
-		nvgpu_hubmmu_report_ecc_error(g, 0,
-				GPU_HUBMMU_TLB_SA_DATA_ECC_UNCORRECTED,
-				ecc_addr,
-				g->ecc.fb.mmu_hubtlb_ecc_uncorrected_err_count[0].counter);
-		nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc sa data error");
-	}
-	if ((corrected_overflow != 0U) || (uncorrected_overflow != 0U)) {
-		nvgpu_info(g, "mmu hubtlb ecc counter overflow!");
-	}
-
-	nvgpu_log(g, gpu_dbg_intr,
-		"ecc error address: 0x%x", ecc_addr);
-	nvgpu_log(g, gpu_dbg_intr,
-		"ecc error count corrected: %d, uncorrected %d",
-		g->ecc.fb.mmu_hubtlb_ecc_corrected_err_count[0].counter,
-		g->ecc.fb.mmu_hubtlb_ecc_uncorrected_err_count[0].counter);
-}
-
-void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status)
-{
-	u32 ecc_addr, corrected_cnt, uncorrected_cnt;
-	u32 corrected_delta, uncorrected_delta;
-	u32 corrected_overflow, uncorrected_overflow;
-
-	ecc_addr = gk20a_readl(g, fb_mmu_fillunit_ecc_address_r());
-	corrected_cnt = gk20a_readl(g,
-		fb_mmu_fillunit_ecc_corrected_err_count_r());
-	uncorrected_cnt = gk20a_readl(g,
-		fb_mmu_fillunit_ecc_uncorrected_err_count_r());
-
-	corrected_delta = fb_mmu_fillunit_ecc_corrected_err_count_total_v(
-							corrected_cnt);
-	uncorrected_delta = fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(
-							uncorrected_cnt);
-	corrected_overflow = ecc_status &
-		fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m();
-
-	uncorrected_overflow = ecc_status &
-		fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m();
-
-	/* clear the interrupt */
-	if ((corrected_delta > 0U) || (corrected_overflow != 0U)) {
-		gk20a_writel(g, fb_mmu_fillunit_ecc_corrected_err_count_r(), 0);
-	}
-	if ((uncorrected_delta > 0U) || (uncorrected_overflow != 0U)) {
-		gk20a_writel(g, fb_mmu_fillunit_ecc_uncorrected_err_count_r(), 0);
-	}
-
-	gk20a_writel(g, fb_mmu_fillunit_ecc_status_r(),
-				fb_mmu_fillunit_ecc_status_reset_clear_f());
-
-	/* Handle overflow */
-	if (corrected_overflow != 0U) {
-		corrected_delta += BIT32(fb_mmu_fillunit_ecc_corrected_err_count_total_s());
-	}
-	if (uncorrected_overflow != 0U) {
-		uncorrected_delta += BIT32(fb_mmu_fillunit_ecc_uncorrected_err_count_total_s());
-	}
-
-
-	g->ecc.fb.mmu_fillunit_ecc_corrected_err_count[0].counter +=
-							corrected_delta;
-	g->ecc.fb.mmu_fillunit_ecc_uncorrected_err_count[0].counter +=
-							uncorrected_delta;
-
-	if ((ecc_status &
-             fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m()) != 0U) {
-		nvgpu_hubmmu_report_ecc_error(g, 0,
-				GPU_HUBMMU_PTE_DATA_ECC_CORRECTED,
-				ecc_addr,
-				g->ecc.fb.mmu_fillunit_ecc_corrected_err_count[0].counter);
-		nvgpu_log(g, gpu_dbg_intr, "corrected ecc pte data error");
-	}
-	if ((ecc_status &
-             fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m()) != 0U) {
-		nvgpu_hubmmu_report_ecc_error(g, 0,
-				GPU_HUBMMU_PTE_DATA_ECC_UNCORRECTED,
-				ecc_addr,
-				g->ecc.fb.mmu_fillunit_ecc_uncorrected_err_count[0].counter);
-		nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc pte data error");
-	}
-	if ((ecc_status &
-             fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m()) != 0U) {
-		nvgpu_hubmmu_report_ecc_error(g, 0,
-				GPU_HUBMMU_PDE0_DATA_ECC_CORRECTED,
-				ecc_addr,
-				g->ecc.fb.mmu_fillunit_ecc_corrected_err_count[0].counter);
-		nvgpu_log(g, gpu_dbg_intr, "corrected ecc pde0 data error");
-	}
-	if ((ecc_status &
-             fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m()) != 0U) {
-		nvgpu_hubmmu_report_ecc_error(g, 0,
-				GPU_HUBMMU_PDE0_DATA_ECC_UNCORRECTED,
-				ecc_addr,
-				g->ecc.fb.mmu_fillunit_ecc_uncorrected_err_count[0].counter);
-		nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc pde0 data error");
-	}
-
-	if ((corrected_overflow != 0U) || (uncorrected_overflow != 0U)) {
-		nvgpu_info(g, "mmu fillunit ecc counter overflow!");
-	}
-
-	nvgpu_log(g, gpu_dbg_intr,
-		"ecc error address: 0x%x", ecc_addr);
-	nvgpu_log(g, gpu_dbg_intr,
-		"ecc error count corrected: %d, uncorrected %d",
-		g->ecc.fb.mmu_fillunit_ecc_corrected_err_count[0].counter,
-		g->ecc.fb.mmu_fillunit_ecc_uncorrected_err_count[0].counter);
-}
-
 static void gv11b_fb_parse_mmfault(struct mmu_fault_info *mmfault)
 {
 	if (mmfault->fault_type >= ARRAY_SIZE(fault_type_descs_gv11b)) {
@@ -1384,7 +1112,7 @@ void gv11b_fb_handle_replayable_mmu_fault(struct gk20a *g)
 	}
 }
 
-static void gv11b_fb_handle_mmu_fault(struct gk20a *g, u32 niso_intr)
+void gv11b_fb_handle_mmu_fault(struct gk20a *g, u32 niso_intr)
 {
 	u32 fault_status = g->ops.fb.read_mmu_fault_status(g);
 
@@ -1445,57 +1173,6 @@ static void gv11b_fb_handle_mmu_fault(struct gk20a *g, u32 niso_intr)
 			fb_mmu_fault_status_valid_clear_f());
 }
 
-void gv11b_fb_hub_isr(struct gk20a *g)
-{
-	u32 status, niso_intr;
-
-	nvgpu_mutex_acquire(&g->mm.hub_isr_mutex);
-
-	niso_intr = gk20a_readl(g, fb_niso_intr_r());
-
-	nvgpu_log(g, gpu_dbg_intr, "enter hub isr, niso_intr = 0x%08x",
-			niso_intr);
-
-	if ((niso_intr &
-		 (fb_niso_intr_hub_access_counter_notify_m() |
-		  fb_niso_intr_hub_access_counter_error_m())) != 0U) {
-
-		nvgpu_info(g, "hub access counter notify/error");
-	}
-	if ((niso_intr &
-	     fb_niso_intr_mmu_ecc_uncorrected_error_notify_pending_f()) != 0U) {
-
-		nvgpu_info(g, "ecc uncorrected error notify");
-
-		status = gk20a_readl(g, fb_mmu_l2tlb_ecc_status_r());
-		if (status != 0U) {
-			gv11b_handle_l2tlb_ecc_isr(g, status);
-		}
-
-		status = gk20a_readl(g, fb_mmu_hubtlb_ecc_status_r());
-		if (status != 0U) {
-			gv11b_handle_hubtlb_ecc_isr(g, status);
-		}
-
-		status = gk20a_readl(g, fb_mmu_fillunit_ecc_status_r());
-		if (status != 0U) {
-			gv11b_handle_fillunit_ecc_isr(g, status);
-		}
-	}
-	if ((niso_intr &
-		(fb_niso_intr_mmu_other_fault_notify_m() |
-		fb_niso_intr_mmu_replayable_fault_notify_m() |
-		fb_niso_intr_mmu_replayable_fault_overflow_m() |
-		fb_niso_intr_mmu_nonreplayable_fault_notify_m() |
-		fb_niso_intr_mmu_nonreplayable_fault_overflow_m())) != 0U) {
-
-		nvgpu_log(g, gpu_dbg_intr, "MMU Fault");
-		gv11b_fb_handle_mmu_fault(g, niso_intr);
-	}
-
-	nvgpu_mutex_release(&g->mm.hub_isr_mutex);
-}
-
 bool gv11b_fb_mmu_fault_pending(struct gk20a *g)
 {
 	if ((gk20a_readl(g, fb_niso_intr_r()) &
diff --git a/drivers/gpu/nvgpu/hal/fb/fb_gv11b.h b/drivers/gpu/nvgpu/hal/fb/fb_gv11b.h
index 8883179eb..d240e26d2 100644
--- a/drivers/gpu/nvgpu/hal/fb/fb_gv11b.h
+++ b/drivers/gpu/nvgpu/hal/fb/fb_gv11b.h
@@ -33,18 +33,15 @@ struct gr_gk20a;
 struct nvgpu_cbc;
 
 void gv11b_fb_init_hw(struct gk20a *g);
-
+void gv11b_fb_handle_mmu_fault(struct gk20a *g, u32 niso_intr);
 void gv11b_fb_init_fs_state(struct gk20a *g);
 void gv11b_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc);
 void gv11b_fb_reset(struct gk20a *g);
-void gv11b_fb_hub_isr(struct gk20a *g);
 
 bool gv11b_fb_is_fault_buf_enabled(struct gk20a *g, u32 index	);
 void gv11b_fb_fault_buf_set_state_hw(struct gk20a *g,
 		 u32 index, u32 state);
 void gv11b_fb_fault_buf_configure_hw(struct gk20a *g, u32 index);
-void gv11b_fb_enable_hub_intr(struct gk20a *g);
-void gv11b_fb_disable_hub_intr(struct gk20a *g);
 bool gv11b_fb_mmu_fault_pending(struct gk20a *g);
 void gv11b_fb_handle_dropped_mmu_fault(struct gk20a *g, u32 fault_status);
 void gv11b_fb_handle_other_fault_notify(struct gk20a *g,
@@ -56,9 +53,6 @@ void gv11b_fb_handle_nonreplay_fault_overflow(struct gk20a *g,
 void gv11b_fb_handle_replay_fault_overflow(struct gk20a *g,
 			 u32 fault_status);
 void gv11b_fb_handle_replayable_mmu_fault(struct gk20a *g);
-void gv11b_handle_l2tlb_ecc_isr(struct gk20a *g, u32 ecc_status);
-void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status);
-void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status);
 
 void fb_gv11b_write_mmu_fault_buffer_lo_hi(struct gk20a *g, u32 index,
 	u32 addr_lo, u32 addr_hi);
diff --git a/drivers/gpu/nvgpu/hal/fb/fb_tu104.c b/drivers/gpu/nvgpu/hal/fb/fb_tu104.c
index c69431908..938f82a82 100644
--- a/drivers/gpu/nvgpu/hal/fb/fb_tu104.c
+++ b/drivers/gpu/nvgpu/hal/fb/fb_tu104.c
@@ -42,52 +42,6 @@
 #include "nvgpu/hw/tu104/hw_fb_tu104.h"
 #include "nvgpu/hw/tu104/hw_func_tu104.h"
 
-void tu104_fb_enable_hub_intr(struct gk20a *g)
-{
-	u32 info_fault = nvgpu_readl(g, fb_mmu_int_vector_info_fault_r());
-	u32 nonreplay_fault = nvgpu_readl(g,
-		fb_mmu_int_vector_fault_r(NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX));
-	u32 replay_fault = nvgpu_readl(g,
-		fb_mmu_int_vector_fault_r(NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX));
-	u32 ecc_error = nvgpu_readl(g, fb_mmu_int_vector_ecc_error_r());
-
-	intr_tu104_vector_en_set(g,
-		fb_mmu_int_vector_info_fault_vector_v(info_fault));
-	intr_tu104_vector_en_set(g,
-		fb_mmu_int_vector_fault_notify_v(nonreplay_fault));
-	intr_tu104_vector_en_set(g,
-		fb_mmu_int_vector_fault_error_v(nonreplay_fault));
-	intr_tu104_vector_en_set(g,
-		fb_mmu_int_vector_fault_notify_v(replay_fault));
-	intr_tu104_vector_en_set(g,
-		fb_mmu_int_vector_fault_error_v(replay_fault));
-	intr_tu104_vector_en_set(g,
-		fb_mmu_int_vector_ecc_error_vector_v(ecc_error));
-}
-
-void tu104_fb_disable_hub_intr(struct gk20a *g)
-{
-	u32 info_fault = nvgpu_readl(g, fb_mmu_int_vector_info_fault_r());
-	u32 nonreplay_fault = nvgpu_readl(g,
-		fb_mmu_int_vector_fault_r(NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX));
-	u32 replay_fault = nvgpu_readl(g,
-		fb_mmu_int_vector_fault_r(NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX));
-	u32 ecc_error = nvgpu_readl(g, fb_mmu_int_vector_ecc_error_r());
-
-	intr_tu104_vector_en_clear(g,
-		fb_mmu_int_vector_info_fault_vector_v(info_fault));
-	intr_tu104_vector_en_clear(g,
-		fb_mmu_int_vector_fault_notify_v(nonreplay_fault));
-	intr_tu104_vector_en_clear(g,
-		fb_mmu_int_vector_fault_error_v(nonreplay_fault));
-	intr_tu104_vector_en_clear(g,
-		fb_mmu_int_vector_fault_notify_v(replay_fault));
-	intr_tu104_vector_en_clear(g,
-		fb_mmu_int_vector_fault_error_v(replay_fault));
-	intr_tu104_vector_en_clear(g,
-		fb_mmu_int_vector_ecc_error_vector_v(ecc_error));
-}
-
 bool tu104_fb_mmu_fault_pending(struct gk20a *g)
 {
 	u32 info_fault = nvgpu_readl(g, fb_mmu_int_vector_info_fault_r());
@@ -115,7 +69,7 @@ bool tu104_fb_mmu_fault_pending(struct gk20a *g)
 	return false;
 }
 
-static void tu104_fb_handle_mmu_fault(struct gk20a *g)
+void tu104_fb_handle_mmu_fault(struct gk20a *g)
 {
 	u32 info_fault = nvgpu_readl(g, fb_mmu_int_vector_info_fault_r());
 	u32 nonreplay_fault = nvgpu_readl(g,
@@ -190,58 +144,6 @@ static void tu104_fb_handle_mmu_fault(struct gk20a *g)
 				fb_mmu_fault_status_valid_clear_f());
 }
 
-void tu104_fb_hub_isr(struct gk20a *g)
-{
-	u32 info_fault = nvgpu_readl(g, fb_mmu_int_vector_info_fault_r());
-	u32 nonreplay_fault = nvgpu_readl(g,
-		fb_mmu_int_vector_fault_r(NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX));
-	u32 replay_fault = nvgpu_readl(g,
-		fb_mmu_int_vector_fault_r(NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX));
-	u32 ecc_error = nvgpu_readl(g, fb_mmu_int_vector_ecc_error_r());
-	u32 status;
-
-	nvgpu_mutex_acquire(&g->mm.hub_isr_mutex);
-
-	if (intr_tu104_vector_intr_pending(g,
-			fb_mmu_int_vector_ecc_error_vector_v(ecc_error))) {
-		nvgpu_info(g, "ecc uncorrected error notify");
-
-		intr_tu104_intr_clear_leaf_vector(g,
-			fb_mmu_int_vector_ecc_error_vector_v(ecc_error));
-
-		status = nvgpu_readl(g, fb_mmu_l2tlb_ecc_status_r());
-		if (status != 0U) {
-			gv11b_handle_l2tlb_ecc_isr(g, status);
-		}
-
-		status = nvgpu_readl(g, fb_mmu_hubtlb_ecc_status_r());
-		if (status != 0U) {
-			gv11b_handle_hubtlb_ecc_isr(g, status);
-		}
-
-		status = nvgpu_readl(g, fb_mmu_fillunit_ecc_status_r());
-		if (status != 0U) {
-			gv11b_handle_fillunit_ecc_isr(g, status);
-		}
-	}
-
-	if (intr_tu104_vector_intr_pending(g,
-			fb_mmu_int_vector_fault_notify_v(replay_fault)) ||
-	    intr_tu104_vector_intr_pending(g,
-			fb_mmu_int_vector_fault_error_v(replay_fault)) ||
-	    intr_tu104_vector_intr_pending(g,
-			fb_mmu_int_vector_fault_notify_v(nonreplay_fault)) ||
-	    intr_tu104_vector_intr_pending(g,
-			fb_mmu_int_vector_fault_error_v(nonreplay_fault)) ||
-	    intr_tu104_vector_intr_pending(g,
-			fb_mmu_int_vector_info_fault_vector_v(info_fault))) {
-		nvgpu_log(g, gpu_dbg_intr, "MMU Fault");
-		tu104_fb_handle_mmu_fault(g);
-	}
-
-	nvgpu_mutex_release(&g->mm.hub_isr_mutex);
-}
-
 void fb_tu104_write_mmu_fault_buffer_lo_hi(struct gk20a *g, u32 index,
 	u32 addr_lo, u32 addr_hi)
 {
diff --git a/drivers/gpu/nvgpu/hal/fb/fb_tu104.h b/drivers/gpu/nvgpu/hal/fb/fb_tu104.h
index db2ccdf04..ef429106e 100644
--- a/drivers/gpu/nvgpu/hal/fb/fb_tu104.h
+++ b/drivers/gpu/nvgpu/hal/fb/fb_tu104.h
@@ -30,10 +30,8 @@ struct gr_gk20a;
 struct nvgpu_mem;
 struct nvgpu_cbc;
 
-void tu104_fb_enable_hub_intr(struct gk20a *g);
-void tu104_fb_disable_hub_intr(struct gk20a *g);
+void tu104_fb_handle_mmu_fault(struct gk20a *g);
 bool tu104_fb_mmu_fault_pending(struct gk20a *g);
-void tu104_fb_hub_isr(struct gk20a *g);
 
 void fb_tu104_write_mmu_fault_buffer_lo_hi(struct gk20a *g, u32 index,
 	u32 addr_lo, u32 addr_hi);
diff --git a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b.c b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b.c
new file mode 100644
index 000000000..6b74b4f8a
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b.c
@@ -0,0 +1,307 @@
+/*
+ * GV11B ECC INTR
+ *
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/nvgpu_err.h>
+
+#include "fb_intr_ecc_gv11b.h"
+
+#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
+
+static void gv11b_fb_intr_handle_ecc_l2tlb(struct gk20a *g, u32 ecc_status)
+{
+	u32 ecc_addr, corrected_cnt, uncorrected_cnt;
+	u32 corrected_delta, uncorrected_delta;
+	u32 corrected_overflow, uncorrected_overflow;
+
+	ecc_addr = nvgpu_readl(g, fb_mmu_l2tlb_ecc_address_r());
+	corrected_cnt = nvgpu_readl(g,
+		fb_mmu_l2tlb_ecc_corrected_err_count_r());
+	uncorrected_cnt = nvgpu_readl(g,
+		fb_mmu_l2tlb_ecc_uncorrected_err_count_r());
+
+	corrected_delta = fb_mmu_l2tlb_ecc_corrected_err_count_total_v(
+							corrected_cnt);
+	uncorrected_delta = fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(
+							uncorrected_cnt);
+	corrected_overflow = ecc_status &
+		fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m();
+
+	uncorrected_overflow = ecc_status &
+		fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m();
+
+	/* clear the interrupt */
+	if ((corrected_delta > 0U) || (corrected_overflow != 0U)) {
+		nvgpu_writel(g, fb_mmu_l2tlb_ecc_corrected_err_count_r(), 0);
+	}
+	if ((uncorrected_delta > 0U) || (uncorrected_overflow != 0U)) {
+		nvgpu_writel(g, fb_mmu_l2tlb_ecc_uncorrected_err_count_r(), 0);
+	}
+
+	nvgpu_writel(g, fb_mmu_l2tlb_ecc_status_r(),
+				fb_mmu_l2tlb_ecc_status_reset_clear_f());
+
+	/* Handle overflow */
+	if (corrected_overflow != 0U) {
+		corrected_delta +=
+			BIT32(fb_mmu_l2tlb_ecc_corrected_err_count_total_s());
+	}
+	if (uncorrected_overflow != 0U) {
+		uncorrected_delta +=
+			BIT32(fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s());
+	}
+
+
+	g->ecc.fb.mmu_l2tlb_ecc_corrected_err_count[0].counter +=
+							corrected_delta;
+	g->ecc.fb.mmu_l2tlb_ecc_uncorrected_err_count[0].counter +=
+							uncorrected_delta;
+
+	if ((ecc_status &
+		fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m())
+									!= 0U) {
+		nvgpu_hubmmu_report_ecc_error(g, 0,
+			GPU_HUBMMU_L2TLB_SA_DATA_ECC_CORRECTED,
+			ecc_addr,
+			g->ecc.fb.mmu_l2tlb_ecc_corrected_err_count[0].counter);
+		nvgpu_log(g, gpu_dbg_intr, "corrected ecc sa data error");
+	}
+	if ((ecc_status &
+		fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m())
+									!= 0U) {
+		nvgpu_hubmmu_report_ecc_error(g, 0,
+			GPU_HUBMMU_L2TLB_SA_DATA_ECC_UNCORRECTED,
+			ecc_addr,
+			g->ecc.fb.mmu_l2tlb_ecc_uncorrected_err_count[0].counter);
+		nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc sa data error");
+	}
+	if ((corrected_overflow != 0U) || (uncorrected_overflow != 0U)) {
+		nvgpu_info(g, "mmu l2tlb ecc counter overflow!");
+	}
+
+	nvgpu_log(g, gpu_dbg_intr,
+		"ecc error address: 0x%x", ecc_addr);
+	nvgpu_log(g, gpu_dbg_intr,
+		"ecc error count corrected: %d, uncorrected %d",
+		g->ecc.fb.mmu_l2tlb_ecc_corrected_err_count[0].counter,
+		g->ecc.fb.mmu_l2tlb_ecc_uncorrected_err_count[0].counter);
+}
+
+static void gv11b_fb_intr_handle_ecc_hubtlb(struct gk20a *g, u32 ecc_status)
+{
+	u32 ecc_addr, corrected_cnt, uncorrected_cnt;
+	u32 corrected_delta, uncorrected_delta;
+	u32 corrected_overflow, uncorrected_overflow;
+
+	ecc_addr = nvgpu_readl(g, fb_mmu_hubtlb_ecc_address_r());
+	corrected_cnt = nvgpu_readl(g,
+		fb_mmu_hubtlb_ecc_corrected_err_count_r());
+	uncorrected_cnt = nvgpu_readl(g,
+		fb_mmu_hubtlb_ecc_uncorrected_err_count_r());
+
+	corrected_delta = fb_mmu_hubtlb_ecc_corrected_err_count_total_v(
+							corrected_cnt);
+	uncorrected_delta = fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(
+							uncorrected_cnt);
+	corrected_overflow = ecc_status &
+		fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m();
+
+	uncorrected_overflow = ecc_status &
+		fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m();
+
+	/* clear the interrupt */
+	if ((corrected_delta > 0U) || (corrected_overflow != 0U)) {
+		nvgpu_writel(g, fb_mmu_hubtlb_ecc_corrected_err_count_r(), 0);
+	}
+	if ((uncorrected_delta > 0U) || (uncorrected_overflow != 0U)) {
+		nvgpu_writel(g, fb_mmu_hubtlb_ecc_uncorrected_err_count_r(), 0);
+	}
+
+	nvgpu_writel(g, fb_mmu_hubtlb_ecc_status_r(),
+				fb_mmu_hubtlb_ecc_status_reset_clear_f());
+
+	/* Handle overflow */
+	if (corrected_overflow != 0U) {
+		corrected_delta +=
+			BIT32(fb_mmu_hubtlb_ecc_corrected_err_count_total_s());
+	}
+	if (uncorrected_overflow != 0U) {
+		uncorrected_delta +=
+			BIT32(fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s());
+	}
+
+
+	g->ecc.fb.mmu_hubtlb_ecc_corrected_err_count[0].counter +=
+							corrected_delta;
+	g->ecc.fb.mmu_hubtlb_ecc_uncorrected_err_count[0].counter +=
+							uncorrected_delta;
+
+	if ((ecc_status &
+	     fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m()) != 0U) {
+		nvgpu_hubmmu_report_ecc_error(g, 0,
+				GPU_HUBMMU_TLB_SA_DATA_ECC_CORRECTED,
+				ecc_addr,
+				g->ecc.fb.mmu_hubtlb_ecc_corrected_err_count[0].counter);
+		nvgpu_log(g, gpu_dbg_intr, "corrected ecc sa data error");
+	}
+	if ((ecc_status &
+	     fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m()) != 0U) {
+		nvgpu_hubmmu_report_ecc_error(g, 0,
+				GPU_HUBMMU_TLB_SA_DATA_ECC_UNCORRECTED,
+				ecc_addr,
+				g->ecc.fb.mmu_hubtlb_ecc_uncorrected_err_count[0].counter);
+		nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc sa data error");
+	}
+	if ((corrected_overflow != 0U) || (uncorrected_overflow != 0U)) {
+		nvgpu_info(g, "mmu hubtlb ecc counter overflow!");
+	}
+
+	nvgpu_log(g, gpu_dbg_intr,
+		"ecc error address: 0x%x", ecc_addr);
+	nvgpu_log(g, gpu_dbg_intr,
+		"ecc error count corrected: %d, uncorrected %d",
+		g->ecc.fb.mmu_hubtlb_ecc_corrected_err_count[0].counter,
+		g->ecc.fb.mmu_hubtlb_ecc_uncorrected_err_count[0].counter);
+}
+
+static void gv11b_fb_intr_handle_ecc_fillunit(struct gk20a *g, u32 ecc_status)
+{
+	u32 ecc_addr, corrected_cnt, uncorrected_cnt;
+	u32 corrected_delta, uncorrected_delta;
+	u32 corrected_overflow, uncorrected_overflow;
+
+	ecc_addr = nvgpu_readl(g, fb_mmu_fillunit_ecc_address_r());
+	corrected_cnt = nvgpu_readl(g,
+		fb_mmu_fillunit_ecc_corrected_err_count_r());
+	uncorrected_cnt = nvgpu_readl(g,
+		fb_mmu_fillunit_ecc_uncorrected_err_count_r());
+
+	corrected_delta = fb_mmu_fillunit_ecc_corrected_err_count_total_v(
+							corrected_cnt);
+	uncorrected_delta = fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(
+							uncorrected_cnt);
+	corrected_overflow = ecc_status &
+		fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m();
+
+	uncorrected_overflow = ecc_status &
+		fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m();
+
+	/* clear the interrupt */
+	if ((corrected_delta > 0U) || (corrected_overflow != 0U)) {
+		nvgpu_writel(g, fb_mmu_fillunit_ecc_corrected_err_count_r(), 0);
+	}
+	if ((uncorrected_delta > 0U) || (uncorrected_overflow != 0U)) {
+		nvgpu_writel(g,
+			fb_mmu_fillunit_ecc_uncorrected_err_count_r(), 0);
+	}
+
+	nvgpu_writel(g, fb_mmu_fillunit_ecc_status_r(),
+				fb_mmu_fillunit_ecc_status_reset_clear_f());
+
+	/* Handle overflow */
+	if (corrected_overflow != 0U) {
+		corrected_delta +=
+			BIT32(fb_mmu_fillunit_ecc_corrected_err_count_total_s());
+	}
+	if (uncorrected_overflow != 0U) {
+		uncorrected_delta +=
+			BIT32(fb_mmu_fillunit_ecc_uncorrected_err_count_total_s());
+	}
+
+
+	g->ecc.fb.mmu_fillunit_ecc_corrected_err_count[0].counter +=
+							corrected_delta;
+	g->ecc.fb.mmu_fillunit_ecc_uncorrected_err_count[0].counter +=
+							uncorrected_delta;
+
+	if ((ecc_status &
+		fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m()) != 0U) {
+		nvgpu_hubmmu_report_ecc_error(g, 0,
+			GPU_HUBMMU_PTE_DATA_ECC_CORRECTED,
+			ecc_addr,
+			g->ecc.fb.mmu_fillunit_ecc_corrected_err_count[0].counter);
+		nvgpu_log(g, gpu_dbg_intr, "corrected ecc pte data error");
+	}
+	if ((ecc_status &
+		fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m())
+									!= 0U) {
+		nvgpu_hubmmu_report_ecc_error(g, 0,
+			GPU_HUBMMU_PTE_DATA_ECC_UNCORRECTED,
+			ecc_addr,
+			g->ecc.fb.mmu_fillunit_ecc_uncorrected_err_count[0].counter);
+		nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc pte data error");
+	}
+	if ((ecc_status &
+		fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m()) != 0U) {
+		nvgpu_hubmmu_report_ecc_error(g, 0,
+			GPU_HUBMMU_PDE0_DATA_ECC_CORRECTED,
+			ecc_addr,
+			g->ecc.fb.mmu_fillunit_ecc_corrected_err_count[0].counter);
+		nvgpu_log(g, gpu_dbg_intr, "corrected ecc pde0 data error");
+	}
+	if ((ecc_status &
+		fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m())
+									!= 0U) {
+		nvgpu_hubmmu_report_ecc_error(g, 0,
+			GPU_HUBMMU_PDE0_DATA_ECC_UNCORRECTED,
+			ecc_addr,
+			g->ecc.fb.mmu_fillunit_ecc_uncorrected_err_count[0].counter);
+		nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc pde0 data error");
+	}
+
+	if ((corrected_overflow != 0U) || (uncorrected_overflow != 0U)) {
+		nvgpu_info(g, "mmu fillunit ecc counter overflow!");
+	}
+
+	nvgpu_log(g, gpu_dbg_intr,
+		"ecc error address: 0x%x", ecc_addr);
+	nvgpu_log(g, gpu_dbg_intr,
+		"ecc error count corrected: %d, uncorrected %d",
+		g->ecc.fb.mmu_fillunit_ecc_corrected_err_count[0].counter,
+		g->ecc.fb.mmu_fillunit_ecc_uncorrected_err_count[0].counter);
+}
+
+void gv11b_fb_intr_handle_ecc(struct gk20a *g)
+{
+	u32 status;
+
+	nvgpu_info(g, "ecc uncorrected error notify");
+
+	status = nvgpu_readl(g, fb_mmu_l2tlb_ecc_status_r());
+	if (status != 0U) {
+		gv11b_fb_intr_handle_ecc_l2tlb(g, status);
+	}
+
+	status = nvgpu_readl(g, fb_mmu_hubtlb_ecc_status_r());
+	if (status != 0U) {
+		gv11b_fb_intr_handle_ecc_hubtlb(g, status);
+	}
+
+	status = nvgpu_readl(g, fb_mmu_fillunit_ecc_status_r());
+	if (status != 0U) {
+		gv11b_fb_intr_handle_ecc_fillunit(g, status);
+	}
+}
diff --git a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b.h b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b.h
new file mode 100644
index 000000000..9ecdce587
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b.h
@@ -0,0 +1,32 @@
+/*
+ * GV11B FB INTR ECC
+ *
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_FB_INTR_ECC_GV11B_H
+#define NVGPU_FB_INTR_ECC_GV11B_H
+
+struct gk20a;
+
+void gv11b_fb_intr_handle_ecc(struct gk20a *g);
+
+#endif /* NVGPU_FB_INTR_ECC_GV11B_H */
diff --git a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_gv100.c b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_gv100.c
new file mode 100644
index 000000000..c70ae9a72
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_gv100.c
@@ -0,0 +1,56 @@
+/*
+ * GV100 FB INTR
+ *
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+
+#include "fb_intr_gv100.h"
+
+#include <nvgpu/hw/gv100/hw_fb_gv100.h>
+
+void gv100_fb_intr_enable(struct gk20a *g)
+{
+	u32 mask;
+
+	mask = fb_niso_intr_en_set_mmu_other_fault_notify_m() |
+		fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m() |
+		fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m() |
+		fb_niso_intr_en_set_mmu_replayable_fault_notify_m() |
+		fb_niso_intr_en_set_mmu_replayable_fault_overflow_m();
+
+	nvgpu_writel(g, fb_niso_intr_en_set_r(0), mask);
+}
+
+void gv100_fb_intr_disable(struct gk20a *g)
+{
+	u32 mask;
+
+	mask = fb_niso_intr_en_set_mmu_other_fault_notify_m() |
+		fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m() |
+		fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m() |
+		fb_niso_intr_en_set_mmu_replayable_fault_notify_m() |
+		fb_niso_intr_en_set_mmu_replayable_fault_overflow_m();
+
+	nvgpu_writel(g, fb_niso_intr_en_clr_r(0), mask);
+}
diff --git a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_gv100.h b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_gv100.h
new file mode 100644
index 000000000..21e06ba01
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_gv100.h
@@ -0,0 +1,33 @@
+/*
+ * GV100 FB INTR
+ *
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_FB_INTR_GV100_H
+#define NVGPU_FB_INTR_GV100_H
+
+struct gk20a;
+
+void gv100_fb_intr_enable(struct gk20a *g);
+void gv100_fb_intr_disable(struct gk20a *g);
+
+#endif /* NVGPU_FB_INTR_GV100_H */
diff --git a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_gv11b.c b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_gv11b.c
new file mode 100644
index 000000000..1d3d31fd1
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_gv11b.c
@@ -0,0 +1,98 @@
+/*
+ * GV11B FB
+ *
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+
+#include "hal/fb/fb_gv11b.h"
+
+#include "fb_intr_gv11b.h"
+#include "fb_intr_ecc_gv11b.h"
+
+#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
+
+
+void gv11b_fb_intr_enable(struct gk20a *g)
+{
+	u32 mask;
+
+	mask = fb_niso_intr_en_set_mmu_other_fault_notify_m() |
+		fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m() |
+		fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m() |
+		fb_niso_intr_en_set_mmu_replayable_fault_notify_m() |
+		fb_niso_intr_en_set_mmu_replayable_fault_overflow_m() |
+		fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_m();
+
+	nvgpu_writel(g, fb_niso_intr_en_set_r(0), mask);
+}
+
+void gv11b_fb_intr_disable(struct gk20a *g)
+{
+	u32 mask;
+
+	mask = fb_niso_intr_en_set_mmu_other_fault_notify_m() |
+		fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m() |
+		fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m() |
+		fb_niso_intr_en_set_mmu_replayable_fault_notify_m() |
+		fb_niso_intr_en_set_mmu_replayable_fault_overflow_m() |
+		fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_m();
+
+	nvgpu_writel(g, fb_niso_intr_en_clr_r(0), mask);
+}
+
+void gv11b_fb_intr_isr(struct gk20a *g)
+{
+	u32 niso_intr;
+
+	nvgpu_mutex_acquire(&g->mm.hub_isr_mutex);
+
+	niso_intr = nvgpu_readl(g, fb_niso_intr_r());
+
+	nvgpu_log(g, gpu_dbg_intr, "enter hub isr, niso_intr = 0x%08x",
+			niso_intr);
+
+	if ((niso_intr &
+		 (fb_niso_intr_hub_access_counter_notify_m() |
+		  fb_niso_intr_hub_access_counter_error_m())) != 0U) {
+
+		nvgpu_info(g, "hub access counter notify/error");
+	}
+	if ((niso_intr &
+	     fb_niso_intr_mmu_ecc_uncorrected_error_notify_pending_f()) != 0U) {
+		gv11b_fb_intr_handle_ecc(g);
+	}
+	if ((niso_intr &
+		(fb_niso_intr_mmu_other_fault_notify_m() |
+		fb_niso_intr_mmu_replayable_fault_notify_m() |
+		fb_niso_intr_mmu_replayable_fault_overflow_m() |
+		fb_niso_intr_mmu_nonreplayable_fault_notify_m() |
+		fb_niso_intr_mmu_nonreplayable_fault_overflow_m())) != 0U) {
+
+		nvgpu_log(g, gpu_dbg_intr, "MMU Fault");
+		gv11b_fb_handle_mmu_fault(g, niso_intr);
+	}
+
+	nvgpu_mutex_release(&g->mm.hub_isr_mutex);
+}
diff --git a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_gv11b.h b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_gv11b.h
new file mode 100644
index 000000000..7d96f9ac5
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_gv11b.h
@@ -0,0 +1,34 @@
+/*
+ * GV11B FB INTR
+ *
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_FB_INTR_GV11B_H
+#define NVGPU_FB_INTR_GV11B_H
+
+struct gk20a;
+
+void gv11b_fb_intr_enable(struct gk20a *g);
+void gv11b_fb_intr_disable(struct gk20a *g);
+void gv11b_fb_intr_isr(struct gk20a *g);
+
+#endif /* NVGPU_FB_INTR_GV11B_H */
diff --git a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_tu104.c b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_tu104.c
new file mode 100644
index 000000000..d89853e6f
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_tu104.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+
+#include "hal/fb/fb_tu104.h"
+#include "hal/mc/mc_tu104.h"
+
+#include "fb_intr_ecc_gv11b.h"
+#include "fb_intr_tu104.h"
+
+#include "nvgpu/hw/tu104/hw_fb_tu104.h"
+
+void tu104_fb_intr_enable(struct gk20a *g)
+{
+	u32 info_fault = nvgpu_readl(g, fb_mmu_int_vector_info_fault_r());
+	u32 nonreplay_fault = nvgpu_readl(g,
+		fb_mmu_int_vector_fault_r(
+				NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX));
+	u32 replay_fault = nvgpu_readl(g,
+		fb_mmu_int_vector_fault_r(NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX));
+	u32 ecc_error = nvgpu_readl(g, fb_mmu_int_vector_ecc_error_r());
+
+	intr_tu104_vector_en_set(g,
+		fb_mmu_int_vector_info_fault_vector_v(info_fault));
+	intr_tu104_vector_en_set(g,
+		fb_mmu_int_vector_fault_notify_v(nonreplay_fault));
+	intr_tu104_vector_en_set(g,
+		fb_mmu_int_vector_fault_error_v(nonreplay_fault));
+	intr_tu104_vector_en_set(g,
+		fb_mmu_int_vector_fault_notify_v(replay_fault));
+	intr_tu104_vector_en_set(g,
+		fb_mmu_int_vector_fault_error_v(replay_fault));
+	intr_tu104_vector_en_set(g,
+		fb_mmu_int_vector_ecc_error_vector_v(ecc_error));
+}
+
+void tu104_fb_intr_disable(struct gk20a *g)
+{
+	u32 info_fault = nvgpu_readl(g, fb_mmu_int_vector_info_fault_r());
+	u32 nonreplay_fault = nvgpu_readl(g,
+		fb_mmu_int_vector_fault_r(
+				NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX));
+	u32 replay_fault = nvgpu_readl(g,
+		fb_mmu_int_vector_fault_r(NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX));
+	u32 ecc_error = nvgpu_readl(g, fb_mmu_int_vector_ecc_error_r());
+
+	intr_tu104_vector_en_clear(g,
+		fb_mmu_int_vector_info_fault_vector_v(info_fault));
+	intr_tu104_vector_en_clear(g,
+		fb_mmu_int_vector_fault_notify_v(nonreplay_fault));
+	intr_tu104_vector_en_clear(g,
+		fb_mmu_int_vector_fault_error_v(nonreplay_fault));
+	intr_tu104_vector_en_clear(g,
+		fb_mmu_int_vector_fault_notify_v(replay_fault));
+	intr_tu104_vector_en_clear(g,
+		fb_mmu_int_vector_fault_error_v(replay_fault));
+	intr_tu104_vector_en_clear(g,
+		fb_mmu_int_vector_ecc_error_vector_v(ecc_error));
+}
+
+void tu104_fb_intr_isr(struct gk20a *g)
+{
+	u32 info_fault = nvgpu_readl(g, fb_mmu_int_vector_info_fault_r());
+	u32 nonreplay_fault = nvgpu_readl(g,
+		fb_mmu_int_vector_fault_r(
+				NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX));
+	u32 replay_fault = nvgpu_readl(g,
+		fb_mmu_int_vector_fault_r(NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX));
+	u32 ecc_error = nvgpu_readl(g, fb_mmu_int_vector_ecc_error_r());
+
+	nvgpu_mutex_acquire(&g->mm.hub_isr_mutex);
+
+	if (intr_tu104_vector_intr_pending(g,
+			fb_mmu_int_vector_ecc_error_vector_v(ecc_error))) {
+		gv11b_fb_intr_handle_ecc(g);
+	}
+
+	if (intr_tu104_vector_intr_pending(g,
+			fb_mmu_int_vector_fault_notify_v(replay_fault)) ||
+	    intr_tu104_vector_intr_pending(g,
+			fb_mmu_int_vector_fault_error_v(replay_fault)) ||
+	    intr_tu104_vector_intr_pending(g,
+			fb_mmu_int_vector_fault_notify_v(nonreplay_fault)) ||
+	    intr_tu104_vector_intr_pending(g,
+			fb_mmu_int_vector_fault_error_v(nonreplay_fault)) ||
+	    intr_tu104_vector_intr_pending(g,
+			fb_mmu_int_vector_info_fault_vector_v(info_fault))) {
+		nvgpu_log(g, gpu_dbg_intr, "MMU Fault");
+		tu104_fb_handle_mmu_fault(g);
+	}
+
+	nvgpu_mutex_release(&g->mm.hub_isr_mutex);
+}
diff --git a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_tu104.h b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_tu104.h
new file mode 100644
index 000000000..8b504cc83
--- /dev/null
+++ b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_tu104.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_FB_INTR_TU104_H
+#define NVGPU_FB_INTR_TU104_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+void tu104_fb_intr_enable(struct gk20a *g);
+void tu104_fb_intr_disable(struct gk20a *g);
+void tu104_fb_intr_isr(struct gk20a *g);
+
+#endif /* NVGPU_FB_INTR_TU104_H */
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gp10b.c b/drivers/gpu/nvgpu/hal/mc/mc_gp10b.c
index 5888684b5..19b4d854d 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gp10b.c
@@ -125,7 +125,7 @@ void mc_gp10b_isr_stall(struct gk20a *g)
 	}
 	if ((g->ops.mc.is_intr_hub_pending != NULL) &&
 		 g->ops.mc.is_intr_hub_pending(g, mc_intr_0)) {
-		g->ops.fb.hub_isr(g);
+		g->ops.fb.intr.isr(g);
 	}
 	if ((mc_intr_0 & mc_intr_pfifo_pending_f()) != 0U) {
 		g->ops.fifo.intr_0_isr(g);
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_tu104.c b/drivers/gpu/nvgpu/hal/mc/mc_tu104.c
index 30adeef46..5630139d1 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_tu104.c
+++ b/drivers/gpu/nvgpu/hal/mc/mc_tu104.c
@@ -349,7 +349,7 @@ void intr_tu104_stall_pause(struct gk20a *g)
 {
 	mc_gp10b_intr_stall_pause(g);
 
-	g->ops.fb.disable_hub_intr(g);
+	g->ops.fb.intr.disable(g);
 }
 
 /* resume all stall interrupts */
@@ -357,7 +357,7 @@ void intr_tu104_stall_resume(struct gk20a *g)
 {
 	mc_gp10b_intr_stall_resume(g);
 
-	g->ops.fb.enable_hub_intr(g);
+	g->ops.fb.intr.enable(g);
 }
 
 void intr_tu104_log_pending_intrs(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 9aaaa46ca..3f17fb6a6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -870,13 +870,10 @@ struct gpu_ops {
 		bool (*is_debug_mode_enabled)(struct gk20a *g);
 		void (*set_debug_mode)(struct gk20a *g, bool enable);
 		int (*tlb_invalidate)(struct gk20a *g, struct nvgpu_mem *pdb);
-		void (*hub_isr)(struct gk20a *g);
 		void (*handle_replayable_fault)(struct gk20a *g);
 		int (*mem_unlock)(struct gk20a *g);
 		int (*init_nvlink)(struct gk20a *g);
 		int (*enable_nvlink)(struct gk20a *g);
-		void (*enable_hub_intr)(struct gk20a *g);
-		void (*disable_hub_intr)(struct gk20a *g);
 		int (*init_fbpa)(struct gk20a *g);
 		void (*handle_fbpa_intr)(struct gk20a *g, u32 fbpa_id);
 		void (*write_mmu_fault_buffer_lo_hi)(struct gk20a *g, u32 index,
@@ -910,6 +907,11 @@ struct gpu_ops {
 					u32 err_id, u64 err_addr,
 					u64 err_cnt);
 		} err_ops;
+		struct {
+			void (*enable)(struct gk20a *g);
+			void (*disable)(struct gk20a *g);
+			void (*isr)(struct gk20a *g);
+		} intr;
 	} fb;
 	struct {
 		u32 (*falcon_base_addr)(void);
diff --git a/drivers/gpu/nvgpu/libnvgpu-drv.export b/drivers/gpu/nvgpu/libnvgpu-drv.export
index 0cc62a998..4c307ff42 100644
--- a/drivers/gpu/nvgpu/libnvgpu-drv.export
+++ b/drivers/gpu/nvgpu/libnvgpu-drv.export
@@ -42,7 +42,7 @@ gp10b_mm_get_mmu_levels
 gp10b_ramin_init_pdb
 gp10b_remove_bar2_vm
 gv11b_channel_count
-gv11b_fb_enable_hub_intr
+gv11b_fb_intr_enable
 gv11b_fb_fault_buf_configure_hw
 gv11b_fb_fault_buf_set_state_hw
 gv11b_fb_init_hw
diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c
index 36a4b41c2..b6fdb0942 100644
--- a/drivers/gpu/nvgpu/tu104/hal_tu104.c
+++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c
@@ -52,6 +52,7 @@
 #include "hal/fb/fb_gv11b.h"
 #include "hal/fb/fb_gv100.h"
 #include "hal/fb/fb_tu104.h"
+#include "hal/fb/intr/fb_intr_tu104.h"
 #include "hal/fuse/fuse_gm20b.h"
 #include "hal/fuse/fuse_gp10b.h"
 #include "hal/fuse/fuse_gp106.h"
@@ -833,13 +834,10 @@ static const struct gpu_ops tu104_ops = {
 		.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
 		.set_debug_mode = gm20b_fb_set_debug_mode,
 		.tlb_invalidate = fb_tu104_tlb_invalidate,
-		.hub_isr = tu104_fb_hub_isr,
 		.handle_replayable_fault = gv11b_fb_handle_replayable_mmu_fault,
 		.mem_unlock = gv100_fb_memory_unlock,
 		.init_nvlink = gv100_fb_init_nvlink,
 		.enable_nvlink = gv100_fb_enable_nvlink,
-		.enable_hub_intr = tu104_fb_enable_hub_intr,
-		.disable_hub_intr = tu104_fb_disable_hub_intr,
 		.init_fbpa = tu104_fbpa_init,
 		.handle_fbpa_intr = tu104_fbpa_handle_intr,
 		.write_mmu_fault_buffer_lo_hi =
@@ -866,6 +864,11 @@ static const struct gpu_ops tu104_ops = {
 		.fault_buf_configure_hw = gv11b_fb_fault_buf_configure_hw,
 		.get_vidmem_size = tu104_fb_get_vidmem_size,
 		.apply_pdb_cache_war = tu104_fb_apply_pdb_cache_war,
+		.intr = {
+			.enable = tu104_fb_intr_enable,
+			.disable = tu104_fb_intr_disable,
+			.isr = tu104_fb_intr_isr,
+		}
 	},
 	.nvdec = {
 		.falcon_base_addr = tu104_nvdec_falcon_base_addr,
diff --git a/userspace/units/mm/page_table_faults/page_table_faults.c b/userspace/units/mm/page_table_faults/page_table_faults.c
index 9005f24e3..a0ce8c053 100644
--- a/userspace/units/mm/page_table_faults/page_table_faults.c
+++ b/userspace/units/mm/page_table_faults/page_table_faults.c
@@ -47,6 +47,7 @@
 #include "hal/fb/fb_gm20b.h"
 #include "hal/fb/fb_gv11b.h"
 #include "hal/fifo/ramin_gk20a.h"
+#include "hal/fb/intr/fb_intr_gv11b.h"
 #include "hal/fifo/ramin_gm20b.h"
 #include "hal/fifo/ramin_gp10b.h"
 
@@ -133,7 +134,7 @@ static int init_mm(struct unit_module *m, struct gk20a *g)
 	g->ops.mm.init_mm_setup_hw = gv11b_init_mm_setup_hw;
 	g->ops.mm.l2_flush = gv11b_mm_l2_flush;
 	g->ops.fb.init_hw = gv11b_fb_init_hw;
-	g->ops.fb.enable_hub_intr = gv11b_fb_enable_hub_intr;
+	g->ops.fb.intr.enable = gv11b_fb_intr_enable;
 	g->ops.fb.fault_buf_configure_hw = gv11b_fb_fault_buf_configure_hw;
 	g->ops.fb.read_mmu_fault_buffer_size =
 		fb_gv11b_read_mmu_fault_buffer_size;