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gpu: nvgpu: ACR interface headers reorganization

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-Moved ACR interface headers from acr_gm20b.h/acr_gp106.h to
Its specific header files under “drivers/gpu/nvgpu/include/nvgpu/acr/”
Folder.

- nvgpu_acr.h - Top-level header-file which include ACR interfaces
headers & defines required to communicate with ACR, including this
header file is good to get access into ACR interface & made changes
accordingly,

-Deleted acr.h & acr_t18x.h as not required anymore
& removed its include from dependent files.

Jira NVGPU-19

Change-Id: Ie404043cfe1ab32404eb63a43831f470d8436324
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1304748
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2017-02-14 22:47:29 +05:30
committed by mobile promotions
parent 8cdb91c527
commit 9c68af58a9
14 changed files with 597 additions and 548 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/gpu/nvgpu/acr_t18x.h
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@@ -1,20 +0,0 @@
/*
* NVIDIA T18x ACR
*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _NVGPU_ACR_T18X_H_
#define _NVGPU_ACR_T18X_H_
#include "gp106/acr_gp106.h"
#endif

3
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -38,6 +38,8 @@ struct acr_desc;
#include "../../../arch/arm/mach-tegra/iomap.h"
#include <nvgpu/acr/nvgpu_acr.h>
#include "as_gk20a.h"
#include "clk_gk20a.h"
#include "ce2_gk20a.h"
@@ -50,7 +52,6 @@ struct acr_desc;
#include "therm_gk20a.h"
#include "platform_gk20a.h"
#include "gm20b/acr_gm20b.h"
#include "acr.h"
#include "cde_gk20a.h"
#include "debug_gk20a.h"
#include "sched_gk20a.h"

3
drivers/gpu/nvgpu/gm20b/acr_gm20b.c
View File

@@ -23,9 +23,12 @@
#include <nvgpu/timers.h>
#include <nvgpu/nvgpu_common.h>
#include <nvgpu/acr/nvgpu_acr.h>
#include "gk20a/gk20a.h"
#include "gk20a/pmu_gk20a.h"
#include "mm_gm20b.h"
#include "acr_gm20b.h"
#include <nvgpu/hw/gm20b/hw_pwr_gm20b.h>

370
drivers/gpu/nvgpu/gm20b/acr_gm20b.h
View File

@@ -1,7 +1,7 @@
/*
* GM20B ACR
*
* Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -15,15 +15,6 @@
#ifndef __ACR_GM20B_H_
#define __ACR_GM20B_H_
#include "gk20a/gk20a.h"
#include "mm_gm20b.h"
/*Defines*/
#define ACR_COMPLETION_TIMEOUT_MS 10000 /*in msec */
/*chip specific defines*/
#define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/
#define LSF_UCODE_DATA_ALIGNMENT 4096
#define GM20B_PMU_UCODE_IMAGE "gpmu_ucode_image.bin"
#define GM20B_PMU_UCODE_DESC "gpmu_ucode_desc.bin"
@@ -33,365 +24,6 @@
#define GM20B_FECS_UCODE_SIG "fecs_sig.bin"
#define T18x_GPCCS_UCODE_SIG "gpccs_sig.bin"
#define LSFM_DISABLE_MASK_NONE (0x00000000) /*Disable all LS falcons*/
#define LSFM_DISABLE_MASK_ALL (0xFFFFFFFF) /*Enable all LS falcons*/
#define PMU_SECURE_MODE (0x1)
#define PMU_LSFM_MANAGED (0x2)
/*ACR load related*/
/*!
* Supporting maximum of 2 regions.
* This is needed to pre-allocate space in DMEM
*/
#define T210_FLCN_ACR_MAX_REGIONS (2)
#define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200)
/*!
* Falcon Id Defines
* Defines a common Light Secure Falcon identifier.
*/
#define LSF_FALCON_ID_PMU (0)
#define LSF_FALCON_ID_RESERVED (1)
#define LSF_FALCON_ID_FECS (2)
#define LSF_FALCON_ID_GPCCS (3)
#define LSF_FALCON_ID_END (11)
#define LSF_FALCON_ID_INVALID (0xFFFFFFFF)
/*!
* Bootstrap Owner Defines
*/
#define LSF_BOOTSTRAP_OWNER_DEFAULT (LSF_FALCON_ID_PMU)
/*!
* Image Status Defines
*/
#define LSF_IMAGE_STATUS_NONE (0)
#define LSF_IMAGE_STATUS_COPY (1)
#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2)
#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3)
#define LSF_IMAGE_STATUS_VALIDATION_DONE (4)
#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5)
#define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6)
/*LSB header related defines*/
#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0
#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE 1
#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0
#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE 4
#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE 8
#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0
/*!
* Light Secure WPR Content Alignments
*/
#define LSF_LSB_HEADER_ALIGNMENT 256
#define LSF_BL_DATA_ALIGNMENT 256
#define LSF_BL_DATA_SIZE_ALIGNMENT 256
#define LSF_BL_CODE_SIZE_ALIGNMENT 256
/*!
* Falcon UCODE header index.
*/
#define FLCN_NL_UCODE_HDR_OS_CODE_OFF_IND (0)
#define FLCN_NL_UCODE_HDR_OS_CODE_SIZE_IND (1)
#define FLCN_NL_UCODE_HDR_OS_DATA_OFF_IND (2)
#define FLCN_NL_UCODE_HDR_OS_DATA_SIZE_IND (3)
#define FLCN_NL_UCODE_HDR_NUM_APPS_IND (4)
/*!
* There are total N number of Apps with code and offset defined in UCODE header
* This macro provides the CODE and DATA offset and size of Ath application.
*/
#define FLCN_NL_UCODE_HDR_APP_CODE_START_IND (5)
#define FLCN_NL_UCODE_HDR_APP_CODE_OFF_IND(N, A) \
(FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2))
#define FLCN_NL_UCODE_HDR_APP_CODE_SIZE_IND(N, A) \
(FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2) + 1)
#define FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) \
(FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (N*2) - 1)
#define FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) \
(FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) + 1)
#define FLCN_NL_UCODE_HDR_APP_DATA_OFF_IND(N, A) \
(FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2))
#define FLCN_NL_UCODE_HDR_APP_DATA_SIZE_IND(N, A) \
(FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2) + 1)
#define FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) \
(FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (N*2) - 1)
#define FLCN_NL_UCODE_HDR_OS_OVL_OFF_IND(N) \
(FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 1)
#define FLCN_NL_UCODE_HDR_OS_OVL_SIZE_IND(N) \
(FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 2)
enum acr_capabilities {
ACR_LRF_TEX_LTC_DRAM_PRIV_MASK_ENABLE_LS_OVERRIDE = (0x00000001),
};
/*Externs*/
/*Structs*/
/*!
* Light Secure Falcon Ucode Description Defines
* This stucture is prelim and may change as the ucode signing flow evolves.
*/
struct lsf_ucode_desc {
u8 prd_keys[2][16];
u8 dbg_keys[2][16];
u32 b_prd_present;
u32 b_dbg_present;
u32 falcon_id;
};
/*!
* Light Secure WPR Header
* Defines state allowing Light Secure Falcon bootstrapping.
*
* falcon_id - LS falcon ID
* lsb_offset - Offset into WPR region holding LSB header
* bootstrap_owner - Bootstrap OWNER (either PMU or SEC2)
* lazy_bootstrap - Skip bootstrapping by ACR
* status - Bootstrapping status
*/
struct lsf_wpr_header {
u32 falcon_id;
u32 lsb_offset;
u32 bootstrap_owner;
u32 lazy_bootstrap;
u32 status;
};
struct lsf_lsb_header {
struct lsf_ucode_desc signature;
u32 ucode_off;
u32 ucode_size;
u32 data_size;
u32 bl_code_size;
u32 bl_imem_off;
u32 bl_data_off;
u32 bl_data_size;
u32 app_code_off;
u32 app_code_size;
u32 app_data_off;
u32 app_data_size;
u32 flags;
};
/*!
* Structure used by the boot-loader to load the rest of the code. This has
* to be filled by host and copied into DMEM at offset provided in the
* hsflcn_bl_desc.bl_desc_dmem_load_off.
*
* signature - 16B signature for secure code. 0s if no secure code
* ctx_dma - CtxDma to be used by BL while loading code/data
* code_dma_base - 256B aligned Physical FB Address where code is located
* non_sec_code_off - Offset from code_dma_base where the nonSecure code is
* located. The offset must be multiple of 256 to help perf
* non_sec_code_size - The size of the nonSecure code part.
* sec_code_size - Offset from code_dma_base where the secure code is
* located. The offset must be multiple of 256 to help perf
* code_entry_point - Code entry point which will be invoked by BL after
* code is loaded.
* data_dma_base - 256B aligned Physical FB Address where data is located.
* data_size - Size of data block. Should be multiple of 256B
*/
struct flcn_bl_dmem_desc {
u32 reserved[4]; /*Should be the first element..*/
u32 signature[4]; /*Should be the first element..*/
u32 ctx_dma;
u32 code_dma_base;
u32 non_sec_code_off;
u32 non_sec_code_size;
u32 sec_code_off;
u32 sec_code_size;
u32 code_entry_point;
u32 data_dma_base;
u32 data_size;
u32 code_dma_base1;
u32 data_dma_base1;
};
/*!
* Legacy structure used by the current PMU/DPU bootloader.
*/
struct loader_config {
u32 dma_idx;
u32 code_dma_base; /*<! upper 32-bits of 40-bit dma address*/
u32 code_size_total;
u32 code_size_to_load;
u32 code_entry_point;
u32 data_dma_base; /*<! upper 32-bits of 40-bit dma address*/
u32 data_size; /*<! initialized data of the application */
u32 overlay_dma_base; /*<! upper 32-bits of the 40-bit dma address*/
u32 argc;
u32 argv;
u16 code_dma_base1; /*<! upper 7 bits of 47-bit dma address*/
u16 data_dma_base1; /*<! upper 7 bits of 47-bit dma address*/
u16 overlay_dma_base1; /*<! upper 7 bits of the 47-bit dma address*/
};
/*!
* Union of all supported structures used by bootloaders.
*/
union flcn_bl_generic_desc {
struct flcn_bl_dmem_desc bl_dmem_desc;
struct loader_config loader_cfg;
};
struct flcn_ucode_img {
u32 *header; /*only some falcons have header*/
u32 *data;
struct pmu_ucode_desc *desc; /*only some falcons have descriptor*/
u32 data_size;
void *fw_ver; /*NV2080_CTRL_GPU_GET_FIRMWARE_VERSION_PARAMS struct*/
u8 load_entire_os_data; /* load the whole osData section at boot time.*/
struct lsf_ucode_desc *lsf_desc; /* NULL if not a light secure falcon.*/
u8 free_res_allocs;/*True if there a resources to freed by the client.*/
u32 flcn_inst;
};
/*!
* LSFM Managed Ucode Image
* next : Next image the list, NULL if last.
* wpr_header : WPR header for this ucode image
* lsb_header : LSB header for this ucode image
* bl_gen_desc : Bootloader generic desc structure for this ucode image
* bl_gen_desc_size : Sizeof bootloader desc structure for this ucode image
* full_ucode_size : Surface size required for final ucode image
* ucode_img : Ucode image info
*/
struct lsfm_managed_ucode_img {
struct lsfm_managed_ucode_img *next;
struct lsf_wpr_header wpr_header;
struct lsf_lsb_header lsb_header;
union flcn_bl_generic_desc bl_gen_desc;
u32 bl_gen_desc_size;
u32 full_ucode_size;
struct flcn_ucode_img ucode_img;
};
struct ls_flcn_mgr {
u16 managed_flcn_cnt;
u32 wpr_size;
u32 disable_mask;
struct lsfm_managed_ucode_img *ucode_img_list;
void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/
};
/*ACR related structs*/
/*!
* start_addr - Starting address of region
* end_addr - Ending address of region
* region_id - Region ID
* read_mask - Read Mask
* write_mask - WriteMask
* client_mask - Bit map of all clients currently using this region
*/
struct flcn_acr_region_prop {
u32 start_addr;
u32 end_addr;
u32 region_id;
u32 read_mask;
u32 write_mask;
u32 client_mask;
};
/*!
* no_regions - Number of regions used.
* region_props - Region properties
*/
struct flcn_acr_regions {
u32 no_regions;
struct flcn_acr_region_prop region_props[T210_FLCN_ACR_MAX_REGIONS];
};
/*!
* reserved_dmem-When the bootstrap owner has done bootstrapping other falcons,
* and need to switch into LS mode, it needs to have its own
* actual DMEM image copied into DMEM as part of LS setup. If
* ACR desc is at location 0, it will definitely get overwritten
* causing data corruption. Hence we are reserving 0x200 bytes
* to give room for any loading data. NOTE: This has to be the
* first member always
* signature - Signature of ACR ucode.
* wpr_region_id - Region ID holding the WPR header and its details
* wpr_offset - Offset from the WPR region holding the wpr header
* regions - Region descriptors
* nonwpr_ucode_blob_start -stores non-WPR start where kernel stores ucode blob
* nonwpr_ucode_blob_end -stores non-WPR end where kernel stores ucode blob
*/
struct flcn_acr_desc {
union {
u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)];
u32 signatures[4];
} ucode_reserved_space;
/*Always 1st*/
u32 wpr_region_id;
u32 wpr_offset;
u32 mmu_mem_range;
struct flcn_acr_regions regions;
u32 nonwpr_ucode_blob_size;
u64 nonwpr_ucode_blob_start;
};
/*!
* The header used by RM to figure out code and data sections of bootloader.
*
* bl_code_off - Offset of code section in the image
* bl_code_size - Size of code section in the image
* bl_data_off - Offset of data section in the image
* bl_data_size - Size of data section in the image
*/
struct hsflcn_bl_img_hdr {
u32 bl_code_off;
u32 bl_code_size;
u32 bl_data_off;
u32 bl_data_size;
};
/*!
* The descriptor used by RM to figure out the requirements of boot loader.
*
* bl_start_tag - Starting tag of bootloader
* bl_desc_dmem_load_off - Dmem offset where _def_rm_flcn_bl_dmem_desc
to be loaded
* bl_img_hdr - Description of the image
*/
struct hsflcn_bl_desc {
u32 bl_start_tag;
u32 bl_desc_dmem_load_off;
struct hsflcn_bl_img_hdr bl_img_hdr;
};
struct bin_hdr {
u32 bin_magic; /* 0x10de */
u32 bin_ver; /* versioning of bin format */
u32 bin_size; /* entire image size including this header */
u32 header_offset; /* Header offset of executable binary metadata,
start @ offset- 0x100 */
u32 data_offset; /* Start of executable binary data, start @
offset- 0x200 */
u32 data_size; /* Size ofexecutable binary */
};
struct acr_fw_header {
u32 sig_dbg_offset;
u32 sig_dbg_size;
u32 sig_prod_offset;
u32 sig_prod_size;
u32 patch_loc;
u32 patch_sig;
u32 hdr_offset; /*this header points to acr_ucode_header_t210_load*/
u32 hdr_size; /*size of above header*/
};
struct wpr_carveout_info {
u64 wpr_base;
u64 nonwpr_base;
u64 size;
};
void gm20b_init_secure_pmu(struct gpu_ops *gops);
int prepare_ucode_blob(struct gk20a *g);
int gm20b_pmu_setup_sw(struct gk20a *g);

1
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
View File

@@ -27,7 +27,6 @@
#include "gr_gm20b.h"
#include "pmu_gm20b.h"
#include "acr_gm20b.h"
#include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
#include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>

6
drivers/gpu/nvgpu/gp106/acr_gp106.c
View File

@@ -19,9 +19,13 @@
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <nvgpu/nvgpu_common.h>
#include <nvgpu/acr/nvgpu_acr.h>
#include "gk20a/gk20a.h"
#include "gk20a/pmu_gk20a.h"
#include "gm20b/mm_gm20b.h"
#include "gm20b/acr_gm20b.h"
#include "gp106/acr_gp106.h"
#include "gp106/pmu_gp106.h"
@@ -29,8 +33,6 @@
#include "sec2_gp106.h"
#include "nvgpu_gpuid_t18x.h"
#include <nvgpu/nvgpu_common.h>
#include <nvgpu/hw/gp106/hw_psec_gp106.h>
#include <nvgpu/hw/gp106/hw_pwr_gp106.h>

141
drivers/gpu/nvgpu/gp106/acr_gp106.h
View File

@@ -14,152 +14,11 @@
#ifndef __ACR_GP106_H_
#define __ACR_GP106_H_
#include "gm20b/acr_gm20b.h"
#define GP106_FECS_UCODE_SIG "gp106/fecs_sig.bin"
#define GP106_GPCCS_UCODE_SIG "gp106/gpccs_sig.bin"
#define GP104_FECS_UCODE_SIG "gp104/fecs_sig.bin"
#define GP104_GPCCS_UCODE_SIG "gp104/gpccs_sig.bin"
struct loader_config_v1 {
u32 reserved;
u32 dma_idx;
struct falc_u64 code_dma_base;
u32 code_size_total;
u32 code_size_to_load;
u32 code_entry_point;
struct falc_u64 data_dma_base;
u32 data_size;
struct falc_u64 overlay_dma_base;
u32 argc;
u32 argv;
};
struct flcn_bl_dmem_desc_v1 {
u32 reserved[4]; /*Should be the first element..*/
u32 signature[4]; /*Should be the first element..*/
u32 ctx_dma;
struct falc_u64 code_dma_base;
u32 non_sec_code_off;
u32 non_sec_code_size;
u32 sec_code_off;
u32 sec_code_size;
u32 code_entry_point;
struct falc_u64 data_dma_base;
u32 data_size;
u32 argc;
u32 argv;
};
/*!
* Union of all supported structures used by bootloaders.
*/
union flcn_bl_generic_desc_v1 {
struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1;
struct loader_config_v1 loader_cfg_v1;
};
struct lsf_ucode_desc_v1 {
u8 prd_keys[2][16];
u8 dbg_keys[2][16];
u32 b_prd_present;
u32 b_dbg_present;
u32 falcon_id;
u32 bsupports_versioning;
u32 version;
u32 dep_map_count;
u8 dep_map[LSF_FALCON_ID_END * 2 * 4];
u8 kdf[16];
};
struct lsf_wpr_header_v1 {
u32 falcon_id;
u32 lsb_offset;
u32 bootstrap_owner;
u32 lazy_bootstrap;
u32 bin_version;
u32 status;
};
struct lsf_lsb_header_v1 {
struct lsf_ucode_desc_v1 signature;
u32 ucode_off;
u32 ucode_size;
u32 data_size;
u32 bl_code_size;
u32 bl_imem_off;
u32 bl_data_off;
u32 bl_data_size;
u32 app_code_off;
u32 app_code_size;
u32 app_data_off;
u32 app_data_size;
u32 flags;
};
struct flcn_ucode_img_v1 {
u32 *header; /*only some falcons have header*/
u32 *data;
struct pmu_ucode_desc_v1 *desc; /*only some falcons have descriptor*/
u32 data_size;
void *fw_ver; /*NV2080_CTRL_GPU_GET_FIRMWARE_VERSION_PARAMS struct*/
u8 load_entire_os_data; /* load the whole osData section at boot time.*/
struct lsf_ucode_desc_v1 *lsf_desc; /* NULL if not a light secure falcon.*/
u8 free_res_allocs;/*True if there a resources to freed by the client.*/
u32 flcn_inst;
};
struct lsfm_managed_ucode_img_v2 {
struct lsfm_managed_ucode_img_v2 *next;
struct lsf_wpr_header_v1 wpr_header;
struct lsf_lsb_header_v1 lsb_header;
union flcn_bl_generic_desc_v1 bl_gen_desc;
u32 bl_gen_desc_size;
u32 full_ucode_size;
struct flcn_ucode_img_v1 ucode_img;
};
struct ls_flcn_mgr_v1 {
u16 managed_flcn_cnt;
u32 wpr_size;
u32 disable_mask;
struct lsfm_managed_ucode_img_v2 *ucode_img_list;
void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/
};
struct flcn_acr_region_prop_v1 {
u32 start_addr;
u32 end_addr;
u32 region_id;
u32 read_mask;
u32 write_mask;
u32 client_mask;
u32 shadowmMem_startaddress;
};
/*!
* no_regions - Number of regions used.
* region_props - Region properties
*/
struct flcn_acr_regions_v1 {
u32 no_regions;
struct flcn_acr_region_prop_v1 region_props[T210_FLCN_ACR_MAX_REGIONS];
};
struct flcn_acr_desc_v1 {
union {
u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)];
} ucode_reserved_space;
u32 signatures[4];
/*Always 1st*/
u32 wpr_region_id;
u32 wpr_offset;
u32 mmu_mem_range;
struct flcn_acr_regions_v1 regions;
u32 nonwpr_ucode_blob_size;
u64 nonwpr_ucode_blob_start;
u32 dummy[4]; //ACR_BSI_VPR_DESC
};
void gp106_init_secure_pmu(struct gpu_ops *gops);
#endif /*__PMU_GP106_H_*/

2
drivers/gpu/nvgpu/gp106/sec2_gp106.c
View File

@@ -22,10 +22,8 @@
#include "gp10b/pmu_gp10b.h"
#include "gp106/pmu_gp106.h"
#include "gp106/acr_gp106.h"
#include "sec2_gp106.h"
#include "acr.h"
#include <nvgpu/hw/gp106/hw_mc_gp106.h>
#include <nvgpu/hw/gp106/hw_pwr_gp106.h>

2
drivers/gpu/nvgpu/gp10b/mm_gp10b.c
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@@ -17,7 +17,7 @@
#include <linux/dma-mapping.h>
#include "gk20a/gk20a.h"
#include "gm20b/mm_gm20b.h"
#include "mm_gp10b.h"
#include "rpfb_gp10b.h"

135
drivers/gpu/nvgpu/include/nvgpu/acr/acr_flcnbl.h Normal file
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@@ -0,0 +1,135 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __ACR_FLCNBL_H__
#define __ACR_FLCNBL_H__
#include <nvgpu/flcnif_cmn.h>
#ifndef __NVGPU_ACR_H__
#warning "acr_flcnbl.h not included from nvgpu_acr.h!" \
"Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces"
#endif
/*
* Structure used by the boot-loader to load the rest of the code. This has
* to be filled by NVGPU and copied into DMEM at offset provided in the
* hsflcn_bl_desc.bl_desc_dmem_load_off.
*/
struct flcn_bl_dmem_desc {
u32 reserved[4]; /*Should be the first element..*/
u32 signature[4]; /*Should be the first element..*/
u32 ctx_dma;
u32 code_dma_base;
u32 non_sec_code_off;
u32 non_sec_code_size;
u32 sec_code_off;
u32 sec_code_size;
u32 code_entry_point;
u32 data_dma_base;
u32 data_size;
u32 code_dma_base1;
u32 data_dma_base1;
};
struct flcn_bl_dmem_desc_v1 {
u32 reserved[4]; /*Should be the first element..*/
u32 signature[4]; /*Should be the first element..*/
u32 ctx_dma;
struct falc_u64 code_dma_base;
u32 non_sec_code_off;
u32 non_sec_code_size;
u32 sec_code_off;
u32 sec_code_size;
u32 code_entry_point;
struct falc_u64 data_dma_base;
u32 data_size;
u32 argc;
u32 argv;
};
/*
* The header used by NVGPU to figure out code and data sections of bootloader
*
* bl_code_off - Offset of code section in the image
* bl_code_size - Size of code section in the image
* bl_data_off - Offset of data section in the image
* bl_data_size - Size of data section in the image
*/
struct flcn_bl_img_hdr {
u32 bl_code_off;
u32 bl_code_size;
u32 bl_data_off;
u32 bl_data_size;
};
/*
* The descriptor used by NVGPU to figure out the requirements of bootloader
*
* bl_start_tag - Starting tag of bootloader
* bl_desc_dmem_load_off - Dmem offset where _def_rm_flcn_bl_dmem_desc
* to be loaded
* bl_img_hdr - Description of the image
*/
struct hsflcn_bl_desc {
u32 bl_start_tag;
u32 bl_desc_dmem_load_off;
struct flcn_bl_img_hdr bl_img_hdr;
};
/*
* Legacy structure used by the current PMU/DPU bootloader.
*/
struct loader_config {
u32 dma_idx;
u32 code_dma_base; /* upper 32-bits of 40-bit dma address */
u32 code_size_total;
u32 code_size_to_load;
u32 code_entry_point;
u32 data_dma_base; /* upper 32-bits of 40-bit dma address */
u32 data_size; /* initialized data of the application */
u32 overlay_dma_base; /* upper 32-bits of the 40-bit dma address */
u32 argc;
u32 argv;
u16 code_dma_base1; /* upper 7 bits of 47-bit dma address */
u16 data_dma_base1; /* upper 7 bits of 47-bit dma address */
u16 overlay_dma_base1; /* upper 7 bits of the 47-bit dma address */
};
struct loader_config_v1 {
u32 reserved;
u32 dma_idx;
struct falc_u64 code_dma_base;
u32 code_size_total;
u32 code_size_to_load;
u32 code_entry_point;
struct falc_u64 data_dma_base;
u32 data_size;
struct falc_u64 overlay_dma_base;
u32 argc;
u32 argv;
};
/*
* Union of all supported structures used by bootloaders.
*/
union flcn_bl_generic_desc {
struct flcn_bl_dmem_desc bl_dmem_desc;
struct loader_config loader_cfg;
};
union flcn_bl_generic_desc_v1 {
struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1;
struct loader_config_v1 loader_cfg_v1;
};
#endif /* __ACR_FLCNBL_H__ */

239
drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h Normal file
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@@ -0,0 +1,239 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __ACR_LSFM_H__
#define __ACR_LSFM_H__
#ifndef __NVGPU_ACR_H__
#warning "acr_lsfm.h not included from nvgpu_acr.h!" \
"Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces"
#endif
/*
* Falcon Id Defines
* Defines a common Light Secure Falcon identifier.
*/
#define LSF_FALCON_ID_PMU (0)
#define LSF_FALCON_ID_RESERVED (1)
#define LSF_FALCON_ID_FECS (2)
#define LSF_FALCON_ID_GPCCS (3)
#define LSF_FALCON_ID_END (11)
#define LSF_FALCON_ID_INVALID (0xFFFFFFFF)
/*
* Light Secure Falcon Ucode Description Defines
* This structure is prelim and may change as the ucode signing flow evolves.
*/
struct lsf_ucode_desc {
u8 prd_keys[2][16];
u8 dbg_keys[2][16];
u32 b_prd_present;
u32 b_dbg_present;
u32 falcon_id;
};
struct lsf_ucode_desc_v1 {
u8 prd_keys[2][16];
u8 dbg_keys[2][16];
u32 b_prd_present;
u32 b_dbg_present;
u32 falcon_id;
u32 bsupports_versioning;
u32 version;
u32 dep_map_count;
u8 dep_map[LSF_FALCON_ID_END * 2 * 4];
u8 kdf[16];
};
/*
* Light Secure WPR Header
* Defines state allowing Light Secure Falcon bootstrapping.
*/
struct lsf_wpr_header {
u32 falcon_id;
u32 lsb_offset;
u32 bootstrap_owner;
u32 lazy_bootstrap;
u32 status;
};
struct lsf_wpr_header_v1 {
u32 falcon_id;
u32 lsb_offset;
u32 bootstrap_owner;
u32 lazy_bootstrap;
u32 bin_version;
u32 status;
};
/*
* Bootstrap Owner Defines
*/
#define LSF_BOOTSTRAP_OWNER_DEFAULT (LSF_FALCON_ID_PMU)
/*
* Image Status Defines
*/
#define LSF_IMAGE_STATUS_NONE (0)
#define LSF_IMAGE_STATUS_COPY (1)
#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2)
#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3)
#define LSF_IMAGE_STATUS_VALIDATION_DONE (4)
#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5)
#define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6)
/*Light Secure Bootstrap header related defines*/
#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0
#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE 1
#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0
#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE 4
#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE 8
#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0
/*
* Light Secure Bootstrap Header
* Defines state allowing Light Secure Falcon bootstrapping.
*/
struct lsf_lsb_header {
struct lsf_ucode_desc signature;
u32 ucode_off;
u32 ucode_size;
u32 data_size;
u32 bl_code_size;
u32 bl_imem_off;
u32 bl_data_off;
u32 bl_data_size;
u32 app_code_off;
u32 app_code_size;
u32 app_data_off;
u32 app_data_size;
u32 flags;
};
struct lsf_lsb_header_v1 {
struct lsf_ucode_desc_v1 signature;
u32 ucode_off;
u32 ucode_size;
u32 data_size;
u32 bl_code_size;
u32 bl_imem_off;
u32 bl_data_off;
u32 bl_data_size;
u32 app_code_off;
u32 app_code_size;
u32 app_data_off;
u32 app_data_size;
u32 flags;
};
/*
* Light Secure WPR Content Alignments
*/
#define LSF_LSB_HEADER_ALIGNMENT 256
#define LSF_BL_DATA_ALIGNMENT 256
#define LSF_BL_DATA_SIZE_ALIGNMENT 256
#define LSF_BL_CODE_SIZE_ALIGNMENT 256
#define LSF_UCODE_DATA_ALIGNMENT 4096
/*
* Supporting maximum of 2 regions.
* This is needed to pre-allocate space in DMEM
*/
#define NVGPU_FLCN_ACR_MAX_REGIONS (2)
#define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200)
/*
* start_addr - Starting address of region
* end_addr - Ending address of region
* region_id - Region ID
* read_mask - Read Mask
* write_mask - WriteMask
* client_mask - Bit map of all clients currently using this region
*/
struct flcn_acr_region_prop {
u32 start_addr;
u32 end_addr;
u32 region_id;
u32 read_mask;
u32 write_mask;
u32 client_mask;
};
struct flcn_acr_region_prop_v1 {
u32 start_addr;
u32 end_addr;
u32 region_id;
u32 read_mask;
u32 write_mask;
u32 client_mask;
u32 shadowmMem_startaddress;
};
/*
* no_regions - Number of regions used.
* region_props - Region properties
*/
struct flcn_acr_regions {
u32 no_regions;
struct flcn_acr_region_prop region_props[NVGPU_FLCN_ACR_MAX_REGIONS];
};
struct flcn_acr_regions_v1 {
u32 no_regions;
struct flcn_acr_region_prop_v1 region_props[NVGPU_FLCN_ACR_MAX_REGIONS];
};
/*
* reserved_dmem-When the bootstrap owner has done bootstrapping other falcons,
* and need to switch into LS mode, it needs to have its own
* actual DMEM image copied into DMEM as part of LS setup. If
* ACR desc is at location 0, it will definitely get overwritten
* causing data corruption. Hence we are reserving 0x200 bytes
* to give room for any loading data. NOTE: This has to be the
* first member always
* signature - Signature of ACR ucode.
* wpr_region_id - Region ID holding the WPR header and its details
* wpr_offset - Offset from the WPR region holding the wpr header
* regions - Region descriptors
* nonwpr_ucode_blob_start -stores non-WPR start where kernel stores ucode blob
* nonwpr_ucode_blob_end -stores non-WPR end where kernel stores ucode blob
*/
struct flcn_acr_desc {
union {
u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)];
u32 signatures[4];
} ucode_reserved_space;
/*Always 1st*/
u32 wpr_region_id;
u32 wpr_offset;
u32 mmu_mem_range;
struct flcn_acr_regions regions;
u32 nonwpr_ucode_blob_size;
u64 nonwpr_ucode_blob_start;
};
struct flcn_acr_desc_v1 {
union {
u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)];
} ucode_reserved_space;
u32 signatures[4];
/*Always 1st*/
u32 wpr_region_id;
u32 wpr_offset;
u32 mmu_mem_range;
struct flcn_acr_regions_v1 regions;
u32 nonwpr_ucode_blob_size;
u64 nonwpr_ucode_blob_start;
u32 dummy[4]; /* ACR_BSI_VPR_DESC */
};
#endif /* __ACR_LSFM_H__ */

82
drivers/gpu/nvgpu/include/nvgpu/acr/acr_objflcn.h Normal file
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@@ -0,0 +1,82 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __ACR_OBJFLCN_H__
#define __ACR_OBJFLCN_H__
#ifndef __NVGPU_ACR_H__
#warning "acr_objflcn.h not included from nvgpu_acr.h!" \
"Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces"
#endif
struct flcn_ucode_img {
u32 *header; /* only some falcons have header */
u32 *data;
struct pmu_ucode_desc *desc; /* only some falcons have descriptor */
u32 data_size;
void *fw_ver; /* CTRL_GPU_GET_FIRMWARE_VERSION_PARAMS struct */
u8 load_entire_os_data; /* load the whole osData section at boot time.*/
/* NULL if not a light secure falcon.*/
struct lsf_ucode_desc *lsf_desc;
/* True if there a resources to freed by the client. */
u8 free_res_allocs;
u32 flcn_inst;
};
struct flcn_ucode_img_v1 {
u32 *header;
u32 *data;
struct pmu_ucode_desc_v1 *desc;
u32 data_size;
void *fw_ver;
u8 load_entire_os_data;
struct lsf_ucode_desc_v1 *lsf_desc;
u8 free_res_allocs;
u32 flcn_inst;
};
/*
* Falcon UCODE header index.
*/
#define FLCN_NL_UCODE_HDR_OS_CODE_OFF_IND (0)
#define FLCN_NL_UCODE_HDR_OS_CODE_SIZE_IND (1)
#define FLCN_NL_UCODE_HDR_OS_DATA_OFF_IND (2)
#define FLCN_NL_UCODE_HDR_OS_DATA_SIZE_IND (3)
#define FLCN_NL_UCODE_HDR_NUM_APPS_IND (4)
/*
* There are total N number of Apps with code and offset defined in UCODE header
* This macro provides the CODE and DATA offset and size of Ath application.
*/
#define FLCN_NL_UCODE_HDR_APP_CODE_START_IND (5)
#define FLCN_NL_UCODE_HDR_APP_CODE_OFF_IND(N, A) \
(FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2))
#define FLCN_NL_UCODE_HDR_APP_CODE_SIZE_IND(N, A) \
(FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2) + 1)
#define FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) \
(FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (N*2) - 1)
#define FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) \
(FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) + 1)
#define FLCN_NL_UCODE_HDR_APP_DATA_OFF_IND(N, A) \
(FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2))
#define FLCN_NL_UCODE_HDR_APP_DATA_SIZE_IND(N, A) \
(FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2) + 1)
#define FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) \
(FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (N*2) - 1)
#define FLCN_NL_UCODE_HDR_OS_OVL_OFF_IND(N) \
(FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 1)
#define FLCN_NL_UCODE_HDR_OS_OVL_SIZE_IND(N) \
(FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 2)
#endif /* __ACR_OBJFLCN_H__ */

76
drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h Normal file
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@@ -0,0 +1,76 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __ACR_OBJLSFM_H__
#define __ACR_OBJLSFM_H__
#ifndef __NVGPU_ACR_H__
#warning "acr_objlsfm.h not included from nvgpu_acr.h!" \
"Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces"
#endif
#include "acr_flcnbl.h"
#include "acr_objflcn.h"
/*
* LSFM Managed Ucode Image
* next : Next image the list, NULL if last.
* wpr_header : WPR header for this ucode image
* lsb_header : LSB header for this ucode image
* bl_gen_desc : Bootloader generic desc structure for this ucode image
* bl_gen_desc_size : Sizeof bootloader desc structure for this ucode image
* full_ucode_size : Surface size required for final ucode image
* ucode_img : Ucode image info
*/
struct lsfm_managed_ucode_img {
struct lsfm_managed_ucode_img *next;
struct lsf_wpr_header wpr_header;
struct lsf_lsb_header lsb_header;
union flcn_bl_generic_desc bl_gen_desc;
u32 bl_gen_desc_size;
u32 full_ucode_size;
struct flcn_ucode_img ucode_img;
};
struct lsfm_managed_ucode_img_v2 {
struct lsfm_managed_ucode_img_v2 *next;
struct lsf_wpr_header_v1 wpr_header;
struct lsf_lsb_header_v1 lsb_header;
union flcn_bl_generic_desc_v1 bl_gen_desc;
u32 bl_gen_desc_size;
u32 full_ucode_size;
struct flcn_ucode_img_v1 ucode_img;
};
/*
* Defines the structure used to contain all generic information related to
* the LSFM.
* Contains the Light Secure Falcon Manager (LSFM) feature related data.
*/
struct ls_flcn_mgr {
u16 managed_flcn_cnt;
u32 wpr_size;
u32 disable_mask;
struct lsfm_managed_ucode_img *ucode_img_list;
void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/
};
struct ls_flcn_mgr_v1 {
u16 managed_flcn_cnt;
u32 wpr_size;
u32 disable_mask;
struct lsfm_managed_ucode_img_v2 *ucode_img_list;
void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/
};
#endif /* __ACR_OBJLSFM_H__ */

65
drivers/gpu/nvgpu/acr.h → drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h
View File

@@ -11,15 +11,60 @@
* more details.
*/
#ifndef __ACR_H_
#define __ACR_H_
#ifndef __NVGPU_ACR_H__
#define __NVGPU_ACR_H__
#include "gm20b/mm_gm20b.h"
#include "gm20b/acr_gm20b.h"
#include "gp106/acr_gp106.h"
#ifdef CONFIG_ARCH_TEGRA_18x_SOC
#include "acr_t18x.h"
#endif
#include "gk20a/mm_gk20a.h"
#include "acr_lsfm.h"
#include "acr_flcnbl.h"
#include "acr_objlsfm.h"
#include "acr_objflcn.h"
#define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/
#define ACR_COMPLETION_TIMEOUT_MS 10000 /*in msec */
#define PMU_SECURE_MODE (0x1)
#define PMU_LSFM_MANAGED (0x2)
struct bin_hdr {
/* 0x10de */
u32 bin_magic;
/* versioning of bin format */
u32 bin_ver;
/* Entire image size including this header */
u32 bin_size;
/*
* Header offset of executable binary metadata,
* start @ offset- 0x100 *
*/
u32 header_offset;
/*
* Start of executable binary data, start @
* offset- 0x200
*/
u32 data_offset;
/* Size of executable binary */
u32 data_size;
};
struct acr_fw_header {
u32 sig_dbg_offset;
u32 sig_dbg_size;
u32 sig_prod_offset;
u32 sig_prod_size;
u32 patch_loc;
u32 patch_sig;
u32 hdr_offset; /* This header points to acr_ucode_header_t210_load */
u32 hdr_size; /* Size of above header */
};
struct wpr_carveout_info {
u64 wpr_base;
u64 nonwpr_base;
u64 size;
};
struct acr_desc {
struct mem_desc ucode_blob;
@@ -32,9 +77,7 @@ struct acr_desc {
const struct firmware *acr_fw;
union{
struct flcn_acr_desc *acr_dmem_desc;
#ifdef CONFIG_ARCH_TEGRA_18x_SOC
struct flcn_acr_desc_v1 *acr_dmem_desc_v1;
#endif
};
struct mem_desc acr_ucode;
const struct firmware *hsbl_fw;
@@ -48,4 +91,4 @@ struct acr_desc {
u32 capabilities;
};
#endif /*__ACR_H_*/
#endif /*__NVGPU_ACR_H__*/