gpu: nvgpu: unit: nvgpu.hal.fifo.ramin unit test

This unit test covers most of the nvgpu.hal.fifo.ramin module lines and
almost all branches.

Jira NVGPU-4391

Change-Id: Iaae4240305822707dd6446cec0ecc9e833ebffdc
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2259638
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

Makefile.umbrella.tmk

@@ -99,6 +99,10 @@ NV_REPOSITORY_COMPONENTS += userspace/units/fifo/pbdma/gv11b
 NV_REPOSITORY_COMPONENTS += userspace/units/fifo/pbdma/gm20b
 NV_REPOSITORY_COMPONENTS += userspace/units/fifo/pbdma/gp10b
 NV_REPOSITORY_COMPONENTS += userspace/units/fifo/preempt
+NV_REPOSITORY_COMPONENTS += userspace/units/fifo/ramin/gk20a
+NV_REPOSITORY_COMPONENTS += userspace/units/fifo/ramin/gm20b
+NV_REPOSITORY_COMPONENTS += userspace/units/fifo/ramin/gp10b
+NV_REPOSITORY_COMPONENTS += userspace/units/fifo/ramin/gv11b
 NV_REPOSITORY_COMPONENTS += userspace/units/fifo/runlist
 NV_REPOSITORY_COMPONENTS += userspace/units/fifo/runlist/gk20a
 NV_REPOSITORY_COMPONENTS += userspace/units/fifo/runlist/gv11b

drivers/gpu/nvgpu/libnvgpu-drv_safe.export

@@ -176,6 +176,9 @@ gv11b_pbdma_handle_intr_1
 gv11b_pbdma_intr_enable
 gv11b_pbdma_set_channel_info_veid
 gv11b_pbdma_setup_hw
+gv11b_ramin_init_subctx_pdb
+gv11b_ramin_set_eng_method_buffer
+gv11b_ramin_set_gr_ptr
 gv11b_runlist_entry_size
 gv11b_runlist_get_tsg_entry
 gv11b_runlist_get_ch_entry
@@ -510,6 +513,7 @@ nvgpu_mc_intr_stall_resume
 nvgpu_mc_intr_stall_unit_config
 nvgpu_memset
 nvgpu_mem_create_from_phys
+nvgpu_mem_get_addr
 nvgpu_mem_iommu_translate
 nvgpu_mem_is_sysmem
 nvgpu_mem_posix_create_from_list

userspace/Makefile.sources

@@ -108,6 +108,10 @@ UNITS :=				\
 	$(UNIT_SRC)/fifo/pbdma/gp10b	\
 	$(UNIT_SRC)/fifo/pbdma/gv11b	\
 	$(UNIT_SRC)/fifo/preempt	\
+	$(UNIT_SRC)/fifo/ramin/gk20a	\
+	$(UNIT_SRC)/fifo/ramin/gm20b	\
+	$(UNIT_SRC)/fifo/ramin/gp10b	\
+	$(UNIT_SRC)/fifo/ramin/gv11b	\
 	$(UNIT_SRC)/fifo/runlist	\
 	$(UNIT_SRC)/fifo/runlist/gk20a	\
 	$(UNIT_SRC)/fifo/runlist/gv11b	\

userspace/SWUTS.h

@@ -55,6 +55,10 @@
  *   - @ref SWUTS-fifo-pbdma-gp10b
  *   - @ref SWUTS-fifo-pbdma-gv11b
  *   - @ref SWUTS-fifo-preempt
+ *   - @ref SWUTS-fifo-ramin-gk20a
+ *   - @ref SWUTS-fifo-ramin-gm20b
+ *   - @ref SWUTS-fifo-ramin-gp10b
+ *   - @ref SWUTS-fifo-ramin-gv11b
  *   - @ref SWUTS-fifo-runlist
  *   - @ref SWUTS-fifo-runlist-gk20a
  *   - @ref SWUTS-fifo-runlist-gv11b

userspace/SWUTS.sources

@@ -29,6 +29,10 @@ INPUT += ../../../userspace/units/fifo/pbdma/gm20b/nvgpu-pbdma-gm20b.h
 INPUT += ../../../userspace/units/fifo/pbdma/gp10b/nvgpu-pbdma-gp10b.h
 INPUT += ../../../userspace/units/fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.h
 INPUT += ../../../userspace/units/fifo/preempt/nvgpu-preempt.h
+INPUT += ../../../userspace/units/fifo/ramin/gk20a/ramin-gk20a-fusa.h
+INPUT += ../../../userspace/units/fifo/ramin/gm20b/ramin-gm20b-fusa.h
+INPUT += ../../../userspace/units/fifo/ramin/gp10b/ramin-gp10b-fusa.h
+INPUT += ../../../userspace/units/fifo/ramin/gv11b/ramin-gv11b-fusa.h
 INPUT += ../../../userspace/units/fifo/runlist/nvgpu-runlist.h
 INPUT += ../../../userspace/units/fifo/runlist/gk20a/nvgpu-runlist-gk20a.h
 INPUT += ../../../userspace/units/fifo/runlist/gv11b/nvgpu-runlist-gv11b.h

userspace/required_tests.json

@@ -4262,6 +4262,48 @@
         "unit": "therm",
         "test_level": 0
     },
+    {
+        "test": "test_gk20a_ramin_alloc_size",
+        "case": "alloc_size",
+        "unit": "ramin_gk20a_fusa",
+        "test_level": 0
+    },
+    {
+        "test": "test_gk20a_ramin_base_shift",
+        "case": "base_shift",
+        "unit": "ramin_gk20a_fusa",
+        "test_level": 0
+    },
+    {
+        "test": "test_gm20b_ramin_set_big_page_size",
+        "case": "set_big_page_size",
+        "unit": "ramin_gm20b_fusa",
+        "test_level": 0
+    },
+    {
+        "test": "test_gp10b_ramin_init_pdb",
+        "case": "init_pdb",
+        "unit": "ramin_gp10b_fusa",
+        "test_level": 0
+    },
+    {
+        "test": "test_gv11b_ramin_init_subctx_pdb",
+        "case": "init_subctx_pdb",
+        "unit": "ramin_gv11b_fusa",
+        "test_level": 0
+    },
+    {
+        "test": "test_gv11b_ramin_set_eng_method_buffer",
+        "case": "set_eng_method_buf",
+        "unit": "ramin_gv11b_fusa",
+        "test_level": 0
+    },
+    {
+        "test": "test_gv11b_ramin_set_gr_ptr",
+        "case": "set_gr_ptr",
+        "unit": "ramin_gv11b_fusa",
+        "test_level": 0
+    },
     {
         "test": "test_device_info_parse_data",
         "case": "top_device_info_parse_data",

userspace/units/fifo/ramin/gk20a/Makefile

@@ -0,0 +1,32 @@
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+.SUFFIXES:
+
+OBJS   = ramin-gk20a-fusa.o
+MODULE = ramin-gk20a-fusa
+
+LIB_PATHS += -lnvgpu-fifo-common
+include ../../../Makefile.units
+
+lib$(MODULE).so: fifo
+
+fifo:
+	$(MAKE) -C ../..

userspace/units/fifo/ramin/gk20a/Makefile.interface.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=ramin-gk20a-fusa
+
+include $(NV_SOURCE)/kernel/nvgpu/userspace/units/Makefile.units.common.interface.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/fifo/ramin/gk20a/Makefile.tmk

@@ -0,0 +1,40 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME = ramin-gk20a-fusa
+NVGPU_UNIT_SRCS = ramin-gk20a-fusa.c
+
+NVGPU_UNIT_INTERFACE_DIRS := \
+	$(NV_SOURCE)/kernel/nvgpu/userspace/units/fifo \
+	$(NV_SOURCE)/kernel/nvgpu/drivers/gpu/nvgpu
+
+include $(NV_SOURCE)/kernel/nvgpu/userspace/units/Makefile.units.common.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/fifo/ramin/gk20a/ramin-gk20a-fusa.c

@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <unit/io.h>
+#include <unit/unit.h>
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
+
+#include "hal/fifo/ramin_gk20a.h"
+
+#include "../../nvgpu-fifo-common.h"
+#include "ramin-gk20a-fusa.h"
+
+#define assert(cond)	unit_assert(cond, goto done)
+
+int test_gk20a_ramin_base_shift(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	int ret = UNIT_FAIL;
+	u32 base_shift = 0U;
+
+	base_shift = gk20a_ramin_base_shift();
+	assert(base_shift == ram_in_base_shift_v());
+
+	ret = UNIT_SUCCESS;
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s failed\n", __func__);
+	}
+	return ret;
+}
+
+int test_gk20a_ramin_alloc_size(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	int ret = UNIT_FAIL;
+	u32 alloc_size = 0U;
+
+	alloc_size = gk20a_ramin_alloc_size();
+	assert(alloc_size == ram_in_alloc_size_v());
+
+	ret = UNIT_SUCCESS;
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s failed\n", __func__);
+	}
+	return ret;
+}
+
+struct unit_module_test ramin_gk20a_fusa_tests[] = {
+	UNIT_TEST(base_shift, test_gk20a_ramin_base_shift, NULL, 0),
+	UNIT_TEST(alloc_size, test_gk20a_ramin_alloc_size, NULL, 0),
+};
+
+UNIT_MODULE(ramin_gk20a_fusa, ramin_gk20a_fusa_tests, UNIT_PRIO_NVGPU_TEST);

userspace/units/fifo/ramin/gk20a/ramin-gk20a-fusa.h

@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef UNIT_FIFO_RAMIN_GK20A_FUSA_H
+#define UNIT_FIFO_RAMIN_GK20A_FUSA_H
+
+#include <nvgpu/types.h>
+
+struct unit_module;
+struct gk20a;
+
+/** @addtogroup SWUTS-fifo-ramin-gk20a
+ *  @{
+ *
+ * Software Unit Test Specification for fifo/ramin/gk20a
+ */
+
+/**
+ * Test specification for: test_gk20a_ramin_base_shift
+ *
+ * Description: Test gk20a base shift value
+ *
+ * Test Type: Feature based
+ *
+ * Targets: gk20a_ramin_base_shift
+ *
+ * Input: None
+ *
+ * Steps:
+ * - Check that instance block shift (in bits) is correct as per hardware
+ *   manual. This gives number of zeros in instance block physical address and
+ *   thus defines alignment.
+ *
+ * Output: Returns PASS if all branches gave expected results. FAIL otherwise.
+ */
+int test_gk20a_ramin_base_shift(struct unit_module *m, struct gk20a *g,
+								void *args);
+
+/**
+ * Test specification for: test_gk20a_ramin_alloc_size
+ *
+ * Description: Test gk20a alloc size
+ *
+ * Test Type: Feature based
+ *
+ * Targets: gk20a_ramin_alloc_size
+ *
+ * Input: None
+ *
+ * Steps:
+ * - Check instance block alloc size is correct as per hardware manuals.
+ *
+ * Output: Returns PASS if all branches gave expected results. FAIL otherwise.
+ */
+int test_gk20a_ramin_alloc_size(struct unit_module *m, struct gk20a *g,
+								void *args);
+
+/**
+ * @}
+ */
+
+#endif /* UNIT_FIFO_RAMIN_GK20A_FUSA_H */

userspace/units/fifo/ramin/gm20b/Makefile

@@ -0,0 +1,32 @@
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+.SUFFIXES:
+
+OBJS   = ramin-gm20b-fusa.o
+MODULE = ramin-gm20b-fusa
+
+LIB_PATHS += -lnvgpu-fifo-common
+include ../../../Makefile.units
+
+lib$(MODULE).so: fifo
+
+fifo:
+	$(MAKE) -C ../..

userspace/units/fifo/ramin/gm20b/Makefile.interface.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=ramin-gm20b-fusa
+
+include $(NV_SOURCE)/kernel/nvgpu/userspace/units/Makefile.units.common.interface.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/fifo/ramin/gm20b/Makefile.tmk

@@ -0,0 +1,40 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME = ramin-gm20b-fusa
+NVGPU_UNIT_SRCS = ramin-gm20b-fusa.c
+
+NVGPU_UNIT_INTERFACE_DIRS := \
+	$(NV_SOURCE)/kernel/nvgpu/userspace/units/fifo \
+	$(NV_SOURCE)/kernel/nvgpu/drivers/gpu/nvgpu
+
+include $(NV_SOURCE)/kernel/nvgpu/userspace/units/Makefile.units.common.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/fifo/ramin/gm20b/ramin-gm20b-fusa.c

@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <unit/io.h>
+#include <unit/unit.h>
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/dma.h>
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
+
+#include "hal/fifo/ramin_gk20a.h"
+#include "hal/fifo/ramin_gm20b.h"
+
+#include "../../nvgpu-fifo-common.h"
+#include "ramin-gm20b-fusa.h"
+
+#ifdef RAMIN_GM20B_UNIT_DEBUG
+#undef unit_verbose
+#define unit_verbose	unit_info
+#else
+#define unit_verbose(unit, msg, ...) \
+	do { \
+		if (0) { \
+			unit_info(unit, msg, ##__VA_ARGS__); \
+		} \
+	} while (0)
+#endif
+
+#define assert(cond)	unit_assert(cond, goto done)
+
+#define branches_str test_fifo_flags_str
+#define pruned test_fifo_subtest_pruned
+
+#define F_SET_BIG_PAGE_SIZE_64K			BIT(0)
+#define F_SET_BIG_PAGE_SIZE_LAST		BIT(1)
+
+static const char *f_set_big_page_size[] = {
+	"set_big_page_size_64K",
+};
+
+int test_gm20b_ramin_set_big_page_size(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	struct nvgpu_mem mem;
+	int ret = UNIT_FAIL;
+	u32 branches = 0U;
+	int err;
+	u32 size;
+	u32 data = 1U;
+
+	g->ops.ramin.alloc_size = gk20a_ramin_alloc_size;
+
+	err = nvgpu_dma_alloc(g, g->ops.ramin.alloc_size(), &mem);
+	assert(err == 0);
+
+	for (branches = 0U; branches < F_SET_BIG_PAGE_SIZE_LAST; branches++) {
+		unit_verbose(m, "%s branches=%s\n",
+			__func__, branches_str(branches, f_set_big_page_size));
+
+		/* Initialize value of big page size in mem struct */
+		nvgpu_mem_wr32(g, &mem, ram_in_big_page_size_w(), data);
+
+		size = branches & F_SET_BIG_PAGE_SIZE_64K ? SZ_64K : SZ_4K;
+
+		gm20b_ramin_set_big_page_size(g, &mem, size);
+
+		if (branches & F_SET_BIG_PAGE_SIZE_64K) {
+			assert(nvgpu_mem_rd32(g, &mem,
+				ram_in_big_page_size_w()) ==
+				(data | ram_in_big_page_size_64kb_f()));
+		} else {
+			assert(nvgpu_mem_rd32(g, &mem,
+				ram_in_big_page_size_w()) ==
+				(data | ram_in_big_page_size_128kb_f()));
+		}
+	}
+
+	ret = UNIT_SUCCESS;
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s branches=%s\n", __func__,
+				branches_str(branches, f_set_big_page_size));
+	}
+
+	nvgpu_dma_free(g, &mem);
+	return ret;
+}
+
+struct unit_module_test ramin_gm20b_fusa_tests[] = {
+	UNIT_TEST(set_big_page_size, test_gm20b_ramin_set_big_page_size, NULL, 0),
+};
+
+UNIT_MODULE(ramin_gm20b_fusa, ramin_gm20b_fusa_tests, UNIT_PRIO_NVGPU_TEST);

userspace/units/fifo/ramin/gm20b/ramin-gm20b-fusa.h

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef UNIT_FIFO_RAMIN_GM20B_FUSA_H
+#define UNIT_FIFO_RAMIN_GM20B_FUSA_H
+
+#include <nvgpu/types.h>
+
+struct unit_module;
+struct gk20a;
+
+/** @addtogroup SWUTS-fifo-ramin-gm20b
+ *  @{
+ *
+ * Software Unit Test Specification for fifo/ramin/gm20b
+ */
+
+/**
+ * Test specification for: test_gm20b_ramin_set_big_page_size
+ *
+ * Description: Test big page size set
+ *
+ * Test Type: Feature based
+ *
+ * Targets: gm20b_ramin_set_big_page_size
+ *
+ * Input: None
+ *
+ * Steps:
+ * - Set big page size in given instance block.
+ *
+ * Output: Returns PASS if all branches gave expected results. FAIL otherwise.
+ */
+int test_gm20b_ramin_set_big_page_size(struct unit_module *m, struct gk20a *g,
+								void *args);
+
+/**
+ * @}
+ */
+
+#endif /* UNIT_FIFO_RAMIN_GM20B_FUSA_H */

userspace/units/fifo/ramin/gp10b/Makefile

@@ -0,0 +1,32 @@
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+.SUFFIXES:
+
+OBJS   = ramin-gp10b-fusa.o
+MODULE = ramin-gp10b-fusa
+
+LIB_PATHS += -lnvgpu-fifo-common
+include ../../../Makefile.units
+
+lib$(MODULE).so: fifo
+
+fifo:
+	$(MAKE) -C ../..

userspace/units/fifo/ramin/gp10b/Makefile.interface.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=ramin-gp10b-fusa
+
+include $(NV_SOURCE)/kernel/nvgpu/userspace/units/Makefile.units.common.interface.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/fifo/ramin/gp10b/Makefile.tmk

@@ -0,0 +1,40 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME = ramin-gp10b-fusa
+NVGPU_UNIT_SRCS = ramin-gp10b-fusa.c
+
+NVGPU_UNIT_INTERFACE_DIRS := \
+	$(NV_SOURCE)/kernel/nvgpu/userspace/units/fifo \
+	$(NV_SOURCE)/kernel/nvgpu/drivers/gpu/nvgpu
+
+include $(NV_SOURCE)/kernel/nvgpu/userspace/units/Makefile.units.common.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/fifo/ramin/gp10b/ramin-gp10b-fusa.c

@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <unit/io.h>
+#include <unit/unit.h>
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/mm.h>
+#include <nvgpu/dma.h>
+#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
+
+#include "hal/fifo/ramin_gk20a.h"
+#include "hal/fifo/ramin_gp10b.h"
+
+#include "../../nvgpu-fifo-common.h"
+#include "ramin-gp10b-fusa.h"
+
+#define assert(cond)	unit_assert(cond, goto done)
+
+int test_gp10b_ramin_init_pdb(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	struct nvgpu_mem inst_block;
+	struct nvgpu_mem pdb_mem;
+	int ret = UNIT_FAIL;
+	int err;
+	u32 data;
+	u32 pdb_addr_lo, pdb_addr_hi;
+	u64 pdb_addr;
+	u32 aperture;
+
+	g->ops.ramin.alloc_size = gk20a_ramin_alloc_size;
+
+	/* Aperture should be fixed = SYSMEM */
+	nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, true);
+	err = nvgpu_alloc_inst_block(g, &inst_block);
+	assert(err == 0);
+
+	err = nvgpu_dma_alloc(g, g->ops.ramin.alloc_size(), &pdb_mem);
+	assert(err == 0);
+
+	pdb_addr = nvgpu_mem_get_addr(g, &pdb_mem);
+	pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
+	pdb_addr_hi = u64_hi32(pdb_addr);
+
+	aperture = ram_in_sc_page_dir_base_target_sys_mem_ncoh_v();
+
+	data = aperture | ram_in_page_dir_base_vol_true_f() |
+		ram_in_big_page_size_64kb_f() |
+		ram_in_page_dir_base_lo_f(pdb_addr_lo) |
+		ram_in_use_ver2_pt_format_true_f();
+
+	gp10b_ramin_init_pdb(g, &inst_block, pdb_addr, &pdb_mem);
+
+	assert(nvgpu_mem_rd32(g, &inst_block, ram_in_page_dir_base_lo_w()) ==
+						data);
+	assert(nvgpu_mem_rd32(g, &inst_block, ram_in_page_dir_base_hi_w()) ==
+					ram_in_page_dir_base_hi_f(pdb_addr_hi));
+
+	ret = UNIT_SUCCESS;
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s failed\n", __func__);
+	}
+
+	nvgpu_dma_free(g, &pdb_mem);
+	nvgpu_free_inst_block(g, &inst_block);
+	nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, false);
+	return ret;
+}
+
+struct unit_module_test ramin_gp10b_fusa_tests[] = {
+	UNIT_TEST(init_pdb, test_gp10b_ramin_init_pdb, NULL, 0),
+};
+
+UNIT_MODULE(ramin_gp10b_fusa, ramin_gp10b_fusa_tests, UNIT_PRIO_NVGPU_TEST);

userspace/units/fifo/ramin/gp10b/ramin-gp10b-fusa.h

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef UNIT_FIFO_RAMIN_GP10B_FUSA_H
+#define UNIT_FIFO_RAMIN_GP10B_FUSA_H
+
+#include <nvgpu/types.h>
+
+struct unit_module;
+struct gk20a;
+
+/** @addtogroup SWUTS-fifo-ramin-gp10b
+ *  @{
+ *
+ * Software Unit Test Specification for fifo/ramin/gp10b
+ */
+
+/**
+ * Test specification for: test_gv11b_ramin_set_gr_ptr
+ *
+ * Description: Initialize instance block's PDB
+ *
+ * Test Type: Feature based
+ *
+ * Targets: gv11b_ramin_set_gr_ptr
+ *
+ * Input: None
+ *
+ * Steps:
+ * - Configure PDB aperture, big page size, pdb address, PT format and default
+ *   attribute.
+ * - Check page directory base values stored in instance block are correct.
+ *
+ * Output: Returns PASS if all branches gave expected results. FAIL otherwise.
+ */
+int test_gp10b_ramin_init_pdb(struct unit_module *m, struct gk20a *g,
+								void *args);
+
+/**
+ * @}
+ */
+
+#endif /* UNIT_FIFO_RAMIN_GP10B_FUSA_H */

userspace/units/fifo/ramin/gv11b/Makefile

@@ -0,0 +1,32 @@
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+.SUFFIXES:
+
+OBJS   = ramin-gv11b-fusa.o
+MODULE = ramin-gv11b-fusa
+
+LIB_PATHS += -lnvgpu-fifo-common
+include ../../../Makefile.units
+
+lib$(MODULE).so: fifo
+
+fifo:
+	$(MAKE) -C ../..

userspace/units/fifo/ramin/gv11b/Makefile.interface.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=ramin-gv11b-fusa
+
+include $(NV_SOURCE)/kernel/nvgpu/userspace/units/Makefile.units.common.interface.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/fifo/ramin/gv11b/Makefile.tmk

@@ -0,0 +1,40 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME = ramin-gv11b-fusa
+NVGPU_UNIT_SRCS = ramin-gv11b-fusa.c
+
+NVGPU_UNIT_INTERFACE_DIRS := \
+	$(NV_SOURCE)/kernel/nvgpu/userspace/units/fifo \
+	$(NV_SOURCE)/kernel/nvgpu/drivers/gpu/nvgpu
+
+include $(NV_SOURCE)/kernel/nvgpu/userspace/units/Makefile.units.common.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/fifo/ramin/gv11b/ramin-gv11b-fusa.c

@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <unit/io.h>
+#include <unit/unit.h>
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/mm.h>
+#include <nvgpu/dma.h>
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
+
+#include "hal/fifo/ramin_gk20a.h"
+#include "hal/fifo/ramin_gv11b.h"
+
+#include "../../nvgpu-fifo-common.h"
+#include "ramin-gv11b-fusa.h"
+
+#ifdef RAMIN_GV11B_UNIT_DEBUG
+#undef unit_verbose
+#define unit_verbose	unit_info
+#else
+#define unit_verbose(unit, msg, ...) \
+	do { \
+		if (0) { \
+			unit_info(unit, msg, ##__VA_ARGS__); \
+		} \
+	} while (0)
+#endif
+
+#define assert(cond)	unit_assert(cond, goto done)
+
+#define branches_str test_fifo_flags_str
+#define pruned test_fifo_subtest_pruned
+
+int test_gv11b_ramin_set_gr_ptr(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	struct nvgpu_mem inst_block;
+	int ret = UNIT_FAIL;
+	int err;
+	u32 addr_lo = 1U;
+	u32 addr_hi = 2U;
+	u64 addr = ((u64)addr_hi << 32U) | (addr_lo << ram_in_base_shift_v());
+	u32 data_lo = ram_in_engine_cs_wfi_v() |
+		ram_in_engine_wfi_mode_f(ram_in_engine_wfi_mode_virtual_v()) |
+		ram_in_engine_wfi_ptr_lo_f(addr_lo);
+	u32 data_hi = ram_in_engine_wfi_ptr_hi_f(addr_hi);
+	u32 *data_ptr;
+
+	g->ops.ramin.alloc_size = gk20a_ramin_alloc_size;
+
+	err = nvgpu_alloc_inst_block(g, &inst_block);
+	assert(err == 0);
+	data_ptr = inst_block.cpu_va;
+
+	gv11b_ramin_set_gr_ptr(g, &inst_block, addr);
+	assert(data_ptr[ram_in_engine_wfi_target_w()] == data_lo);
+	assert(data_ptr[ram_in_engine_wfi_ptr_hi_w()] == data_hi);
+
+	ret = UNIT_SUCCESS;
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s failed\n", __func__);
+	}
+
+	nvgpu_free_inst_block(g, &inst_block);
+	return ret;
+}
+
+#define F_INIT_SUBCTX_PDB_REPLAYABLE			BIT(0)
+#define F_INIT_SUBCTX_PDB_LAST				BIT(1)
+
+static const char *f_init_subctx_pdb[] = {
+	"init_subctx_pdb",
+};
+
+int test_gv11b_ramin_init_subctx_pdb(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	struct nvgpu_mem inst_block;
+	struct nvgpu_mem pdb_mem;
+	int ret = UNIT_FAIL;
+	u32 branches = 0U;
+	int err;
+	bool replayable;
+	u32 subctx_id, format_data;
+	u32 addr_lo, addr_hi;
+	u32 pdb_addr_lo, pdb_addr_hi;
+	u64 pdb_addr;
+	u32 max_subctx_count = ram_in_sc_page_dir_base_target__size_1_v();
+	u32 aperture = ram_in_sc_page_dir_base_target_sys_mem_ncoh_v();
+
+	g->ops.ramin.alloc_size = gk20a_ramin_alloc_size;
+
+	/* Aperture should be fixed = SYSMEM */
+	nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, true);
+	err = nvgpu_alloc_inst_block(g, &inst_block);
+	assert(err == 0);
+
+	err = nvgpu_dma_alloc(g, g->ops.ramin.alloc_size(), &pdb_mem);
+	assert(err == 0);
+
+	pdb_addr = nvgpu_mem_get_addr(g, &pdb_mem);
+	pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
+	pdb_addr_hi = u64_hi32(pdb_addr);
+
+	format_data = ram_in_sc_page_dir_base_target_f(aperture, 0U) |
+		ram_in_sc_page_dir_base_vol_f(
+		ram_in_sc_page_dir_base_vol_true_v(), 0U) |
+		ram_in_sc_use_ver2_pt_format_f(1U, 0U) |
+		ram_in_sc_big_page_size_f(1U, 0U) |
+		ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo);
+
+	for (branches = 0U; branches < F_INIT_SUBCTX_PDB_LAST; branches++) {
+		unit_verbose(m, "%s branches=%s\n",
+			__func__, branches_str(branches, f_init_subctx_pdb));
+
+		replayable = branches & F_INIT_SUBCTX_PDB_REPLAYABLE ?
+				true : false;
+
+		if (replayable) {
+			format_data |=
+				ram_in_sc_page_dir_base_fault_replay_tex_f(
+					1U, 0U) |
+				ram_in_sc_page_dir_base_fault_replay_gcc_f(
+					1U, 0U);
+		}
+
+		gv11b_ramin_init_subctx_pdb(g, &inst_block, &pdb_mem,
+								replayable);
+
+		for (subctx_id = 0; subctx_id < max_subctx_count; subctx_id++) {
+			addr_lo = ram_in_sc_page_dir_base_vol_w(subctx_id);
+			addr_hi = ram_in_sc_page_dir_base_hi_w(subctx_id);
+			assert(nvgpu_mem_rd32(g, &inst_block, addr_lo) ==
+							format_data);
+			assert(nvgpu_mem_rd32(g, &inst_block, addr_hi) ==
+							pdb_addr_hi);
+		}
+
+		for (subctx_id = 0; subctx_id < ram_in_sc_pdb_valid__size_1_v();
+							subctx_id += 32U) {
+			assert(nvgpu_mem_rd32(g, &inst_block,
+				ram_in_sc_pdb_valid_long_w(subctx_id)) ==
+								U32_MAX);
+		}
+
+	}
+
+	ret = UNIT_SUCCESS;
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s branches=%s\n", __func__,
+				branches_str(branches, f_init_subctx_pdb));
+	}
+
+	nvgpu_dma_free(g, &pdb_mem);
+	nvgpu_free_inst_block(g, &inst_block);
+	nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, false);
+	return ret;
+}
+
+int test_gv11b_ramin_set_eng_method_buffer(struct unit_module *m,
+						struct gk20a *g, void *args)
+{
+	struct nvgpu_mem inst_block;
+	int ret = UNIT_FAIL;
+	int err;
+	u32 addr_lo = 1U;
+	u32 addr_hi = 2U;
+	u64 addr = ((u64)addr_hi << 32U) | (addr_lo);
+	u32 *data_ptr;
+
+	g->ops.ramin.alloc_size = gk20a_ramin_alloc_size;
+
+	err = nvgpu_alloc_inst_block(g, &inst_block);
+	assert(err == 0);
+	data_ptr = inst_block.cpu_va;
+
+	gv11b_ramin_set_eng_method_buffer(g, &inst_block, addr);
+	assert(data_ptr[ram_in_eng_method_buffer_addr_lo_w()] == addr_lo);
+	assert(data_ptr[ram_in_eng_method_buffer_addr_hi_w()] == addr_hi);
+
+	ret = UNIT_SUCCESS;
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s failed\n", __func__);
+	}
+
+	nvgpu_free_inst_block(g, &inst_block);
+	return ret;
+}
+
+struct unit_module_test ramin_gv11b_fusa_tests[] = {
+	UNIT_TEST(set_gr_ptr, test_gv11b_ramin_set_gr_ptr, NULL, 0),
+	UNIT_TEST(init_subctx_pdb, test_gv11b_ramin_init_subctx_pdb, NULL, 0),
+	UNIT_TEST(set_eng_method_buf, test_gv11b_ramin_set_eng_method_buffer, NULL, 0),
+};
+
+UNIT_MODULE(ramin_gv11b_fusa, ramin_gv11b_fusa_tests, UNIT_PRIO_NVGPU_TEST);

userspace/units/fifo/ramin/gv11b/ramin-gv11b-fusa.h

@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef UNIT_FIFO_RAMIN_GV11B_FUSA_H
+#define UNIT_FIFO_RAMIN_GV11B_FUSA_H
+
+#include <nvgpu/types.h>
+
+struct unit_module;
+struct gk20a;
+
+/** @addtogroup SWUTS-fifo-ramin-gv11b
+ *  @{
+ *
+ * Software Unit Test Specification for fifo/ramin/gv11b
+ */
+
+/**
+ * Test specification for: test_gv11b_ramin_set_gr_ptr
+ *
+ * Description: Test GR address set in instance block
+ *
+ * Test Type: Feature based
+ *
+ * Targets: gv11b_ramin_set_gr_ptr
+ *
+ * Input: None
+ *
+ * Steps:
+ * - Store GPU_VA of GR engine context state in channel instance block.
+ * - Check that stored value is correct.
+ *
+ * Output: Returns PASS if all branches gave expected results. FAIL otherwise.
+ */
+int test_gv11b_ramin_set_gr_ptr(struct unit_module *m, struct gk20a *g,
+								void *args);
+
+/**
+ * Test specification for: test_gv11b_ramin_init_subctx_pdb
+ *
+ * Description: Test page directory buffer configure for sub-contexts of
+ *              instance block
+ *
+ * Test Type: Feature based
+ *
+ * Targets: gv11b_ramin_init_subctx_pdb, gv11b_subctx_commit_pdb,
+ *          gv11b_subctx_commit_valid_mask
+ *
+ * Input: None
+ *
+ * Steps:
+ * - Build PDB entry with PT version, big page size, volatile attribute and
+ *   pdb_mem aperture mask. If errors are replayable, set replayable attribute
+ *   for TEX and GCC faults. Set lo and hi 32-bits to point to pdb_mem and store
+ *   this related entry in instance block.
+ * - Check that the stored entry value is correct.
+ *
+ * Output: Returns PASS if all branches gave expected results. FAIL otherwise.
+ */
+int test_gv11b_ramin_init_subctx_pdb(struct unit_module *m, struct gk20a *g,
+								void *args);
+
+/**
+ * Test specification for: test_gv11b_ramin_set_eng_method_buffer
+ *
+ * Description: Test engine method buffer set
+ *
+ * Test Type: Feature based
+ *
+ * Targets: gv11b_ramin_set_eng_method_buffer
+ *
+ * Input: None
+ *
+ * Steps:
+ * - Save engine method buffer gpu_va to instance block data.
+ * - Check address stored at specific offset is equal to given address.
+ *
+ * Output: Returns PASS if all branches gave expected results. FAIL otherwise.
+ */
+int test_gv11b_ramin_set_eng_method_buffer(struct unit_module *m,
+						struct gk20a *g, void *args);
+
+/**
+ * @}
+ */
+
+#endif /* UNIT_FIFO_RAMIN_GV11B_FUSA_H */