From 9cd4357f4e27f979514e88d4ec1f03e0de9a77ba Mon Sep 17 00:00:00 2001 From: vinodg Date: Wed, 4 Dec 2019 14:23:41 -0800 Subject: [PATCH] gpu: nvgpu: gr.falcon unit test update Remove the code used to verify the nonsecure gpccs path on initialize ctxsw ucode. For Safety secure path is enabled by default. Jira NVGPU-4453 Change-Id: I55aae29f56a9909d6c9966582a5d56f85b684a12 Signed-off-by: vinodg Reviewed-on: https://git-master.nvidia.com/r/2255491 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: mobile promotions Tested-by: mobile promotions --- userspace/units/gr/falcon/nvgpu-gr-falcon.c | 44 +-------------------- userspace/units/gr/falcon/nvgpu-gr-falcon.h | 35 +++++++++++----- 2 files changed, 27 insertions(+), 52 deletions(-) diff --git a/userspace/units/gr/falcon/nvgpu-gr-falcon.c b/userspace/units/gr/falcon/nvgpu-gr-falcon.c index f37a453f6..8fd1846da 100644 --- a/userspace/units/gr/falcon/nvgpu-gr-falcon.c +++ b/userspace/units/gr/falcon/nvgpu-gr-falcon.c @@ -46,9 +46,6 @@ struct gr_gops_falcon_orgs { void (*bind_instblk)(struct gk20a *g, struct nvgpu_mem *mem, u64 inst_ptr); - void (*load_ctxsw_ucode_header)(struct gk20a *g, - u32 reg_offset, u32 boot_signature, u32 addr_code32, - u32 addr_data32, u32 code_size, u32 data_size); int (*load_ctxsw_ucode)(struct gk20a *g, struct nvgpu_gr_falcon *falcon); int (*init_ctx_state)(struct gk20a *g, @@ -64,14 +61,6 @@ static void test_gr_falcon_bind_instblk(struct gk20a *g, /* Do nothing */ } -static void test_gr_falcon_load_ctxsw_ucode_header(struct gk20a *g, - u32 reg_offset, u32 boot_signature, u32 addr_code32, - u32 addr_data32, u32 code_size, u32 data_size) -{ - /* Do nothing */ - -} - static int gr_falcon_stub_init_ctx_state(struct gk20a *g, struct nvgpu_gr_falcon_query_sizes *sizes) { @@ -88,8 +77,6 @@ static void gr_falcon_save_gops(struct gk20a *g) { gr_falcon_gops.load_ctxsw_ucode = g->ops.gr.falcon.load_ctxsw_ucode; - gr_falcon_gops.load_ctxsw_ucode_header = - g->ops.gr.falcon.load_ctxsw_ucode_header; gr_falcon_gops.bind_instblk = g->ops.gr.falcon.bind_instblk; gr_falcon_gops.init_ctx_state = g->ops.gr.falcon.init_ctx_state; } @@ -98,8 +85,6 @@ static void gr_falcon_stub_gops(struct gk20a *g) { g->ops.gr.falcon.load_ctxsw_ucode = nvgpu_gr_falcon_load_secure_ctxsw_ucode; - g->ops.gr.falcon.load_ctxsw_ucode_header = - test_gr_falcon_load_ctxsw_ucode_header; g->ops.gr.falcon.bind_instblk = test_gr_falcon_bind_instblk; } @@ -149,14 +134,6 @@ int test_gr_falcon_init_ctxsw(struct unit_module *m, if (err) { unit_return_fail(m, "nvgpu_gr_falcon_init_ctxsw failed\n"); } - - /* Test nonsecure gpccs */ - nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); - nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); - err = nvgpu_gr_falcon_init_ctxsw(g, unit_gr_falcon); - if (err) { - unit_return_fail(m, "nvgpu_gr_falcon_init_ctxsw failed\n"); - } nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); /* Test for recovery to fail */ @@ -176,25 +153,6 @@ int test_gr_falcon_init_ctxsw(struct unit_module *m, "falcon_init_ctxsw secure recovery failed\n"); } - /* Test for nonsecure gpccs recovery */ - nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); - err = nvgpu_gr_falcon_init_ctxsw(g, unit_gr_falcon); - if (err != 0) { - unit_return_fail(m, - "falcon_init_ctxsw nonsecure recovery failed\n"); - } - - g->ops.gr.falcon.load_ctxsw_ucode_header = - gr_falcon_gops.load_ctxsw_ucode_header; - err = nvgpu_gr_falcon_init_ctxsw(g, unit_gr_falcon); - if (err != 0) { - unit_return_fail(m, - "falcon_init_ctxsw nonsecure recovery failed\n"); - } - g->ops.gr.falcon.load_ctxsw_ucode_header = - test_gr_falcon_load_ctxsw_ucode_header; - nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); - return UNIT_SUCCESS; } @@ -276,7 +234,7 @@ int test_gr_falcon_deinit(struct unit_module *m, return UNIT_SUCCESS; } -static int test_gr_falcon_fail_ctxsw_ucode(struct unit_module *m, +int test_gr_falcon_fail_ctxsw_ucode(struct unit_module *m, struct gk20a *g, void *args) { int err = 0; diff --git a/userspace/units/gr/falcon/nvgpu-gr-falcon.h b/userspace/units/gr/falcon/nvgpu-gr-falcon.h index b3bd5583f..b76a6a494 100644 --- a/userspace/units/gr/falcon/nvgpu-gr-falcon.h +++ b/userspace/units/gr/falcon/nvgpu-gr-falcon.h @@ -64,7 +64,7 @@ int test_gr_falcon_init(struct unit_module *m, * * Description: Helps to verify common.gr.falcon subunit deinitialization. * - * Test Type: Feature based, Error injection.. + * Test Type: Feature based, Error injection. * * Targets: #nvgpu_gr_falcon_remove_support. * @@ -95,13 +95,8 @@ int test_gr_falcon_deinit(struct unit_module *m, * Steps: * - By default code use secure gpccs path. * - Call #nvgpu_gr_falcon_init_ctxsw. - * - Enable nonsecure gpccs path. - * - Call #nvgpu_gr_falcon_init_ctxsw. - * - Enable secure gpccs path. * - Call #nvgpu_gr_falcon_init_ctxsw to test recovery path failure. - * - Enable nonsecure gpccs path. * - Call #nvgpu_gr_falcon_init_ctxsw to test recovery path success. - * - Enable secure gpccs path. * * Output: Returns PASS if the steps above were executed successfully. FAIL * otherwise. @@ -144,15 +139,37 @@ int test_gr_falcon_init_ctx_state(struct unit_module *m, * Input: #test_gr_falcon_init must have been executed successfully. * * Steps: - * - Call #nvgpu_gr_falcon_get_fecs_ucode_segments. - * - Call #nvgpu_gr_falcon_get_gpccs_ucode_segments. - * - Call #nvgpu_gr_falcon_get_surface_desc_cpu_va. + * - Call #nvgpu_gr_falcon_get_fecs_ucode_segments. + * - Call #nvgpu_gr_falcon_get_gpccs_ucode_segments. + * - Call #nvgpu_gr_falcon_get_surface_desc_cpu_va. * * Output: Returns PASS if the steps above were executed successfully. FAIL * otherwise. */ int test_gr_falcon_query_test(struct unit_module *m, struct gk20a *g, void *args); + +/** + * Test specification for: test_gr_falcon_fail_ctxsw_ucode. + * + * Description: Helps to verify the allocation failures for + * nvgpu_gr_falcon_init_ctxsw_ucode function is handled properly. + * + * Test Type: Error injection. + * + * Targets: #nvgpu_gr_falcon_init_ctxsw_ucode. + * + * Input: #test_gr_falcon_init must have been executed successfully. + * + * Steps: + * - Request Kmemory and dma allocation failures at various locations. + * - Call #nvgpu_gr_falcon_init_ctxsw_ucode. + * + * Output: Returns PASS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_gr_falcon_fail_ctxsw_ucode(struct unit_module *m, + struct gk20a *g, void *args); #endif /* UNIT_NVGPU_GR_FALCON_H */ /**