From 9d723a5f1f9e621166fa6f55f1f3d51e92f93fab Mon Sep 17 00:00:00 2001 From: Vedashree Vidwans Date: Wed, 24 Jun 2020 15:09:03 -0700 Subject: [PATCH] gpu: nvgpu: add knob to control fecs_trace feature Currently, NVGPU_SUPPORT_FECS_CTXSW_TRACE enabled flag is set to true when fecs_trace s/w setup is executed successfully. Sometimes, fecs_trace is required to be disabled for debugging. This change will help disable/enable fecs_trace feature by modifying one of the enabled flags. Enable NVGPU_SUPPORT_FECS_CTXSW_TRACE during chip specific hal init. Control fec_trace init and ctxsw dev open depending on NVGPU_SUPPORT_FECS_CTXSW_TRACE flag status. JIRA NVGPU-5616 Change-Id: Id0754a5af7cd95a67a1f0ae5de36115d44e1111b Signed-off-by: Vedashree Vidwans Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2357501 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/fecs_trace.c | 6 +++--- drivers/gpu/nvgpu/common/vgpu/gr/fecs_trace_vgpu.c | 6 ++++-- drivers/gpu/nvgpu/hal/init/hal_gm20b.c | 1 + drivers/gpu/nvgpu/hal/init/hal_gp10b.c | 1 + drivers/gpu/nvgpu/hal/init/hal_gv11b.c | 1 + drivers/gpu/nvgpu/hal/init/hal_tu104.c | 1 + drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c | 4 ++++ drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c | 4 ++++ drivers/gpu/nvgpu/os/linux/fecs_trace_linux.c | 8 +++++++- 9 files changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/fecs_trace.c b/drivers/gpu/nvgpu/common/gr/fecs_trace.c index 365b107ae..0deae927e 100644 --- a/drivers/gpu/nvgpu/common/gr/fecs_trace.c +++ b/drivers/gpu/nvgpu/common/gr/fecs_trace.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -137,12 +137,14 @@ int nvgpu_gr_fecs_trace_init(struct gk20a *g) if (!is_power_of_2(GK20A_FECS_TRACE_NUM_RECORDS)) { nvgpu_err(g, "invalid NUM_RECORDS chosen"); + nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, false); return -EINVAL; } trace = nvgpu_kzalloc(g, sizeof(struct nvgpu_gr_fecs_trace)); if (trace == NULL) { nvgpu_err(g, "failed to allocate fecs_trace"); + nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, false); return -ENOMEM; } g->fecs_trace = trace; @@ -153,8 +155,6 @@ int nvgpu_gr_fecs_trace_init(struct gk20a *g) nvgpu_init_list_node(&trace->context_list); - nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true); - trace->enable_count = 0; return 0; diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/fecs_trace_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/gr/fecs_trace_vgpu.c index 0d121eafb..3ff39b3a6 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gr/fecs_trace_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/gr/fecs_trace_vgpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -42,20 +42,22 @@ int vgpu_fecs_trace_init(struct gk20a *g) nvgpu_log_fn(g, " "); if (g->fecs_trace) { + nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, false); return 0; } vcst = nvgpu_kzalloc(g, sizeof(*vcst)); if (!vcst) { + nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, false); return -ENOMEM; } err = nvgpu_dt_read_u32_index(g, "mempool-fecs-trace", 1, &mempool); if (err) { nvgpu_info(g, "does not support fecs trace"); + nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, false); goto fail; } - nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true); vcst->cookie = vgpu_ivm_mempool_reserve(mempool); if ((vcst->cookie == NULL) || diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index da6617cff..a3cb1be11 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -1222,6 +1222,7 @@ int gm20b_init_hal(struct gk20a *g) #ifdef CONFIG_NVGPU_FECS_TRACE nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false); nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); + nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true); #endif /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c index 48492cf32..a7dfa2f59 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c @@ -1320,6 +1320,7 @@ int gp10b_init_hal(struct gk20a *g) #ifdef CONFIG_NVGPU_FECS_TRACE nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false); nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); + nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true); #endif #ifdef CONFIG_NVGPU_DGPU diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index 3dee6f2f9..140fd5a18 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -1609,6 +1609,7 @@ int gv11b_init_hal(struct gk20a *g) #ifdef CONFIG_NVGPU_FECS_TRACE nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true); nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, true); + nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true); #endif nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 9e17c06fc..e5b0b1143 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -1726,6 +1726,7 @@ int tu104_init_hal(struct gk20a *g) #ifdef CONFIG_NVGPU_FECS_TRACE nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true); nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, true); + nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true); #endif nvgpu_set_enabled(g, NVGPU_SUPPORT_SEC2_RTOS, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_PMU_RTOS_FBQ, true); diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c index c75dabd33..83eb93cc2 100644 --- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c @@ -925,6 +925,10 @@ int vgpu_gp10b_init_hal(struct gk20a *g) gops->fuse = vgpu_gp10b_ops.fuse; gops->top = vgpu_gp10b_ops.top; +#ifdef CONFIG_NVGPU_FECS_TRACE + nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true); +#endif + /* Lone Functions */ gops->chip_init_gpu_characteristics = vgpu_gp10b_ops.chip_init_gpu_characteristics; diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c index 5269f96cb..fed82feb0 100644 --- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c @@ -1045,6 +1045,10 @@ int vgpu_gv11b_init_hal(struct gk20a *g) gops->fuse = vgpu_gv11b_ops.fuse; gops->top = vgpu_gv11b_ops.top; +#ifdef CONFIG_NVGPU_FECS_TRACE + nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true); +#endif + /* Lone functions */ gops->chip_init_gpu_characteristics = vgpu_gv11b_ops.chip_init_gpu_characteristics; diff --git a/drivers/gpu/nvgpu/os/linux/fecs_trace_linux.c b/drivers/gpu/nvgpu/os/linux/fecs_trace_linux.c index 9de09b7ba..66b4975ab 100644 --- a/drivers/gpu/nvgpu/os/linux/fecs_trace_linux.c +++ b/drivers/gpu/nvgpu/os/linux/fecs_trace_linux.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -325,6 +326,11 @@ int gk20a_ctxsw_dev_open(struct inode *inode, struct file *filp) if (!g) return -ENODEV; + if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE)) { + nvgpu_put(&l->g); + return -ENODEV; + } + nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, "g=%p", g); if (!capable(CAP_SYS_ADMIN)) { @@ -576,7 +582,7 @@ int gk20a_ctxsw_trace_init(struct gk20a *g) nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, "g=%p trace=%p", g, trace); /* if tracing is not supported, skip this */ - if (!g->ops.gr.fecs_trace.init) + if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE)) return 0; if (likely(trace))